Data processing method, delay chain unit, delay device, and many-core system

Abstract

The present disclosure provides a data processing method, applied to a delay chain unit, comprising multiple delay buffers; the delay chain unit is applied to a synapse, wherein the synapse corresponds to a predecessor neuron; the method comprises: searching the multiple delay buffers for the firing data of a target neuron, the target neuron being the predecessor neuron corresponding to the synapse; and sequentially connecting the multiple delay buffers to the output of the delay chain unit at intervals of at least one time beat to output the firing data of the target neuron. The present disclosure also provides a delay chain unit, a delay device, and a many-core system.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, a delay chain unit, a delay device, and a many-core system. Background Art

[0002] High-performance brain-inspired computing and brain simulation technologies have become important tools for studying brain science. The development of computational neuroscience has had a significant impact on fields such as intelligence science, cognitive science, information processing, and artificial intelligence. The basic functions of the human brain require the coordinated activity of millions of neurons. More accurate simulations of brain function require larger-scale brain simulation systems.

[0003] Among some related technologies, brain simulation technology still has defects. Summary of the Invention

[0004] The present disclosure provides a data processing method, a delay chain unit, a delay device, and a many-core system.

[0005] In a first aspect, an embodiment of the present disclosure provides a data processing method, which is applied to a delay chain unit, wherein the delay chain unit includes multiple delay buffers; the delay chain unit is applied to a synapse, and the synapse corresponds to a predecessor neuron; the method includes:

[0006] Searching for the firing data of a target neuron from the plurality of delay buffers, the target neuron being the predecessor neuron corresponding to the synapse;

[0007] The plurality of delay buffers are sequentially connected to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the target neuron.

[0008] In some embodiments, before searching for the firing data of the target neuron from the plurality of delay buffers, the method further comprises:

[0009] According to the output buffer and the predetermined number of time beats that the emission data of the target neuron needs to be delayed, the emission data of the target neuron is written into the target buffer, the output buffer is a delay buffer that is connected to the output end of the delay chain unit at the current time beat, and the target buffer is a delay buffer that is connected to the output end of the delay chain unit after the predetermined number of time beats.

[0010] In some embodiments, writing the firing data of the target neuron to the target buffer according to the output buffer and a predetermined number of time beats by which the firing data of the target neuron needs to be delayed comprises:

[0011] Determining a write enable signal corresponding to each of the delay buffers according to the sequence number of the output buffer and the predetermined time beat number, wherein the write enable signal is used to control whether the corresponding delay buffer is writable;

[0012] The firing data of the predecessor neuron is written into the target buffer, wherein the target buffer is one of the plurality of delay buffers that can be written.

[0013] In some embodiments, determining the write enable signal corresponding to each of the delay buffers according to the sequence number of the output buffer and the predetermined time beat number includes:

[0014] A write enable signal corresponding to the first buffer is determined as a first signal, where the first signal is used to control the corresponding delay buffer to be writable, wherein the sequence number of the first buffer satisfies:

[0015] m=(n+1)mod N

[0016] Wherein, m represents the sequence number of the first buffer, n represents the sequence number of the output buffer, l represents the predetermined time number, N represents the total number of delay buffers in the delay chain unit, mod represents a remainder operation, N, l, n, and m are integers, N>1, 0≤n<N, 0≤m<N;

[0017] A write enable signal corresponding to a second buffer is determined as a second signal, where the second signal is used to control the corresponding delay buffer to be non-writable, wherein the second buffer is a delay buffer other than the first buffer in the delay chain unit.

[0018] In some embodiments, sequentially connecting the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the predecessor neuron includes:

[0019] Every time a time beat passes, the delay buffer connected to the output end of the delay chain unit is switched, wherein the sequence number of the delay buffer connected to the output end of the delay chain unit after switching satisfies:

[0020] p=(q+1)mod N

[0021] Wherein, p represents the sequence number of the delay buffer connected to the output end of the delay chain unit after switching, q represents the sequence number of the delay buffer connected to the output end of the delay chain unit before switching, N represents the total number of delay buffers in the delay chain unit, mod represents a remainder operation, N, p, and q are integers, N>1, 0≤p<N, 0≤q<N;

[0022] When the delay buffer connected to the output end of the delay chain unit is a delay buffer storing the firing data of the target neuron, the firing data of the target neuron is output.

[0023] In some embodiments, searching for the firing data of the target neuron from the plurality of delay buffers comprises:

[0024] The firing data of the target neuron is searched from the plurality of delay buffers according to the data access address; wherein the plurality of delay buffers are arranged in parallel.

[0025] In some embodiments, searching for the firing data of the target neuron from the plurality of delay buffers according to the data access address includes:

[0026] According to the data access address, the emission data of the target neuron is read from the storage space corresponding to the target neuron in the delay buffer.

[0027] In some embodiments, a plurality of synapses in a synaptic array are divided into a plurality of groups, each group including a plurality of synapses; synapses in different groups correspond to different successor neurons; and searching for the firing data of the target neuron from the plurality of delay buffers according to the data access address comprises:

[0028] Matching the data access address with identification information of predecessor neurons corresponding to the plurality of synapses stored in the delay buffer, wherein the identification information includes a sequence number of the corresponding predecessor neuron and a group number of the group to which the corresponding successor neuron belongs;

[0029] In the event of a successful match, firing data representing the firing of the target neuron is generated.

[0030] In a second aspect, an embodiment of the present disclosure provides a data processing method, which is applied to a delay device, wherein the delay device includes a weight buffer area and multiple delay chain units, and the delay chain units are used to perform the data processing method described in any one of the first aspects of the embodiments of the present disclosure; the delay device is applied to a synapse array, and the synapse array is used to connect multiple predecessor neurons and multiple successor neurons, and one synapse in the synapse array corresponds to one predecessor neuron and one successor neuron; each time beat includes multiple time steps executed in sequence, and in one time step, the delay device corresponds to one predecessor neuron, and each delay chain unit corresponds to one synapse; for any time step, the method includes:

[0031] Inputting the data access address into each of the delay chain units to obtain the output data of the target neuron corresponding to each of the delay chain units, wherein the target neuron is the predecessor neuron corresponding to the delay device in the current time step;

[0032] Obtaining weight data of a plurality of target synapses from the weight buffer, wherein the target synapses are synapses corresponding to the delay chain units in the current time step;

[0033] According to the output data and weight data corresponding to each of the target synapses in the current time step and the intermediate current value corresponding to each of the target synapses in the previous time step, the intermediate current value corresponding to each of the target synapses in the current time step is determined to obtain the input current values ​​of the current time beat of multiple successor neurons in the last time step of the current time beat.

[0034] In some embodiments, before inputting the data access address into each of the delay chain units to obtain output data of a target neuron corresponding to each of the delay chain units, where the target neuron is the predecessor neuron corresponding to the delay device in the current time step, the method further includes:

[0035] The firing data of the target neuron is written into each of the delay chain units.

[0036] In some embodiments, the delay device further includes a plurality of registers, and the plurality of registers correspond one-to-one to the plurality of delay chain units; determining the intermediate current value corresponding to each of the target synapses in the current time step based on the output data and weight data corresponding to each of the target synapses in the current time step and the intermediate current value corresponding to each of the target synapses in the previous time step includes:

[0037] Corresponding to any one of the target synapses, calculating the product of the output data and the weight data corresponding to the target synapse in the current time step to obtain a weighted current value;

[0038] Reading an intermediate current value corresponding to the target synapse in a previous time step from a register corresponding to the target synapse;

[0039] The sum of the weighted current value and the intermediate current value corresponding to the target synapse in the previous time step is calculated to obtain the intermediate current value of the subsequent neuron corresponding to the target synapse in the current time step.

[0040] In some embodiments, after calculating the sum of the weighted current value and the intermediate current value corresponding to the target synapse in the previous time step to obtain the intermediate current value corresponding to the target synapse in the current time step, the method further includes:

[0041] Writing the intermediate current value corresponding to the target synapse in the current time step into the register corresponding to the target synapse;

[0042] Determine whether the current time step is the last time step of the current time step;

[0043] When the current time step is the last time step of the current time beat, the intermediate current value corresponding to the target synapse stored in the register corresponding to the target synapse is used as the input current of the successor neuron corresponding to the target synapse in the current time beat and output.

[0044] In some embodiments, the synapse array is divided into a plurality of groups, each group including a plurality of synapses; each group corresponds to a plurality of successor neurons, and different groups correspond to different successor neurons; in one time step, the delay device corresponds to one group; for any one time step, before inputting a data access address into each of the delay chain units to obtain output data corresponding to a target neuron of each of the delay chain units, the method further comprises:

[0045] The data access address is determined according to the identifier of the target neuron and the identifier of the group corresponding to the delay device in the current time step.

[0046] In a third aspect, an embodiment of the present disclosure provides a delay chain unit, wherein the delay chain unit is applied to a synapse, wherein the synapse corresponds to a preceding neuron; the delay chain unit comprises:

[0047] Multiple delay buffers;

[0048] a control module configured to search for firing data of a target neuron from the plurality of delay buffers, the target neuron being a predecessor neuron corresponding to the synapse;

[0049] The data selector is configured to sequentially connect the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the target neuron.

[0050] In a fourth aspect, an embodiment of the present disclosure provides a delay device applied to a synapse array, wherein the synapse array is used to connect multiple predecessor neurons and multiple successor neurons, and one synapse in the synapse array corresponds to one predecessor neuron and one successor neuron;

[0051] The delay device comprises:

[0052] Weight cache;

[0053] a plurality of delay chain units, each of which is configured to execute the data processing method according to any one of the first aspects of the embodiments of the present disclosure; each time beat comprising a plurality of time steps executed sequentially, wherein in a time step, the delay device corresponds to one of the preceding neurons, and each of the delay chain units corresponds to one of the synapses;

[0054] The processing module is configured to input the data acquisition address into each of the delay chain units for any time step to obtain the output data of the target neuron corresponding to each of the delay chain units, where the target neuron is the predecessor neuron corresponding to the delay device in the current time step; obtain the weight data of multiple target synapses from the weight buffer area, where the target synapses are the synapses corresponding to the delay chain units in the current time step; determine the intermediate current value corresponding to each of the target synapses in the current time step based on the output data and weight data corresponding to each of the target synapses in the current time step and the intermediate current value corresponding to each of the target synapses in the previous time step, so as to obtain the input current values ​​of the current time beat of multiple successor neurons in the last time step of the current time beat.

[0055] In a fifth aspect, an embodiment of the present disclosure provides a many-core system, including:

[0056] Multiple processing cores;

[0057] an on-chip network configured to exchange data between the plurality of processing cores and external data;

[0058] One or more instructions are stored in one or more of the processing cores, and the one or more instructions are executed by the one or more processing cores to enable the one or more processing cores to implement at least one of the following methods:

[0059] The data processing method according to any one of the first aspects of the embodiments of the present disclosure;

[0060] The data processing method described in any one of the second aspects of the embodiments of the present disclosure.

[0061] The data processing method applied to the delay chain unit provided in the embodiment of the present disclosure connects multiple delay buffers in the delay chain unit for storing the firing data of neurons to the output end of the delay chain unit at intervals of at least one time beat, and can output the firing data of neurons after delaying it for a certain number of time beats, thereby simulating synaptic delay and facilitating further effective simulation of biological neural systems.

[0062] The data processing method applied to the delay device provided by the embodiment of the present disclosure uses a delay chain unit to simulate the delay of each synapse in the synaptic array, and can determine the input current of the successor neuron while delaying the discharge data of the predecessor neuron, thereby realizing effective simulation of the biological nervous system.

[0063] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0065] Figure 1 This is a schematic diagram of the structure of a neuromorphic chip;

[0066] Figure 2 This is a schematic diagram of the structure of the processing core of a neuromorphic chip;

[0067] Figure 3 is a flow chart of a data processing method according to an embodiment of the present disclosure;

[0068] Figure 4 It is a schematic diagram of the relationship between neurons;

[0069] Figure 5 is a schematic structural diagram of a delay chain unit in an embodiment of the present disclosure;

[0070] Figure 6 is a flowchart of some steps in another data processing method in an embodiment of the present disclosure;

[0071] Figure 7 is a flowchart of some steps in another data processing method in an embodiment of the present disclosure;

[0072] Figure 8 is a schematic structural diagram of another delay chain unit in an embodiment of the present disclosure;

[0073] Figure 9 is a schematic diagram of a storage structure of a delay buffer in an embodiment of the present disclosure;

[0074] Figure 10 is a schematic diagram of another storage structure of a delay buffer in an embodiment of the present disclosure;

[0075] Figure 11 is a flow chart of a data processing method according to an embodiment of the present disclosure;

[0076] Figure 12 is a flowchart of some steps in another data processing method in an embodiment of the present disclosure;

[0077] Figure 13 is a schematic diagram of a synapse array according to an embodiment of the present disclosure;

[0078] Figure 14 is a structural diagram of a delay device according to an embodiment of the present disclosure;

[0079] Figure 15 is a block diagram of a delay chain unit in an embodiment of the present disclosure;

[0080] Figure 16 is a block diagram of a delay device according to an embodiment of the present disclosure;

[0081] Figure 17 This is a block diagram of a many-core system in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] To enable those skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0083] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0084] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0085] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0086] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0087] In some related technologies, neural networks are run on neuromorphic chips. Figure 1As shown, the neuromorphic chip includes multiple processing cores 10, each of which has independent computing power and storage space. Figure 2 yes Figure 1 A schematic diagram of the structure of the processing core in the neuromorphic chip shown in FIG. Figure 2 As shown, each processing core usually includes a group (multiple) of neurons, a group of axons, a group of dendrites, and a synaptic array, which can simulate the behavior of a biological neuron cluster. Each processing core in the neuromorphic chip can complete the dendrite integration process and cell body operation process of a corresponding group of neurons. Among them, the dendrite is a structure for receiving external stimuli and generating input current, the axon is a structure for transmitting pulses to the synapses of subsequent neurons, the synapse is a structure for connecting neurons, and the synaptic array is an array composed of multiple synapses, which is used to connect a group of axons and a group of dendrites. For each neuron in the processing core, the dendrite integration calculation process is used to describe the process of integrating the pulse data of all input axons connected to the dendrites of the neuron; the cell body operation process is responsible for updating the membrane potential of the neuron and judging the release of pulses, so that the neuromorphic chip can more accurately simulate the structure in the biological nervous system.

[0088] However, in order to more accurately simulate the functions of the biological nervous system and achieve brain simulation, it is also necessary to effectively simulate neuron delays.

[0089] In view of this, firstly, referring to Figure 3 The present disclosure provides a data processing method applied to a delay chain unit, wherein the delay chain unit includes a plurality of delay buffers; the delay chain unit is applied to a synapse, wherein the synapse corresponds to a predecessor neuron; the method includes:

[0090] S1. Searching for the firing data of a target neuron from multiple delay buffers, where the target neuron is the predecessor neuron corresponding to the synapse;

[0091] S2. Connecting the plurality of delay buffers to the output end of the delay chain unit in sequence at intervals of at least one time beat to output the firing data of the target neuron.

[0092] In an optional embodiment of the present disclosure, the above synapse may also correspond to a predecessor neuron and a successor neuron, and the predecessor neuron and successor neuron may be relative concepts used to describe the connection relationship between the neurons corresponding to the synapse. For example, Figure 4 Schematic diagram of the connection relationship of some neurons in the embodiment of the present disclosure. Figure 4 As shown, multiple neurons A and multiple neurons C are in a fully connected relationship, and multiple neurons A are connected to multiple neurons C through a synaptic array. Among them, for any synapse in the synaptic array, the neuron A corresponding to the synapse is the predecessor neuron, and the neuron C corresponding to the synapse is the successor neuron.

[0093] In the disclosed embodiment, corresponding to a firing of a target neuron, only one of the multiple delay buffers stores the firing data of the target neuron. Accordingly, when executing step S1, the firing data of the target neuron can be searched in each delay buffer, but the firing data of the target neuron can only be found in one of the delay buffers.

[0094] In the embodiment of the present disclosure, at least one time beat is used as an interval, which can be one time beat or multiple time beats. The embodiment of the present disclosure does not specifically limit this. In the embodiment of the present disclosure, when the delay buffer is connected to the output end of the delay chain unit, the data found by the delay buffer through step S1 can be used as the output data of the delay chain unit and output. Corresponding to any time beat, the delay buffer connected to the output end of the delay chain unit can be a delay buffer that stores the release data of the target neuron. The release data of the target neuron can be found through step S1, so the release data of the target neuron is used as the output data of the delay chain unit and output; the delay buffer connected to the output end of the delay chain unit can also be a delay buffer that does not store the release data of the target neuron. The release data of the target neuron is not found through step S1, so the delay buffer will not output the release data of the target neuron.

[0095] It should be noted that, in step S2, the target neuron's firing data is output only when the delay buffer storing the target neuron's firing data is connected to the output of the delay chain unit. If the delay buffer storing the target neuron's firing data is not connected to the output of the delay chain unit, it will take at least one time beat for the delay buffer to connect to the output of the delay chain unit and output the target neuron's firing data. This allows the target neuron's firing data to be delayed by a predetermined number of time beats.

[0096] The embodiments of the present disclosure do not specifically limit the emission data of the target neuron. In some embodiments, the emission data of the target neuron is data that can characterize the emission state of the target neuron (i.e., whether the target neuron is emitted). For example, when the target neuron is emitted, the emission data of the target neuron obtained by searching in step S1 is 1; when the target neuron is not emitted, the emission data of the target neuron obtained by searching in step S1 is 0. In some embodiments, the delay buffer that does not store the emission data of the target neuron has the data obtained by searching in step S1 as 0, which is conducive to further calculating the input current of the subsequent neuron corresponding to the synapse based on the output data output by the delay chain unit.

[0097] The disclosed embodiments do not impose any specific restrictions on the number of delay buffers in a delay chain unit. In some embodiments, the number of delay buffers is determined based on the maximum number of time beats required for delay in the synapse array. For example, if the maximum number of time beats required for delay in the synapse array is N, then the delay chain unit requires N+1 delay buffers.

[0098] Figure 5 This is a schematic diagram of the structure of a delay chain unit in an embodiment of the present disclosure. Figure 5 The data processing method provided in the embodiment of the present disclosure is explained.

[0099] exist Figure 5 In the example, the delay chain unit includes four delay buffers with buffer identifiers BankID 0, 1, 2, and 3, respectively. The data selector MUX selects the data from each delay buffer in BankID order at intervals of one time tick as the output data of the delay chain unit, that is, sequentially connects each delay buffer to the output of the delay chain unit. In the current time tick, the data selector MUX connects the delay buffer with BankID = 1 to the output of the delay chain unit. If the target neuron's firing data is stored in the delay buffer with BankID = 2, the data access address raddr can only find the target neuron's firing data in the delay buffer with BankID = 2, and the target neuron's firing data in the current time tick will not be output. In the next time tick, the data selector MUX connects the delay buffer with BankID = 2 to the output of the delay chain unit, thereby outputting the target neuron's firing data found in the delay buffer with BankID = 2. In other words, the target neuron's firing data is output after being delayed by at least one time tick. Correspondingly, at the current time beat, if the emission data of the target neuron is stored in the delay buffer of BankID=3, it will be output after a delay of at least 2 time beats; if the emission data of the target neuron is stored in the delay buffer of BankID=0, it will be output after a delay of at least 3 time beats; if the emission data of the target neuron is stored in the delay buffer of BankID=1, it will not be delayed and will be output directly.

[0100] It should be noted that, in the embodiment of the present disclosure, a time beat is a fixed duration, and multiple consecutive time beats constitute a continuous duration. The embodiment of the present disclosure does not specifically limit the duration of a time beat.

[0101] The data processing method applied to the delay chain unit provided in the embodiment of the present disclosure connects multiple delay buffers in the delay chain unit for storing the firing data of neurons to the output end of the delay chain unit at intervals of at least one time beat, and can output the firing data of neurons after delaying it for a certain number of time beats, thereby simulating synaptic delay and facilitating further effective simulation of biological neural systems.

[0102] In the embodiment of the present disclosure, corresponding to any time beat, each delay buffer in the delay chain unit corresponds to a different delay time. Figure 5 For example, at the current time beat, if the delay buffer of BankID=1 is turned on to the output end of the delay chain unit, the delay time corresponding to the delay buffer of BankID=1 is 0 time beats, the delay time corresponding to the delay buffer of BankID=2 is 1 time beat, the delay time corresponding to the delay buffer of BankID=3 is 2 time beats, and the delay time corresponding to the delay buffer of BankID=0 is 3 time beats; at the current time beat, if the delay buffer of BankID=0 is turned on to the output end of the delay chain unit, the delay time corresponding to the delay buffer of BankID=0 is 0 time beats, the delay time corresponding to the delay buffer of BankID=1 is 1 time beat, the delay time corresponding to the delay buffer of BankID=2 is 2 time beats, and the delay time corresponding to the delay buffer of BankID=3 is 3 time beats.

[0103] In some embodiments, the firing data of different neurons in a synapse may require the same or different delay times; the firing data of the same neuron at different times may require the same or different delay times. In some embodiments, the firing data of a neuron may be delayed by a corresponding number of beats by writing the firing data of the neuron into a delay buffer that meets the delay requirements of the firing data of the neuron.

[0104] Accordingly, in some embodiments, reference Figure 6 Before step S1, the method further includes:

[0105] S3. According to the predetermined number of time beats that the emission data of the target neuron needs to be delayed between the output buffer and the target neuron, the emission data of the target neuron is written into the target buffer. The output buffer is a delay buffer that is connected to the output end of the delay chain unit at the current time beat, and the target buffer is a delay buffer that is connected to the output end of the delay chain unit after the predetermined number of time beats.

[0106] In the embodiment of the present disclosure, through step S3, the firing data of the target neuron can be written into a delay buffer that meets the delay requirement of the target neuron firing data, thereby delaying the firing data of the target neuron by a corresponding number of time beats.

[0107] by Figure 5 For example, at the current time, the delay buffer of BankID=1 is connected to the output of the delay chain unit, that is, the delay buffer of BankID=1 is the output buffer. If the target neuron’s release data x i If a delay of 1 time beat is required, the delay buffer of BankID=2 is the target buffer, and the release data x of the target neuron is i Write to the delay buffer of BankID=2; if the target neuron’s release data x i If a delay of 2 time beats is required, the delay buffer of BankID=3 is the target buffer, and the release data x of the target neuron is i Write to the delay buffer of BankID=3; if the target neuron’s release data x i If a delay of 3 time beats is required, the delay buffer of BankID=0 is the target buffer, and the release data x of the target neuron is i Write to the delay buffer of BankID=0; if the target neuron’s release data x i If a delay of 0 time beats is required, the delay buffer of BankID=1 is the target buffer, and the release data x of the target neuron is i Write to the delay buffer of BankID=1.

[0108] It should be noted that, in the embodiment of the present disclosure, step S3 and step S2 can be executed at the same time beat. For example, at the current time beat, the target neuron is fired, and the firing data of the target neuron is written into the delay chain unit by executing step S3; then, at the current time beat, it is determined by executing step S2 whether the firing data of the target neuron is output at the current time beat. In some embodiments, step S3 and step S2 can also be executed at different time beats. For example, the target neuron is fired at the previous time beat, and the firing data of the target neuron has been written into the delay chain unit by executing step S3. At the current time beat, it is determined by executing step S2 whether the firing data of the target neuron is output at the current time beat.

[0109] The disclosed embodiments do not specifically limit how the target neuron's firing data is written to the target buffer. In some embodiments, the target buffer is first determined based on the output buffer and the predetermined number of beats by which the target neuron's firing data needs to be delayed, and then the target neuron's firing data is directly written to the target buffer. In some embodiments, the target neuron's firing data is written to each delay buffer simultaneously, and the writability of each delay buffer is controlled based on the output buffer and the predetermined number of beats by which the target neuron's firing data needs to be delayed, so that only the target buffer is writable, thereby writing only the target neuron's firing data to the target buffer.

[0110] Accordingly, in some embodiments, reference Figure 7 , step S3 includes:

[0111] S31, determining a write enable signal corresponding to each delay buffer according to the sequence number of the output buffer and the predetermined time beat number, where the write enable signal is used to control whether the corresponding delay buffer is writable;

[0112] S32. Writing the emission data of the preceding neuron into a target buffer, wherein the target buffer is one of the multiple delay buffers that can be written.

[0113] In the embodiment of the present disclosure, through steps S31 to S32, by controlling whether each delay buffer is writable, the emission data of the predecessor neuron can be written into the target buffer that meets the delay requirements, thereby eliminating the need to calculate the corresponding target buffer for each predecessor neuron separately, which is beneficial to reducing the amount of calculation and improving processing efficiency.

[0114] Figure 8 Schematic diagram of another delay chain unit in the embodiment of the present disclosure. In the embodiment of the present disclosure, i is the serial number of the preceding neuron, j is the serial number of the succeeding neuron, and the quadruple (W i，j , d i，j , i, j) represents the synapse connecting the predecessor neuron with sequence number i and the successor neuron with sequence number j, W i，j is the synaptic weight data, d i，j is the predetermined time number that the synapse needs to delay. In the embodiment of the present disclosure, the buffer identifier BankID of the delay buffer is the serial number of the delay buffer, and curr represents the serial number of the output buffer. Figure 8 As shown, multiple write control modules DEC0, DEC1, DEC2, and DEC3 correspond to four delay buffers with BankIDs 0, 1, 2, and 3, respectively. i，j )mod N=BankID, the write control module outputs the write enable signal 1, so that the corresponding delay buffer can be written; i，j ) When mod N ≠ BankID, the write control module outputs a write enable signal of 0, making the corresponding delay buffer unwritable. Where N represents the total number of delay buffers in the delay chain unit, and mod represents a modulo operation.

[0115] At the current time, the delay buffer with BankID=1 is connected to the output of the delay chain unit, that is, the sequence number of the output buffer is curr=1, and the target neuron's emission data x is written to each delay buffer at the same time according to the write address waddr. i If the target neuron's emission data x i Requires delay i，j=1 time beat, then the write control module DEC2 corresponding to the delay buffer of BankID=2 outputs 1, making the delay buffer of BankID=2 writable, and the write control modules DEC0, DEC1, and DEC3 output 0, making the delay buffers of BankID=3, BankID=0, and BankID=1 unwritable, thereby only the emission data x of the target neuron is written. i Write to the delay buffer of BankID=2; if the target neuron’s release data x i Requires delay i，j =3 time beats, then the write control module DEC0 corresponding to the delay buffer of BankID=0 outputs 1, making the delay buffer of BankID=0 writable, and the write control modules DEC1, DEC2, and DEC3 output 0, making the delay buffers of BankID=1, BankID=2, and BankID=3 unwritable, thereby only the firing data x of the target neuron is written. i Write to the delay buffer of BankID=0.

[0116] Accordingly, in some embodiments, determining the write enable signal corresponding to each delay buffer according to the sequence number of the output buffer and the predetermined time beat number includes:

[0117] The write enable signal corresponding to the first buffer is determined as the first signal, and the first signal is used to control the corresponding delay buffer to be writable, wherein the sequence number of the first buffer satisfies:

[0118] m=(n+1)modN

[0119] Wherein, m represents the serial number of the first buffer, n represents the serial number of the output buffer, l represents the number of predetermined time beats, N represents the total number of delay buffers in the delay chain unit, mod represents a modulo operation, N, l, n, and m are integers, N>1, 0≤n<N, 0≤m<N;

[0120] The write enable signal corresponding to the second buffer is determined as the second signal, and the second signal is used to control the corresponding delay buffer to be non-writable, wherein the second buffer is a delay buffer other than the first buffer in the delay chain unit.

[0121] In the embodiment of the present disclosure, through the above-mentioned process of determining the write enable signal corresponding to each delay buffer according to the sequence number of the output buffer and the predetermined number of time beats, each delay buffer can be cycled and used as the target buffer in turn, so that a limited number of delay buffers can be reused to achieve the output of the neuron's emission data after delaying it for a certain number of time beats.

[0122] Accordingly, in some embodiments, sequentially connecting a plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the successor neuron includes:

[0123] After each time beat, the delay buffer connected to the output end of the delay chain unit is switched, wherein the sequence number of the delay buffer connected to the output end of the delay chain unit after switching satisfies:

[0124] p=(q+1)modN, where p represents the sequence number of the delay buffer connected to the output end of the delay chain unit after switching, q represents the sequence number of the delay buffer connected to the output end of the delay chain unit before switching, N represents the total number of delay buffers in the delay chain unit, mod represents a remainder operation, N, p, and q are integers, N>1, 0≤p<N, and 0≤q≤N;

[0125] When the delay buffer connected to the output end of the delay chain unit is the delay buffer storing the firing data of the target neuron, the firing data of the target neuron is output.

[0126] In the embodiment of the present disclosure, through the above-mentioned process of sequentially connecting multiple delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the release data of the predecessor neuron, each delay buffer can be circulated and sequentially connected to the output end of the delay chain unit, so that a limited number of delay buffers can be multiplexed to achieve the output of the neuron's release data after delaying it for a certain number of time beats.

[0127] like Figure 8 As shown, if the current time is beat, the delay buffer of BankID=1 is turned on to the output end of the delay chain unit, and the next time is beat, the delay buffer of BankID=2 is turned on to the output end of the delay chain unit; if the current time is beat, the delay buffer of BankID=3 is turned on to the output end of the delay chain unit, and the next time is beat, the delay buffer of BankID=0 is turned on to the output end of the delay chain unit.

[0128] The disclosed embodiment does not impose any special limitation on how to search for the firing data of the target neuron from multiple delay buffers.

[0129] In some embodiments, searching for firing data of a target neuron from a plurality of delay buffers includes:

[0130] The firing data of the target neuron is searched from a plurality of delay buffers according to the data access address; wherein the plurality of delay buffers are arranged in parallel.

[0131] In the embodiment of the present disclosure, the firing data of the target neuron is searched from multiple delay buffers according to the data access address, so that the firing data of different neurons can be stored in the delay buffer, which is conducive to the reuse of the delay chain unit.

[0132] The present disclosure does not impose any special restrictions on the storage structure of the delay buffer. In some embodiments, the storage structure of the delay buffer is a dense storage structure. For example, Figure 9 As shown in the figure, in the delay buffer, each successor neuron i has an independent storage space. When the current successor neuron i fires, the corresponding storage space stores the firing data 1; when the current successor neuron i does not fire, the corresponding storage space stores the firing data 0. 1 represents a valid event of the previous successor neuron firing, and 0 represents an invalid event of the previous successor neuron not firing.

[0133] Accordingly, in some embodiments, searching for the firing data of the target neuron from the plurality of delay buffers according to the data access address includes:

[0134] According to the data access address, the emission data of the target neuron is read from the storage space corresponding to the target neuron in the delay buffer.

[0135] In the embodiment of the present disclosure, through the above process, it is achieved that data access is issued when the storage structure of the delay buffer is a dense storage structure.

[0136] In some embodiments, the storage structure of the delay buffer is a sparse storage structure. Figure 10 As shown, in the delay buffer, only the identification information of the predecessor neuron corresponding to the valid event is stored, where the valid event refers to the firing of the predecessor neuron. The multiple synapses in the synaptic array are divided into multiple groups, each group includes multiple synapses; each group corresponds to multiple successor neurons, and different groups correspond to different successor neurons; Figure 10 In the , a binary group (i, Gid) is used as the identification information of the predecessor neuron, i is the identification of the predecessor neuron, and Gid is the identification of the group to which the successor neuron belongs after the multiple synapses in the synaptic array are divided into multiple groups.

[0137] Accordingly, in some embodiments, the plurality of synapses in the synaptic array are divided into a plurality of groups, each group including a plurality of synapses; the synapses in different groups correspond to different successor neurons; and searching for the firing data of the target neuron from the plurality of delay buffers according to the data access address includes:

[0138] Matching the data access address with identification information of predecessor neurons corresponding to the plurality of synapses stored in the delay buffer, wherein the identification information includes a sequence number of the corresponding predecessor neuron and a group number of the group to which the corresponding successor neuron belongs;

[0139] In the event of a successful match, firing data is generated that characterizes the firing of the target neuron.

[0140] In the embodiment of the present disclosure, through the above process, it is achieved that when the storage structure of the delay buffer is a sparse storage structure, data access is issued. The use of a sparse storage structure can save storage resources.

[0141] In some embodiments, if the match is successful, the emission data 1 is generated. It should be noted that if the match fails, indicating that the identification information of the target neuron is not stored in the delay buffer or the target neuron does not emit, the emission data 0 is generated.

[0142] The disclosed embodiments do not specifically limit the access address. In some embodiments, the access address includes the identifier of the target neuron. In some embodiments, the plurality of synapses in the synaptic array are divided into a plurality of groups, and the access address includes the sequence number of the target neuron and the group number of the group to which the target neuron belongs.

[0143] Secondly, refer to Figure 11 The present disclosure provides a data processing method applied to a delay device, the delay device including a weight buffer and a plurality of delay chain units; the delay device is applied to a synapse array, the synapse array is used to connect a plurality of predecessor neurons and a plurality of successor neurons, and a synapse in the synapse array corresponds to a predecessor neuron and a successor neuron; each time beat includes a plurality of time steps executed sequentially, and in a time step, the delay device corresponds to a predecessor neuron, and each delay chain unit corresponds to a synapse; for any time step, the method includes:

[0144] S4. Input the data access address into each delay chain unit to obtain the output data of the target neuron corresponding to each delay chain unit, where the target neuron is the predecessor neuron corresponding to the delay device in the current time step;

[0145] S5. Obtain weight data of multiple target synapses from the weight buffer, where the target synapses are synapses corresponding to the delay chain units in the current time step;

[0146] S6. Determine the intermediate current value corresponding to each target synapse in the current time step based on the output data and weight data corresponding to each target synapse in the current time step and the intermediate current value corresponding to each target synapse in the previous time step, so as to obtain the input current value of the current time beat of multiple successor neurons in the last time step of the current time beat.

[0147] It should be noted that, in the embodiment of the present disclosure, the delay chain unit in the delay device can delay the firing data of the target neuron for a predetermined number of time beats before outputting it according to the data processing method of the first aspect of the embodiment of the present disclosure.

[0148] It should be noted that, in one time step, the delay device corresponds to a preceding neuron, and each delay chain unit corresponds to a synapse, wherein the synapse corresponding to the delay chain unit is the synapse corresponding to the preceding neuron.

[0149] The disclosed embodiments do not impose any particular restrictions on the number of delay chain units in the delay device. In some embodiments, the number of delay chain units in the delay device is determined in relation to the number of synapses in the synapse array. For example, the number of delay chain units in the delay device can be 4, 16, 32, or the like.

[0150] It should be noted that by executing steps S4 to S6 at multiple time steps in a time beat, when the synaptic array performs delayed processing on the firing data of each successor neuron, an integral calculation process of the firing data of all successor neurons is performed for any successor neuron.

[0151] The data processing method applied to the delay device provided by the embodiment of the present disclosure uses a delay chain unit to simulate the delay of each synapse in the synaptic array, and can determine the input current of the successor neuron while delaying the discharge data of the predecessor neuron, thereby realizing effective simulation of the biological nervous system.

[0152] In some embodiments, reference Figure 12 , before step S4, for any time step, the method further includes:

[0153] S7. Write the firing data of the target neuron into each delay chain unit.

[0154] In the embodiment of the present disclosure, through step S7, the firing data of the target neuron can be written into a delay buffer that meets the delay requirement of the target neuron firing data, thereby delaying the firing data of the target neuron by a corresponding number of time beats.

[0155] In the disclosed embodiment, step S7 and step S4 can be executed at the same time. For example, at the current time, the target neuron fires, and step S7 is executed to write the target neuron's firing data into each delay chain unit; then, at the current time, step S4 is executed to obtain the output data of each delay chain unit. In some embodiments, step S7 and step S4 can also be executed at different time. For example, if the target neuron fires at the previous time, and step S7 has already written the target neuron's firing data into each delay chain unit, at the current time, step S4 is executed to obtain the output data of each delay chain unit.

[0156] In some embodiments, the delay device further includes a plurality of registers, each of which corresponds to a plurality of delay chain units. Determining the intermediate current value corresponding to each target synapse in the current time step based on the output data and weight data corresponding to each target synapse in the current time step and the intermediate current value corresponding to each target synapse in the previous time step includes:

[0157] For any target synapse, calculate the product of the output data and weight data corresponding to the target synapse in the current time step to obtain the weighted current value;

[0158] Read the intermediate current value corresponding to the target synapse in the previous time step from the register corresponding to the target synapse;

[0159] The sum of the weighted current value and the intermediate current value corresponding to the target synapse in the previous time step is calculated to obtain the intermediate current value of the subsequent neuron corresponding to the target synapse in the current time step.

[0160] In an embodiment of the present disclosure, the above process is performed in multiple time steps of a time beat, thereby obtaining the input current values ​​of multiple successor neurons in the last time step of the time beat. In some embodiments, after calculating the sum of the weighted current value and the intermediate current value corresponding to the target synapse in the previous time step to obtain the intermediate current value corresponding to the target synapse in the current time step, the above method further includes:

[0161] Write the intermediate current value corresponding to the target synapse in the current time step into the register corresponding to the target synapse;

[0162] Determine whether the current time step is the last time step of the current time step;

[0163] When the current time step is the last time step of the current time beat, the intermediate current value corresponding to the target synapse stored in the register corresponding to the target synapse is used as the input current of the successor neuron corresponding to the target synapse of the current time beat and output.

[0164] In the embodiment of the present disclosure, by executing the above process in multiple time steps of a time beat, the input current values ​​of multiple successor neurons can be obtained and output in the last time step of the time beat.

[0165] In some embodiments, the synapse array is divided into a plurality of groups, each group including a plurality of synapses; each group corresponds to a plurality of successor neurons, and different groups correspond to different successor neurons; in one time step, a delay device corresponds to one group; for any one time step, before inputting a data access address into each delay chain unit to obtain output data corresponding to a target neuron of each delay chain unit, the method further comprises:

[0166] The data access address is determined according to the identifier of the target neuron and the identifier of the group corresponding to the current time step delay device.

[0167] In the embodiment of the present disclosure, delay device multiplexing can be achieved through the above process.

[0168] It should be noted that in one time step, the delay device corresponds to a predecessor neuron, each delay chain unit corresponds to a synapse, and the delay device corresponds to a group, wherein the synapse corresponding to the delay chain unit in the delay device is the synapse corresponding to the predecessor neuron and belonging to the group.

[0169] Figure 13 is a schematic diagram of grouping synapse arrays in an embodiment of the present disclosure. Figure 14 This is a schematic diagram of the structure of a delay device in an embodiment of the present disclosure. Figure 13 、 Figure 14 The data processing method provided in the embodiment of the present disclosure is explained.

[0170] In the embodiment of the present disclosure, i is the serial number of the preceding neuron, j is the serial number of the succeeding neuron, and the quadruple (W i，j , d i，j , i, j) represents the synapse connecting the predecessor neuron with sequence number i and the successor neuron with sequence number j, W i，j is the synaptic weight data, d i，j is the predetermined time number that the synapse needs to delay. The input current value of the successor neuron with sequence number j can be expressed as:

[0171]

[0172] Among them, x i Represents the firing data of the preceding neuron.

[0173] like Figure 13 As shown, the synaptic array is divided into two groups, Gid=0 and Gid=1. The group Gid=0 corresponds to the successor neurons with serial numbers 0, 1, 2, and 3, and the group Gid=1 corresponds to the successor neurons with serial numbers 4, 5, 6, and 7.

[0174] like Figure 14As shown, the delay device includes a weight buffer and four delay chain units. In any time step, the four delay chains in the delay device correspond to the synapses of a predecessor neuron in a group. In a time step, the processing process of the delay device includes: reading the weight data of the synapses corresponding to each delay chain from the weight buffer according to the data access address, the delay chain delays the release data of the predecessor neuron to obtain output data, uses a multiplier to calculate the product of the weight data and the output data to obtain a weighted current value, and uses an adder to calculate the weighted current value and the intermediate current value of the previous time step stored in the register (reg) to obtain the intermediate current value of the current time step, and then writes the intermediate current value of the current time step into reg.

[0175] In a time beat, the processing process of the delay device includes: in the first time step, calculating the intermediate current values ​​of the four synapses that satisfy i=0 and Gid=0; in the second time step, calculating the intermediate current values ​​of the four synapses that satisfy i=1 and Gid=0; in the third time step, calculating the intermediate current values ​​of the four synapses that satisfy i=2 and Gid=0; in the fourth time step, calculating the intermediate current values ​​of the four synapses that satisfy i=3 and Gid=0, and obtaining the successor numbers 0, 1, 2, and 3 corresponding to the group of Gid=0. The input current value of the neuron; in the fifth time step, the intermediate current value of the four synapses satisfying i=0 and Gid=1 is calculated; in the sixth time step, the intermediate current value of the four synapses satisfying i=1 and Gid=1 is calculated; in the seventh time step, the intermediate current value of the four synapses satisfying i=2 and Gid=1 is calculated; in the eighth time step, the intermediate current value of the four synapses satisfying i=3 and Gid=1 is calculated, and the input current values ​​of the successor neurons numbered 4, 5, 6, and 7 corresponding to the group of Gid=1 are obtained.

[0176] Thirdly, refer to Figure 15 The present disclosure provides a delay chain unit, which is applied to a synapse, where the synapse corresponds to a preceding neuron. The delay chain unit includes:

[0177] a plurality of delay buffers 101;

[0178] The control module 102 is configured to search for the firing data of the target neuron from the plurality of delay buffers 101 , where the target neuron is the predecessor neuron corresponding to the synapse;

[0179] The data selector 103 is configured to sequentially connect the plurality of delay buffers 101 to the output terminals of the delay chain units at intervals of at least one time beat, so as to output the firing data of the target neuron.

[0180] Fourthly, refer to Figure 16 , an embodiment of the present disclosure provides a delay device, which is applied to a synapse array, the synapse array being used to connect a plurality of predecessor neurons and a plurality of successor neurons, wherein one synapse in the synapse array corresponds to one predecessor neuron and one successor neuron;

[0181] Delay devices include:

[0182] Weight buffer 201;

[0183] Multiple delay chain units 202, each delay chain unit 202 is configured to execute the data processing method according to any one of the first aspects of the embodiments of the present disclosure; each time beat includes multiple time steps executed sequentially, and in one time step, the delay device corresponds to a preceding neuron, and each delay chain unit 202 corresponds to a synapse;

[0184] The processing module 203 is configured to input the data acquisition address into each delay chain unit 202 for any time step, obtain the output data of the target neuron corresponding to each delay chain unit 202, and the target neuron is the predecessor neuron corresponding to the delay device in the current time step; obtain the weight data of multiple target synapses from the weight buffer area 201, and the target synapse is the synapse corresponding to the delay chain unit 202 in the current time step; determine the intermediate current value corresponding to each target synapse in the current time step based on the output data and weight data corresponding to each target synapse in the current time step and the intermediate current value corresponding to each target synapse in the previous time step, so as to obtain the input current value of the current time beat of multiple successor neurons in the last time step of the current time beat.

[0185] Fifth, refer to Figure 17 The embodiment of the present disclosure provides a many-core system, including: multiple processing cores 301 and an on-chip network 302, wherein the multiple processing cores 301 are connected to the on-chip network 302, and the on-chip network 302 is used to exchange data between the multiple processing cores and external data.

[0186] Among them, one or more instructions are stored in one or more processing cores 301, and one or more instructions are executed by one or more processing cores 301, so that one or more processing cores 301 can implement the data processing method of the first aspect of the embodiment of the present disclosure and / or the data processing method of the second aspect of the embodiment of the present disclosure.

[0187] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0188] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data processing method, applied to a delay chain unit, wherein the delay chain unit includes a plurality of delay buffers; the delay chain unit is applied to a synapse, wherein the synapse corresponds to a preceding neuron; the method comprising: Searching for the firing data of a target neuron from the plurality of delay buffers, the target neuron being the predecessor neuron corresponding to the synapse; sequentially connecting the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the target neuron; The step of sequentially connecting the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the target neuron includes: When the delay buffer storing the firing data of the target neuron is connected to the output end of the delay chain unit, the firing data of the target neuron is output; when the delay buffer storing the firing data of the target neuron is not connected to the output end of the delay chain unit, after at least one time beat, the delay buffer storing the firing data of the target neuron is connected to the output end of the delay chain unit to output the firing data of the target neuron.

2. The data processing method according to claim 1, wherein: Before searching for the firing data of the target neuron from the plurality of delay buffers, the method further includes: According to the output buffer and the predetermined number of time beats that the emission data of the target neuron needs to be delayed, the emission data of the target neuron is written into the target buffer, the output buffer is a delay buffer that is connected to the output end of the delay chain unit at the current time beat, and the target buffer is a delay buffer that is connected to the output end of the delay chain unit after the predetermined number of time beats.

3. The data processing method according to claim 2, wherein: Writing the emission data of the target neuron into the target buffer according to the output buffer and the predetermined time number of beats by which the emission data of the target neuron needs to be delayed includes: Determining a write enable signal corresponding to each of the delay buffers according to the sequence number of the output buffer and the predetermined time beat number, wherein the write enable signal is used to control whether the corresponding delay buffer is writable; The firing data of the predecessor neuron is written into the target buffer, wherein the target buffer is one of the plurality of delay buffers that can be written.

4. The data processing method according to claim 3, wherein: Determining a write enable signal corresponding to each of the delay buffers according to the sequence number of the output buffer and the predetermined time beat number includes: A write enable signal corresponding to the first buffer is determined as a first signal, where the first signal is used to control the corresponding delay buffer to be writable, wherein the sequence number of the first buffer satisfies: m=(n+1)mod N Wherein, m represents the serial number of the first buffer, n represents the serial number of the output buffer, l represents the predetermined time number, N represents the total number of delay buffers in the delay chain unit, mod represents the remainder operation, N, l, n, m are integers, N>1, 0≤n <N,0≤m<N; A write enable signal corresponding to a second buffer is determined as a second signal, where the second signal is used to control the corresponding delay buffer to be non-writable, wherein the second buffer is a delay buffer other than the first buffer in the delay chain unit.

5. The data processing method according to any one of claims 1 to 4, wherein: The method of sequentially connecting the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the predecessor neuron comprises: Every time a time beat passes, the delay buffer connected to the output end of the delay chain unit is switched, wherein the sequence number of the delay buffer connected to the output end of the delay chain unit after switching satisfies: p=(q+1)mod N Wherein, p represents the sequence number of the delay buffer connected to the output end of the delay chain unit after switching, q represents the sequence number of the delay buffer connected to the output end of the delay chain unit before switching, N represents the total number of delay buffers in the delay chain unit, mod represents the remainder operation, N, p, q are integers, N>1, 0≤p <N,0≤q<N; When the delay buffer connected to the output end of the delay chain unit is a delay buffer storing the firing data of the target neuron, the firing data of the target neuron is output.

6. The data processing method according to any one of claims 1 to 4, wherein: Searching for the firing data of the target neuron from the plurality of delay buffers includes: The firing data of the target neuron is searched from the plurality of delay buffers according to the data access address; wherein the plurality of delay buffers are arranged in parallel.

7. The data processing method according to claim 6, wherein: Searching for the emission data of the target neuron from the plurality of delay buffers according to the data access address includes: According to the data access address, the emission data of the target neuron is read from the storage space corresponding to the target neuron in the delay buffer.

8. The data processing method according to claim 6, wherein: The plurality of synapses in the synaptic array are divided into a plurality of groups, each group including a plurality of synapses; Synapses in different groups correspond to different subsequent neurons; Searching for the emission data of the target neuron from the plurality of delay buffers according to the data access address includes: Matching the data access address with identification information of predecessor neurons corresponding to the plurality of synapses stored in the delay buffer, wherein the identification information includes a sequence number of the corresponding predecessor neuron and a group number of the group to which the corresponding successor neuron belongs; In the event of a successful match, firing data representing the firing of the target neuron is generated.

9. A data processing method, applied to a delay device, the delay device comprising a weight buffer and a plurality of delay chain units, the delay chain units being configured to execute the data processing method according to any one of claims 1 to 8; the delay device being applied to a synapse array, the synapse array being configured to connect a plurality of predecessor neurons and a plurality of successor neurons, wherein one synapse in the synapse array corresponds to one predecessor neuron and one successor neuron; each time beat comprising a plurality of time steps executed sequentially, wherein in one time step, the delay device corresponds to one predecessor neuron, and each delay chain unit corresponds to one synapse; for any one time step, the method comprising: Inputting the data access address into each of the delay chain units to obtain the output data of the target neuron corresponding to each of the delay chain units, wherein the target neuron is the predecessor neuron corresponding to the delay device in the current time step; Obtaining weight data of a plurality of target synapses from the weight buffer, wherein the target synapses are synapses corresponding to the delay chain units in the current time step; According to the output data and weight data corresponding to each of the target synapses in the current time step and the intermediate current value corresponding to each of the target synapses in the previous time step, the intermediate current value corresponding to each of the target synapses in the current time step is determined to obtain the input current values ​​of the current time beat of multiple successor neurons in the last time step of the current time beat.

10. The method according to claim 9, wherein: Before inputting the data access address into each of the delay chain units to obtain output data of a target neuron corresponding to each of the delay chain units, where the target neuron is the predecessor neuron corresponding to the delay device in the current time step, the method further includes: The firing data of the target neuron is written into each of the delay chain units.

11. The method according to claim 9 or 10, wherein: The delay device further includes a plurality of registers, each of the registers corresponding to the plurality of delay chain units on a one-to-one basis; determining an intermediate current value corresponding to each of the target synapses in the current time step based on the output data and weight data corresponding to each of the target synapses in the current time step and the intermediate current value corresponding to each of the target synapses in the previous time step, including: Corresponding to any one of the target synapses, calculating the product of the output data and the weight data corresponding to the target synapse in the current time step to obtain a weighted current value; Reading an intermediate current value corresponding to the target synapse in a previous time step from a register corresponding to the target synapse; The sum of the weighted current value and the intermediate current value corresponding to the target synapse in the previous time step is calculated to obtain the intermediate current value of the subsequent neuron corresponding to the target synapse in the current time step.

12. The method according to claim 11, wherein After calculating the sum of the weighted current value and the intermediate current value corresponding to the target synapse in the previous time step to obtain the intermediate current value corresponding to the target synapse in the current time step, the method further includes: Writing the intermediate current value corresponding to the target synapse in the current time step into the register corresponding to the target synapse; Determine whether the current time step is the last time step of the current time step; When the current time step is the last time step of the current time beat, the intermediate current value corresponding to the target synapse stored in the register corresponding to the target synapse is used as the input current of the successor neuron corresponding to the target synapse in the current time beat and output.

13. The method according to claim 9 or 10, wherein: The synapse array is divided into a plurality of groups, each group including a plurality of synapses; each group corresponds to a plurality of successor neurons, and different groups correspond to different successor neurons; in one time step, the delay device corresponds to one group; for any one time step, before inputting a data access address into each of the delay chain units to obtain output data corresponding to a target neuron of each of the delay chain units, the method further comprises: The data access address is determined according to the identifier of the target neuron and the identifier of the group corresponding to the delay device in the current time step.

14. A delay chain unit, wherein the delay chain unit is applied to a synapse, wherein the synapse corresponds to a preceding neuron; The delay chain unit comprises: Multiple delay buffers; a control module configured to search for firing data of a target neuron from the plurality of delay buffers, the target neuron being a predecessor neuron corresponding to the synapse; a data selector configured to sequentially connect the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat, so as to output the firing data of the target neuron; The step of sequentially connecting the plurality of delay buffers to the output end of the delay chain unit at intervals of at least one time beat to output the firing data of the target neuron includes: When the delay buffer storing the firing data of the target neuron is connected to the output end of the delay chain unit, the firing data of the target neuron is output; when the delay buffer storing the firing data of the target neuron is not connected to the output end of the delay chain unit, after at least one time beat, the delay buffer storing the firing data of the target neuron is connected to the output end of the delay chain unit to output the firing data of the target neuron.

15. A delay device, applied to a synapse array, wherein the synapse array is used to connect a plurality of predecessor neurons and a plurality of successor neurons, wherein one synapse in the synapse array corresponds to one predecessor neuron and one successor neuron; The delay device comprises: Weight cache; a plurality of delay chain units, wherein the delay chain units are configured to execute the data processing method according to any one of claims 1 to 8; Each time beat includes a plurality of time steps executed sequentially, in which the delay device corresponds to one of the preceding neurons, and each of the delay chain units corresponds to one of the synapses; The processing module is configured to input the data acquisition address into each of the delay chain units for any time step to obtain the output data of the target neuron corresponding to each of the delay chain units, where the target neuron is the predecessor neuron corresponding to the delay device in the current time step; obtain the weight data of multiple target synapses from the weight buffer area, where the target synapses are the synapses corresponding to the delay chain units in the current time step; determine the intermediate current value corresponding to each of the target synapses in the current time step based on the output data and weight data corresponding to each of the target synapses in the current time step and the intermediate current value corresponding to each of the target synapses in the previous time step, so as to obtain the input current values ​​of the current time beat of multiple successor neurons in the last time step of the current time beat.

16. A many-core system comprising: Multiple processing cores; an on-chip network configured to exchange data between the plurality of processing cores and external data; One or more instructions are stored in one or more of the processing cores, and the one or more instructions are executed by the one or more processing cores to enable the one or more processing cores to implement at least one of the following methods: The data processing method according to any one of claims 1 to 8; A method for data processing according to any one of claims 9 to 13.

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