Data processing device, method, chip, board, electronic device and storage medium

Abstract

The present disclosure provides a data processing device, method, chip, board, electronic device and storage medium, characterized in that it includes: a control unit and a conversion processing unit; the control unit is used to generate a first instruction stream based on a preset data element reading order in response to receiving a data processing instruction, and send the first instruction stream to the conversion processing unit; the conversion processing unit is used to read a first data element in the to-be-processed data from a preset storage space based on the data element reading order indicated by the first instruction stream in response to receiving the first instruction stream, and store the read first data element in a register stack; after the first data element stored in the register stack meets a preset conversion condition, the first data element is converted to obtain a second data element; wherein each second data element is obtained by converting multiple first data elements, and the number of registers in the register stack is determined based on the data element reading order.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a data processing device, method, chip, board, electronic device and storage medium. Background Art

[0002] As convolutional neural networks are increasingly used in computer vision, speech recognition, natural language processing, and other fields, fast convolution takes advantage of the data reuse in its calculation process and reduces the time-consuming multiplication operations by adding a small number of addition / subtraction operations. When the convolution kernel size is small, it can effectively improve the running speed of the convolution network. Therefore, it is widely used in convolution networks with small-sized convolution kernels (such as 3*3 or 5*5 convolution kernels).

[0003] Fast convolution often requires an additional cache in the pre-processing phase to ensure simultaneous access to multiple data points in the input block. This is typically implemented using registers. The increased number of registers in this cache impacts the area of ​​the data processing chip. Summary of the Invention

[0004] The embodiments of the present disclosure provide at least one data processing device, method, chip, board, electronic device, and storage medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a data processing device, including: a control unit and a conversion processing unit.

[0006] The control unit is configured to, in response to receiving a data processing instruction, generate a first instruction stream based on a preset data element reading order, and send the first instruction stream to the conversion processing unit;

[0007] The conversion processing unit is used to, in response to receiving the first instruction stream, read the first data element in the data to be processed from a preset storage space based on the data element reading order indicated by the first instruction stream, and store the read first data element in the register stack; after the first data element stored in the register stack meets the preset conversion condition, perform conversion processing on the first data element to obtain a second data element; wherein each second data element is obtained by converting multiple first data elements, and the number of registers in the register stack is determined based on the data element reading order.

[0008] In a second aspect, the present disclosure also provides a data processing method, which includes:

[0009] In response to receiving the data processing instruction, the control unit generates a first instruction stream based on a preset data element reading order, and sends the first instruction stream to the conversion processing unit;

[0010] In response to receiving the first instruction stream, the conversion processing unit reads the first data element in the data to be processed from a preset storage space based on the data element reading order indicated by the first instruction stream, and stores the read first data element in the register stack; after the first data element stored in the register stack meets the preset conversion condition, the first data element is converted to obtain a second data element; wherein each second data element is converted from multiple first data elements, and the number of registers in the register stack is determined based on the data element reading order.

[0011] In a third aspect, an embodiment of the present disclosure provides a data processing chip, comprising the data processing device as described in the first aspect or any one of the first aspects.

[0012] In a fourth aspect, an embodiment of the present disclosure provides a board comprising the data processing chip described in the third aspect.

[0013] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, comprising the data processing device described in the first aspect or any item of the first aspect, or the data processing chip described in the third aspect, or the board described in the fourth aspect.

[0014] In a sixth aspect, an optional implementation of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run, it executes the steps of the above-mentioned second aspect or any possible implementation of the second aspect.

[0015] The present disclosure provides a data processing device that reduces the cache depth of registers by adjusting the order in which data elements are read, thereby reducing the space occupied by registers in the data processing device and reducing the impact of additional cache on the area and power consumption of computing hardware in fast convolution calculations.

[0016] For a description of the effects of the above-mentioned computer equipment and computer-readable storage medium, please refer to the description of the above-mentioned data processing device, which will not be repeated here.

[0017] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure.

[0018] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without inventive effort.

[0020] Figure 1 An example of a fast convolution processing process provided by an embodiment of the present disclosure is shown;

[0021] Figure 2 A schematic diagram of a data processing device provided by an embodiment of the present disclosure is shown;

[0022] Figure 3 A schematic diagram showing a specific example of determining a reading order of child data elements by crossing a reading order of parent data elements provided by an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of another data processing device provided by an embodiment of the present disclosure is shown;

[0024] Figure 5 A schematic diagram of another data processing device provided by an embodiment of the present disclosure is shown;

[0025] Figure 6 A schematic diagram of a board provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0027] Research has found that fast (Winograd) convolution, due to its data reuse, reduces time-consuming multiplication operations by adding a small number of addition or subtraction operations. This effectively improves the running speed of convolutional networks when the convolution kernel size is small. Therefore, it is widely used in convolutional networks with small convolution kernels (such as 3x3 and 5x5). The fast convolution operation process generally includes three processing steps: pre-processing, operation processing, and post-processing.

[0028] like Figure 1 As shown in the figure, a specific example of fast convolution is provided. In this example, the size of the convolution kernel of the fast convolution is 3*3, the image block D of size 4*4 is used as input, and the convolution result block of size 2*2 is used as output.

[0029] (1): During the pre-processing process, based on the formula V=B T DB transforms the input image block D to obtain the image block V after the image block D is transformed, where B represents the transformation matrix. After the formula is expanded, it satisfies the following formula:

[0030]

[0031] (2) During the computational process, the 4*4 image block V obtained from the pre-processing process and the 4*4 weight block U are used to obtain the matrix block Y based on the formula Y = U⊙V. Here, the weight block U represents the weight block determined by the convolution kernel based on the fast convolution. ⊙ represents point-by-point multiplication. This process is completed by the computational array.

[0032] (3): In the post-processing process, the matrix block Y obtained by point-by-point multiplication is transformed into a matrix R = A T YA, and get the output matrix R. The output matrix R is the feature map obtained by fast convolution processing of the image block D using the convolution kernel. After the matrix calculation is expanded, it is equivalent to the following formula:

[0033] r0=y0+y1+y2+y4+y5+y6+y8+y9+y10

[0034] r1=y1-y2-y3+y5-y6-y7+y9-y10-y11

[0035] r2=y4+y5+y6-y8-y9-y10-y12-y13-y14

[0036] r3=y5-y6-y7-y9+y10+y11-y13+y14+y15

[0037] Then, the corresponding four data elements in the matrix block Y belonging to the same data channel in the output matrix R are output.

[0038] During pre-processing, the four data elements in the input image block D must be processed accordingly, necessitating additional cache space for storing these data elements. This cache space is typically implemented using registers, each of which can typically only store one data element. The number of registers represents the cache depth. A greater number of registers requires more space in the data processing device, impacting the area and power consumption of the data processing chip. This impact is positively correlated with the cache depth of the register.

[0039] Here, the minimum cache depth refers to the minimum number of registers required to store data elements in image block D while meeting the computational requirements of the pre-processing process. The computational requirement here means that when a data element in image block V is calculated in a certain order during the pre-processing process, the four data elements in image block D required by that data element must already be stored in registers.

[0040] For example, in the related art, for input data D with sizes of 4, 4 and 16 in the H (height), W (width) and C (data channel) directions respectively, the unit vector Vi in the C direction (size of 1×1×16) can be used as cache data, that is, the vector Vi0 corresponding to d0 in the C channel direction, the vector Vi1 corresponding to d1 in the C channel direction, the vector Vi2 corresponding to d2 in the C channel direction, etc. can be cached in the register in the order of d0 to d15 as cache data.

[0041] Exemplarily, when the image block V and the input block D satisfy the following formula:

[0042]

[0043] Among them, for any data element of image block V, it is necessary to add the four data elements in image block D. For the i-th data element in V, the maximum coordinate of the four data elements in image block D corresponding to the i-th data element vi is P(i), and the minimum coordinate is Q(i). Taking the 0th point v0=d0-d2-d8+d10 in image block V as an example, the required maximum coordinate in image block D is P(i)=10 and the minimum coordinate is Q(i)=0. It can be deduced that the minimum cache depth of the register satisfies:

[0044]

[0045] The above formula consists of two terms. Because the maximum function is used, the values ​​of i in the first and second terms range from 0 to 15, and the two values ​​of i do not need to be the same. P(i)-i represents: for the i-th point in image block V, subtract i from the maximum coordinate value P(i) among the four data elements d associated with it.

[0046] max i＝0～15 (P(i)-i) means: iterate over the values ​​of i. In this example, it traverses 0 to 15, and when it reaches i, calculates the value of P(i)-i, and finally takes the maximum value of these 16 P(i)-i.

[0047] For example, when traversing to 0, for v0=d0-d2-d8+d10, P(i)-i=10-0=10;

[0048] When traversing to 1, for v1=d1+d2-d9-d10, P(i)-i=10-1=9;

[0049] When traversing to 2, for v2 = d2 - d1 + d9 - d10, P(i) - i = 10 - 2 = 8;

[0050] When traversing to 3, for v3 = -d3 + d1 - d9 + d11, P(i) - i = 11 - 3 = 8;

[0051] When traversing to 4, for v4 = d4 - d6 + d8 - d10, P(i) - i = 10 - 4 = 6;

[0052] …

[0053] When traversing to 15, for v15=d15-d5-d7-d13, P(i)-i=15-15=0.

[0054] Then we can get max i＝0～15 The value of (P(i)-i) is 10.

[0055] iQ(i) represents: for the i-th data element in the image block V, the minimum coordinate value Q(i) among the four data elements d related to it is subtracted from i.

[0056] max i＝0～15 (iQ(i)) means: iterate over the values ​​of i. In this example, it iterate over 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15. When it reaches i, calculate the value of iQ(i) and finally take the maximum value of these 16 iQ(i).

[0057] For example, when traversing to 0, for v0=d0-d2-d8+d10, iQ(i)=0-0=0;

[0058] When traversing to 1, for v1=d1+d2-d9-d10, iQ(i)=1-1=0;

[0059] When traversing to 2, for v2 = d2 - d1 + d9 - d10, P(i) - i = 2 - 1 = 1;

[0060] When traversing to 3, for v3 = -d3 + d1 - d9 + d11, iQ(i) = 3 - 1 = 2;

[0061] …

[0062] When traversing to 15, for v15=d15+d5-d7-d13, iQ(i)=15-5=10.

[0063] Then we can get max i＝0～15 The value of (iQ(i)) is 10.

[0064] Based on the above formula, the minimum cache depth is 10 + 10 + 2 = 22. In a sample configuration (16 operation arrays, 128-bit input), the number of registers added to this cache is 22 * ​​128 * 16 = 45 Kbits, which has a certain impact on the area and power consumption of the data processing device.

[0065] Based on the above research, the present disclosure provides a data processing device that reduces the cache depth of registers by adjusting the order in which data elements are read, reduces the space occupied by registers in the data processing device, and reduces the impact of additional cache on the area and power consumption of computing hardware in fast convolution calculations.

[0066] The defects in the above solutions are the results obtained by the inventors after practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by this disclosure for the above problems below should be the contributions made by the inventors to this disclosure during the disclosure process.

[0067] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0068] The data processing device provided by the embodiment of the present disclosure can be applied to a computer device; the computer device includes, for example, a terminal device, a server or other processing equipment. Among them, the terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The computer device can use the data processing device provided by the embodiment of the present disclosure to process data. In addition, the data processing device provided by the embodiment of the present disclosure can also be deployed in a data processing chip, such as an artificial intelligence (AI) chip, a graphics processing unit (GPU), a central processing unit (CPU), etc.

[0069] The data to be processed in the embodiments of the present disclosure include, for example: an image, or a feature map obtained after feature extraction of an image, or partial data in a feature map, or data after standardization, binarization, or normalization of the feature map.

[0070] In specific implementations, the data processing device proposed in the embodiments of the present disclosure can be used to perform convolution processing on input data corresponding to the convolution processing type. That is, in one possible implementation, the data processing device can perform different types of convolution processing transformations depending on the convolution processing type. The number and specific types of convolution processing types included can be flexibly determined based on actual circumstances and are not limited to the following disclosed embodiments.

[0071] In an optional embodiment, the convolution processing type may include ordinary convolution and special convolution. Among them, ordinary convolution can be a convolution calculation implemented according to the original convolution definition method. Special convolution can be various forms of convolution other than ordinary convolution. The number of types and specific types included in special convolution can also be flexibly determined according to actual conditions. In one possible implementation, special convolution may include: fast convolution and / or depth convolution.

[0072] In an optional embodiment, when the special convolution includes only one of the various types of special convolutions proposed above, the data processing device proposed in the embodiment of the present disclosure can perform convolution processing of ordinary convolution or convolution processing of special convolution on the input data according to the instruction; in a possible implementation method, when the special convolution includes multiple types of the various types of special convolutions proposed above, the data processing device proposed in the embodiment of the present disclosure can perform convolution processing of ordinary convolution on the input data according to the instruction (using the convolution module in the data processing unit), or convolution processing of a special convolution indicated by the instruction. The subsequent disclosed embodiments take the special convolution including fast convolution as an example to illustrate the implementation method of the data processing device. The special convolution is other types of convolution, or the special convolution includes multiple types of convolution. The expansion can be referred to the subsequent disclosed embodiments and will not be explained here.

[0073] like Figure 2 As shown, an embodiment of the present disclosure provides a structural schematic diagram of a data processing device; the data processing device is used to perform convolution processing corresponding to the convolution processing type on input data, and the data processing device includes:

[0074] a control unit 10 for, in response to receiving a data processing instruction, generating a first instruction stream based on a preset data element reading order, and sending the first instruction stream to the conversion processing unit;

[0075] The conversion processing unit 20 is used to respond to receiving the first instruction stream and, based on the data element reading order indicated by the first instruction stream, read the first data element in the data to be processed from a preset storage space, and store the read first data element in a register stack; after the first data element stored in the register stack meets the preset conversion condition, perform conversion processing on the first data element to obtain a second data element; wherein each second data element is obtained by converting multiple first data elements, and the number of registers in the register stack is determined based on the data element reading order.

[0076] According to the different implementation methods of the convolution processing type, the implementation form of the control unit 10 and the conversion processing unit 20 can be flexibly adjusted. It can be seen from the above-mentioned disclosed embodiments that the control unit 10 can issue different instructions to the conversion processing unit 20 according to the different convolution processing types. The conversion processing unit 20 can perform the conversion processing operation corresponding to the convolution processing type on the input data according to the different convolution processing types to obtain the target data. Therefore, as the convolution processing type changes, the hardware implementation method of the control unit 10 and the conversion processing unit 20, as well as the conversion processing method implemented based on the hardware implementation method, may change.

[0077] In an optional embodiment, when the convolution processing type includes fast convolution, the control unit 10 and the conversion processing unit 20 can perform the conversion processing operation corresponding to the fast convolution of the input data according to the convolution processing type indicated by the instruction. The specific implementation process of the above operation can be referred to the following disclosed embodiments.

[0078] In an optional embodiment, when the convolution processing type includes depthwise convolution, the hardware structure of the control unit 10 and the conversion processing unit 20 may be different from the structure of the above-mentioned conversion processing unit 20 that can perform fast convolution, so that depthwise convolution transformation, etc. can be achieved.

[0079] The data format obtained by the conversion processing unit 20 can be determined according to the actual situation of the input data and the form of the conversion processing operation corresponding to the convolution processing type, and is therefore not limited in the embodiments of the present disclosure. The number of conversion processing units 20 is not limited in the embodiments of the present disclosure and can be flexibly changed according to the amount and size of the input data. In an optional embodiment, the data processing device can include one conversion processing unit 20. In an optional embodiment, the data processing device can also include multiple conversion processing units 20 at the same time.

[0080] After receiving a data processing instruction, the data processing provided by the embodiment of the present disclosure generates a first instruction stream based on a preset data element reading order and sends the first instruction stream to the conversion processing unit. After receiving the first instruction stream, the conversion processing unit reads the first data element in the to-be-processed data from a preset storage space based on the data element reading order indicated in the first instruction stream, and stores the read first data element in a register file; after the first data element stored in the register file meets a preset conversion condition, the first data element is converted to obtain a second data element.

[0081] Among them, since each second data element is obtained by converting multiple first data elements, and the number of registers in the register file is determined by the reading order of the data elements, as long as appropriate conditions are set and a suitable reading order of data elements is found, the entire convolution operation process can be implemented through a smaller cache space, thereby reducing the requirements for the number of registers, reducing the space occupied by registers in the data processing device, and reducing the impact of additional cache in fast convolution calculations on the area and power consumption of the computing hardware.

[0082] The specific functions of the control unit and the conversion processing unit are described in detail below.

[0083] For control unit 10:

[0084] In a specific implementation, the data processing instruction includes, for example, a fast convolution processing instruction for instructing the data processing device to perform fast convolution.

[0085] In a computer architecture including a host and a data processing device, the host can send a data processing instruction to the data processing device to instruct the data processing device to execute the data processing instruction, and the data processing instruction originates from the host; or in a computer architecture including a data processing device and a CPU, the CPU can send a data processing instruction to the data processing device to instruct the data processing device to execute the data processing instruction, and the data processing instruction originates from the CPU. In the case where the data processing instruction includes a fast convolution processing instruction, the conversion processing unit is configured to perform a pre-processing process in the fast convolution processing process based on the control of the control unit.

[0086] In an optional embodiment, as Figure 5 As shown, the data processing device described in the present disclosure may further include: the pre-processing unit 30.

[0087] The pre-processing unit 30 is used to determine the reading order of the data elements.

[0088] In an optional implementation, the pre-processing unit 30, when determining the data element reading order, is configured to:

[0089] During each of the plurality of genetic mutation cycles, performing:

[0090] Performing genetic variation processing on a reading order of parent data elements corresponding to a current genetic variation cycle to obtain a reading order of child data elements corresponding to the current genetic variation cycle; the parent data element reading order includes: an original data element reading order, and / or a reading order of child data elements in a historical genetic variation cycle corresponding to the current genetic variation cycle, and / or a reading order of parent data elements in the historical genetic variation cycle;

[0091] Determine a first minimum register cache depth corresponding to a descendant data element reading order;

[0092] In response to a current genetic variation cycle satisfying a preset iteration stop condition, determining, based on the current iteration cycle, a second minimum register cache depth corresponding to a parent generation data element reading order corresponding to the current genetic variation cycle, and a first minimum register cache depth, the data element reading order from a historical parent generation data element reading order corresponding to the current genetic variation cycle and a historical child generation data element reading order;

[0093] In response to the current genetic variation cycle not satisfying the iteration stop condition, entering the next genetic variation cycle.

[0094] In an optional embodiment, the pre-processing unit 30, before performing genetic variation processing on the parent data element reading order corresponding to the current genetic variation cycle to obtain the child data element reading order corresponding to the current genetic variation cycle, is further configured to:

[0095] In response to the current genetic variation cycle being the first genetic variation cycle, determining the original data element reading order to be the parent data element reading order corresponding to the current genetic variation cycle;

[0096] In response to the current genetic variation cycle not being the first genetic variation cycle, a parent data element reading order corresponding to the current genetic variation cycle is determined based on a first minimum register cache depth corresponding to a historical child data element reading order of the historical genetic variation cycle and a second minimum register cache depth corresponding to a historical parent data element reading order of the historical genetic variation cycle.

[0097] In a specific implementation, the data element reading order can be determined by using a genetic variation algorithm, for example.

[0098] Among them, the genetic algorithm is a random global search optimization method that simulates phenomena such as replication, crossover, and mutation that occur in natural selection and genetics. Starting from any initial population, through random selection, crossover, and mutation operations, it produces a group of individuals that are more suitable for the environment, allowing the group to evolve to better and better areas in the search space. In this way, it continues to reproduce and evolve from generation to generation, and finally converges to a group of individuals that are most adapted to the environment, thereby obtaining a high-quality solution to the problem.

[0099] In order to prevent the genetic algorithm from falling into a local optimal solution during the optimization process, individuals need to be mutated during the search process. In practical applications, single-point mutation, also called bit mutation, is mainly used, that is, only one bit in the gene sequence needs to be mutated. Taking binary coding as an example, 0 becomes 1, and 1 becomes 0.

[0100] In this embodiment, the reading order of data elements, that is, the input cycle corresponding to each data element can become the object of genetic mutation. For example, if the input cycle of a data element is 10, it can be mutated to 01, that is, the input is changed from the tenth cycle to the first cycle.

[0101] When using a genetic variation algorithm to determine the order in which data elements are read, for example, the following methods corresponding to steps 11 and 12 may be used:

[0102] Step 11: Determine the original data element reading order corresponding to each data element in the image block. Exemplarily, the original data element reading order can be determined according to the position of each data element in the image block, for example, it can be expressed as:

[0103] SI_0-15={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}.

[0104] Each number in the original data element reading sequence SI_0-15 is used to represent the data reading cycle corresponding to the first data element at the corresponding position. In the initial data element reading sequence, the reading sequence of the data elements is not adjusted.

[0105] For example, assuming that the data in the image block includes d0 to d15, the above data element reading sequence represents the number of reading cycles corresponding to the 16 data elements. Taking the 0 displayed in the first position as an example, it represents that the first data element d0 needs to be read in the 0th cycle, which can also be understood as the initial cycle or the need to be read from the beginning; taking the 1 displayed in the second position as an example, it represents that the second data element d1 needs to be read in the 1st cycle; taking the sixteenth position as an example, it represents that the sixteenth data element d15 needs to be read in the 15th cycle. The above example data element reading sequence uses the cycle number 0 to 15 to describe, which is not a limitation. The corresponding cycle number can also be described using 1 to 16 or other number series. In addition, the specific representation method can also be determined based on the actual number of data elements in the image block.

[0106] Alternatively, the initial data element reading order can be randomly determined. There can be multiple or just one initial data element reading order. Each genetic variation cycle can correspond to one or more parent-generation data element reading orders; and each genetic variation cycle can correspond to one or more child-generation data element reading orders.

[0107] Step 12: During each of the plurality of genetic variation cycles, executing:

[0108] Step 121: Perform genetic variation processing on the reading order of the parent data elements corresponding to the current genetic variation cycle to obtain the reading order of the child data elements corresponding to the current genetic variation cycle.

[0109] In which, in response to the current genetic variation cycle being the first genetic variation cycle, the parent data element reading order corresponding to the current genetic variation cycle includes, for example, an initial data element reading order.

[0110] For example, assuming that the current genetic variation cycle is the first genetic variation cycle, the order of reading the parent data elements includes:

[0111] Parent: SI_0-15 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}.

[0112] When mutating it, for example, the data reading order of any two data elements can be randomly adjusted, for example, the data reading order of the 2nd and 5th data elements can be adjusted, and the resulting reading order of the child data elements is:

[0113] Offspring: SI_0-15 = {0, 4, 2, 3, 1, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}.

[0114] When making adjustments, there is no limit on the number of adjustments that can be made per mutation, and there is no limit on the position of the adjustments.

[0115] There may also be multiple read orders for the obtained child data elements.

[0116] In response to the current genetic variation cycle being not the first genetic variation cycle, the reading order of the parent data elements corresponding to the current genetic variation cycle is determined in a genetic variation cycle before the current genetic variation cycle.

[0117] For example, if you want to obtain the data element reading order corresponding to the current genetic variation cycle, that is, the offspring data element reading order corresponding to the second genetic variation cycle, you need to determine the parent data element reading order corresponding to the second genetic variation cycle based on the data element reading order of the first genetic variation cycle. In this case, the data element reading order of the first genetic variation cycle is the parent generation, and the data element reading order of the second genetic variation cycle is the offspring generation.

[0118] The specific determination method can be found in step 123 below.

[0119] The parent generation's data element reading order can be randomly generated or manually set. There can also be multiple parent generation data element reading orders. This allows for both mutation and crossover operations when determining the data element reading order. The child generation's data element reading order can be determined based on a parent generation's data element reading order, by mutating the parent generation's data element reading order to obtain the child generation's data element reading order. Alternatively, the child generation's data element reading order can be determined based on multiple parent generation data element reading orders, for example, by crossovering any two parent generation data element reading orders to obtain the child generation's data element reading order.

[0120] The mutation operation can be performed on the reading order of a single parent data element, and the crossover operation can be performed based on the reading orders of multiple parent data elements, thereby obtaining multiple reading orders for the child data elements. During the genetic mutation of the parent data element reading order, the reading orders of different parent data elements can be crossovered to obtain the reading order of the child data elements; or the reading order of a parent data element can be mutated to obtain the reading order of the child data elements.

[0121] Exemplarily, a partial mutation method can be used when performing mutation processing, for example, only the reading order of some data elements is changed, while the reading order of other data elements remains unchanged. Among the 16 data elements, the reading order of the first 8 data elements remains the reading order of the data elements in the parent generation, while the reading order of the last 8 data elements is redistributed.

[0122] Illustratively, when performing crossover processing, a crossover point may be determined first and then a repetition period may be processed. For example, in the following two sequences, crossover processing may be performed using the interval between the 9th data element and the 10th data element in a read sequence of 16 data elements as the crossover point:

[0123] Parent 1: SI_0-15 = {1, 2, 4, 0, 7, 10, 9, 11, 3, 6, 5, 8, 13, 12, 15, 14}

[0124] Parent 2: SI_0-15 = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0}

[0125] The crossover process Figure 3 As shown,

[0126] The crossover results include: {1,2,4,0,7,10,9,11,3,10,11,12,13,14,15,0}

[0127] However, since repeated read cycles occur, the repeated cycles can be replaced with cycles that do not appear in the sequence. That is, in this example, the second occurrence of 10 is replaced with 5, the second occurrence of 11 is replaced with 6, and the second occurrence of 0 is replaced with 8. Finally, the resulting reading order of the child data elements is as follows:

[0128] Offspring: SI_0-15 = {1, 2, 4, 0, 7, 10, 9, 11, 3, 5, 6, 12, 13, 14, 15, 8}.

[0129] Step 122: Determine a first minimum register cache depth corresponding to the descendant data element reading order.

[0130] In a specific implementation, for example, assuming that the i-th pixel in the image block D is input in the SI(i)-th cycle and the i-th pixel in the image block V is calculated in the SO(i)-th cycle, the calculation process of the cache depth becomes:

[0131] The i-th data element of image block V needs to be obtained by adding the four data elements in input block D. Assume that the maximum value of the input period of these four data elements is P'(i) and the minimum value is Q'(i). Taking v0 = d0 - d2 - d8 + d10 as an example, the corresponding P'(0) = max(SI(0), SI(2), SI(8), SI(10)) and Q'(0) = min(SI(0), SI(2), SI(8), SI(10)). It can be deduced that the minimum cache depth satisfies the following formula:

[0132]

[0133] Exemplarily, the data element reading order and the data element conversion order include:

[0134] SI_0-15={1,2,4,0,7,10,9,11,3,6,5,8,13,12,15,14}

[0135] SO_0-15={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}

[0136] It should be stated in advance that the number of cycles in the SI sequence and the SO sequence represent the data element reading order and the data element conversion order, respectively. The same number does not mean that the time points corresponding to the two cycles are the same. These are two different cycle sequences. For example, when it is the fourth data element reading cycle, the first data element conversion cycle may not have started yet, that is, the number of data element reading cycles and the number of data element conversion cycles are counted separately.

[0137] Each number in the data element conversion sequence SO_0-15 represents the data conversion cycle corresponding to the second data element at the corresponding position. The SO sequence is generated based on the SI sequence. For example, the second data element V0 can be determined by the first data elements d0, d2, d8, and d10. According to the above SI sequence, the first data element d0 must be input in the first data element reading cycle, the first data element d2 must be input in the fourth data element reading cycle, the first data element d8 must be input in the third data element reading cycle, and the first data element d10 must be input in the fifth data element reading cycle. That is, when the number is input to the fifth data element reading cycle, all four first data elements required to form the second data element V0 have been input, and V0 is also the first second data element that meets the data conversion conditions. At this time, the second data element V0 can be converted in the first data element conversion cycle, that is, starting from the 0th data element conversion cycle. Based on this method, a complete SO sequence can be obtained.

[0138] Taking i=0 as an example, v0=d0-d2-d8+d10, corresponding to P'(0)=max(SI(0),SI(2),SI(8),SI(10)), Q'(0)=min(SI(0),SI(2),SI(8),SI(10)).

[0139] Among them, SI(0) is input in the third data element reading cycle, that is: SI(0)=3;

[0140] SI(2) is input during the first data element reading cycle, i.e., SI(2) = 1;

[0141] SI(8) is input in the 11th data element reading cycle, that is, SI(8)=11;

[0142] SI(10) is input during the fifth data element read cycle, i.e. SI(10) = 5;

[0143] Then according to the above formula, when i=0, P'(0)=max(SI(0),SI(2),SI(8),SI(10))=11;

[0144] Q'(0)=min(SI(0), SI(2), SI(8), SI(10))=1; SO(i)=0.

[0145] Taking i=7 as an example, v7=-d7+d5+d9-d11, corresponding to P'(7)=max(SI(7),SI(5),SI(9),SI(11)), Q'(7)=min(SI(7),SI(5),SI(9),SI(11)).

[0146] Among them, SI(7) is input in the fourth data element reading cycle, that is: SI(7)=4;

[0147] SI(5) is input during the 10th data element read cycle, i.e., SI(5) = 10;

[0148] SI(9) is input in the 6th data element reading cycle, that is: SI(9)=6;

[0149] SI(11) is input in the 7th data element reading cycle, that is, SI(11)=7;

[0150] According to the above formula, when i=7, P'(7)=max(SI(7),SI(5),SI(9),SI(11))=10;

[0151] Q'(7)=min(SI(7), SI(5), SI(9), SI(11))=4; SO(i)=7.

[0152] The minimum cache depth is calculated by max i＝0～15 (P′(i)-SO(i)), max i＝0～15 The calculation consists of two terms: (SO(i) - Q′(i)) + 2. Because the maximum function is used, the values ​​of i in the two terms range from 0 to 15, and the two values ​​of i do not need to be the same. After the values ​​of i in the two terms range from 0 to 15, the maximum value is taken and added together. The minimum cache depth corresponding to the above SI / SO sequence is 12.

[0153] Step 123: Based on the second minimum register cache depth and the first minimum register cache depth corresponding to the parent data element reading order, determine the parent data element reading order corresponding to the next genetic variation cycle from the parent data element reading order corresponding to the current genetic variation cycle and the child data element reading order.

[0154] Here, for example, the second minimum register cache depth and the first minimum register cache depth can be sorted in descending order or in descending order. Then, a preset number of minimum register cache depths are selected based on the sorting order, and the data element reading order corresponding to the selected preset number of minimum register cache depths is used as the parent data element reading order corresponding to the next genetic variation cycle.

[0155] For example, if there are M parent generation data element reading orders in the current genetic variation cycle (for example, in the previous genetic variation cycle, two offspring are obtained by performing two mutations on the same parent generation. In the current genetic variation cycle, the two offspring obtained in the previous genetic variation cycle can be used as the current parent generation), the corresponding second minimum register cache depths are: F1 to F M , the reading order of the offspring data elements in the current genetic mutation cycle is N, and the corresponding first minimum register cache depths are Z1~Z N , then F1~F M , and Z1~Z N Sort them in descending order, and then select S minimum register cache depths from the end of the sort, assuming they are: G1~G S , among which G1~G S The set composed belongs to F1~F M , and Z1~Z N Then the selected S minimum register cache depths G1~G S The corresponding data element reading order is used as the parent data element reading order corresponding to the next genetic variation cycle.

[0156] In another embodiment, during each genetic variation cycle, it is further determined whether the genetic variation cycle meets a preset stop condition. If the preset stop condition is met, the next genetic variation cycle is not performed. If the stop condition is not met, the next genetic variation cycle is performed.

[0157] The stopping conditions may include, for example, at least one of the following: the current genetic variation cycle reaches a preset cycle threshold; or the reading order of parent data elements determined by multiple genetic variation cycles no longer changes. Other stopping conditions may also be set, depending on actual needs.

[0158] Furthermore, since the data element reading order has changed compared to the data element reading order in the related art, the calculation order of each second data element in the image block V has also changed. That is, the data element conversion order has also changed accordingly. When determining the data element reading order, the data element conversion order can also be determined based on the determined data element reading order.

[0159] Specifically, for example, based on the determined data element reading order, it can be determined when the first data element read into the register will satisfy the processing conditions of each second data element in the image block V. That is, the processing condition of any second data element can be met after all first data elements required to calculate the second data element are cached in the register. Then, based on the order in which the processing conditions are satisfied by each second data element, the data element conversion order is determined.

[0160] exist Figure 1 In the corresponding example, the above method is used to find the optimal SI (data element reading order) / SO (data element conversion order) sequence, and the optimal cache depth is finally obtained as 12. The corresponding data element reading order and data element conversion order include, for example:

[0161] SI_0-15={1,2,4,0,7,10,9,11,3,6,5,8,13,12,15,14}

[0162] SO_0-15={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}

[0163] or:

[0164] SI_0-15={1,12,7,13,2,9,4,15,3,11,6,10,0,8,5,14}

[0165] SO_0-15={3,11,10,15,1,9,7,14,2,6,8,13,0,5,4,12}.

[0166] By changing the order in which data elements are read and converted, the data elements processed in each read cycle and conversion cycle can be maximized, without inputting data elements that cannot be used in a short period of time during certain read cycles, which would cause such data elements to accumulate in the storage space and take up too much space. The efficient use of data elements and their conversion as soon as possible after input reduces the space occupied by registers in the data processing device and reduces the power consumption caused by registers. After calculating using the above minimum cache depth calculation formula, it can also be found that the small cache depth of the register changes from 22 to 12.

[0167] The data element reading order can be generated in advance. After the data element reading order is generated, the determined data element reading order can be used as configuration information of the data processing device. After the data processing device is started, the determined data element reading order is transmitted to the control unit of the data processing device, so that the control unit can generate a first instruction stream based on the data element reading order and send the first instruction stream to the conversion processing unit.

[0168] The first instruction stream includes: first data read instructions corresponding to a plurality of data read cycles respectively.

[0169] The first data read instruction includes: address information of a first data element to be read in a data read cycle corresponding to the first data read instruction.

[0170] When the control unit 11 generates the first instruction stream based on the preset data element reading order, it may specifically adopt the following methods described in steps 31 to 34:

[0171] Step 31: Obtain a sequence of read cycle numbers corresponding to the data element read sequence, wherein the sequence of data element read cycle numbers includes: read cycle numbers of data read cycles corresponding to a plurality of first data elements in the data to be processed.

[0172] In a specific implementation, the read cycle number sequence is as described in the above example and is expressed as:

[0173] SI_0-15={1,2,4,0,7,10,9,11,3,6,5,8,13,12,15,14}

[0174] Among them, 1 means that d0 is read in the 1st data reading cycle; 2 means that d1 is read in the 2nd data reading cycle; 4 means that d2 is read in the 4th data reading cycle; 0 means that d3 is read in the 0th data reading cycle; 7 means that d4 is read in the 7th data reading cycle...; In this way, based on the above reading cycle number sequence, the data reading cycle number corresponding to each first data element in the data to be processed can be determined.

[0175] Step 32: Determine index information of the first data element corresponding to the read cycle number of each data read cycle from the read cycle number sequence; the index information is used to represent the position of the corresponding first data element in the data to be processed.

[0176] In a specific implementation, based on the correspondence between each data reading cycle and the first data element in the reading cycle number sequence, the index information of the first data element corresponding to each data reading cycle can be determined. Figure 1The corresponding image block D includes 16 first data elements, and the index information of the 16 first data elements is d0 to d15. Based on the meaning of the numerical values ​​in the above read cycle number sequence, the index information of the first data element corresponding to the 0th data read cycle is determined to be d3; the index information of the first data element corresponding to the 1st data read cycle is d0; the index information of the first data element corresponding to the 2nd data read cycle is d1, and so on. Based on this correspondence, the index information of the first data elements corresponding to multiple data read cycles can be determined.

[0177] Step 33: Determine the address information of the first data element corresponding to each data reading cycle according to the starting address, address width, and index information of the data to be processed.

[0178] Here, the address information P of the first data element satisfies, for example: P=starting address*index information*address bit width.

[0179] Step 34: Generate a first data read instruction corresponding to each data read cycle according to the obtained address information of the first data element corresponding to each data read cycle.

[0180] Here, when generating the first data read instruction, the address information of the first data element is carried in the first data read instruction, so that after receiving the first data processing instruction, the conversion processing unit can access the corresponding storage space according to the address information and obtain the corresponding first data element.

[0181] The control unit 10 may send a first data reading instruction corresponding to each data reading cycle to the conversion processing unit 20 in each data reading cycle among the plurality of data reading cycles.

[0182] After the conversion processing unit 20 receives the first data read instruction corresponding to each data read cycle sent by the control unit 10, the first data element corresponding to each data read cycle is read from the preset storage space based on the address information carried in the received first data read instruction.

[0183] The preset storage space may include: a memory, a hard disk, a USB flash drive, etc., which is not limited in the present disclosure. The storage space is used to store data to be processed.

[0184] When the conversion processing unit 20 stores the read first data element in the register stack connected to the conversion processing unit, it can determine the target register address corresponding to the current data reading cycle in each data reading cycle of the multiple data reading cycles according to the number of registers in the register stack, the initial register address corresponding to the register stack, the address bit width of the register, and the register identifier corresponding to the previous data reading cycle; based on the target storage address corresponding to the current data reading cycle, the data element read in the current data reading cycle is stored in the corresponding register.

[0185] For example, Figure 4 In the data processing device shown, there are m registers in the register file. When each first data element enters the register file, it is stored in sequence according to the order of the registers in the register file. For example, the first first data element read is stored in register 1; the second first data element read is stored in register 2; ... the mth first data element read is stored in register m; the (m+1)th data element read is stored in register 1, and the previously stored first data element is overwritten... In this way, each register in the register file is reused to temporarily store each first data element. Among them, the register identifier is used to indicate the position of the register in the register file. That is, a register with a register identifier of i indicates that the position of the register in the register file is the i-th register.

[0186] In any data reading cycle, when determining the target register address corresponding to the current data reading cycle according to the above-mentioned storage method, based on the number of registers in the register stack, the initial register address corresponding to the register stack, the address bit width of the register, and the register identifier corresponding to the previous data reading cycle, the current register identifier corresponding to the current data reading cycle can be determined based on the number of registers in the register stack and the register identifier corresponding to the previous data reading cycle, and then the target register address corresponding to the current data reading cycle can be determined based on the current register identifier corresponding to the current data reading cycle, the initial register address corresponding to the register stack, and the address bit width of the register.

[0187] That is, if the register address corresponding to the previous data read cycle is identified as i, then the target register identification corresponding to the current data read cycle is (i%m)+1, where % represents the remainder after dividing m by i.

[0188] The initial register address corresponding to the register stack is: M, the address bit width is f, then the target register address corresponding to the current data read cycle satisfies: ((i%m)+1)*f+M.

[0189] Then, according to the target register address, the first data element read in the current data reading cycle is stored in the corresponding register.

[0190] For the conversion processing unit 20:

[0191] In a possible implementation, the conversion processing unit includes: a first reading logic circuit 201.

[0192] When the control unit 10 sends the first instruction stream to the conversion processing unit 20 , specifically, the control unit 10 sends instructions to the first reading logic circuit 201 included in the conversion processing unit 20 .

[0193] The first reading logic circuit 201 is used to respond to receiving the first instruction stream sent by the control unit, read the first data element in the data to be processed from the preset storage space based on the data element reading order indicated by the first instruction stream, and store the read first data element in the register stack.

[0194] In a specific implementation, after receiving the first instruction stream sent by the control unit, the first logic circuit 201 can determine the number of read cycles corresponding to each first data element and the address information of the first data element corresponding to the read cycle. Based on the data element reading order in the first instruction stream, the first data element is read from a preset storage space and stored in a register file.

[0195] In an optional embodiment, the control unit 10 can also be used to generate a second instruction stream based on a preset data element conversion order; and after the first data element read into the register stack meets the preset conversion condition, send the second instruction stream to the conversion processing unit.

[0196] In a specific implementation, after determining the order of data element conversion, the second instruction stream has been generated. The reading and conversion of data elements requires a certain amount of time. When the first data element in the register stack reaches the preset conversion condition, the generated second instruction stream will be sent to the conversion processing unit.

[0197] Each second data element is obtained by converting multiple first data elements. The preset conversion condition may be that multiple first data elements constituting a second data element are already stored in a register file, or may be a conversion condition related to the currently-in-progress data element processing. The second instruction stream includes second data read instructions corresponding to multiple data conversion cycles.

[0198] Each data conversion cycle is determined based on the data element reading order, and after determining that the first data elements stored in the register file include all first data elements required for the second data elements corresponding to the current data conversion cycle based on the data element reading order, it is determined that the current data conversion cycle has been reached. For example, the corresponding relationship between the first data element and the second data element can be expressed by the following formula (1):

[0199]

[0200] Among them, the implementation of d0~d15 can refer to Figure 1 .from Figure 2 It can also be seen that Figure 2 The input data D disclosed in the above disclosed embodiment is B T DB conversion and splicing on the C channel can be transformed into an image block V. The data scale of V is the same as that of D, which is also 4×4×16. The plane vector data V0~V15 in the image block V can be obtained by performing corresponding addition / subtraction calculations on the plane vectors d0~d15 in the input data D according to the above calculation method.

[0201] Based on the calculation process disclosed above, it can be seen that in a possible implementation, after obtaining multiple cache data d through the cache, the corresponding d can be added and / or subtracted by the transformation method in the above formula. For example, in one example, when D is processed in the order of d0, d1, d2, etc. to obtain V, it is necessary to read d0 to d15 required to obtain V in the data reading order and store them in the register. When the first data element of the cache in the register meets the calculation conditions of any second data element in V, for example, when the cache data d10 is cached, the first data elements d0, d2, d8 and d10 can be added and subtracted by the first term of the matrix in formula (1) (that is, each output data on the C channel is calculated in the manner of d0-d2-d8+d10) to obtain the second data element V0 in the image block V. Similarly, other output vectors V1 to V15 in the image block V can be obtained respectively.

[0202] The second instruction stream is sent to the conversion processing unit 20 through the control unit 10 only after the preset conversion conditions are met, while the first instruction stream can be sent to the conversion processing unit 20 through the control unit 10 from the start of data reading after it is generated. The first instruction stream and the second instruction stream are sent asynchronously.

[0203] In an optional embodiment, after receiving the second instruction stream, the conversion processing unit 20 reads multiple first data elements corresponding to the second data elements from the register stack based on the second instruction stream, and converts the read first data elements to obtain corresponding second data elements.

[0204] When generating the second instruction stream based on the preset data element conversion order and the data element reading order, the control unit 10 is configured to: for each of the plurality of data conversion cycles, determine, from each of the first data elements of the data to be processed, a target first data element required for the second data element corresponding to each data conversion cycle. For example, as can be seen from the formula mentioned above, the first data elements corresponding to the second data element V0 are d0, d2, d8, and d10, respectively, and the corresponding relationships for the other elements are similar.

[0205] Based on the data element reading order, data reading cycles corresponding to the target first data elements and register addresses in the register file are determined.

[0206] Based on the data reading cycles corresponding to the target first data elements, a target data reading cycle associated with each data conversion cycle is determined; wherein, the target data reading cycle is used to indicate that after the target data reading cycle is reached, a second data reading instruction corresponding to the data conversion cycle is sent to the conversion processing unit.

[0207] A second data read instruction corresponding to each data conversion cycle is generated based on a target data read cycle associated with each data conversion cycle and the register addresses of the target first data elements in the register file.

[0208] In a specific implementation, for the jth data conversion cycle, if the ith data read cycle is used to read the last first data element d4 required for the second data element to be converted in the jth data conversion cycle, then the i+1th data read cycle is the target data read cycle. After the i+1th data read cycle is reached, a corresponding second data read instruction is sent to the conversion processing unit to read the four first data elements d1-d4 required for the jth data conversion cycle, and convert the read four data elements to obtain the second data element Vj corresponding to the jth data conversion cycle.

[0209] When the control unit 10 sends the second instruction stream to the conversion processing unit 20, it can send the second data read instruction corresponding to the current data conversion cycle to the conversion processing unit when the current data read cycle reaches the target data read cycle corresponding to the current data conversion cycle.

[0210] The conversion processing unit 20, after receiving the second instruction stream, reads a plurality of first data elements corresponding to the second data elements from the register file.

[0211] In a specific implementation, in response to receiving a second data processing instruction corresponding to a current data conversion cycle, the conversion processing unit 20 reads the target first data element corresponding to the current data conversion cycle based on the register addresses of the target first data elements indicated by the received second data processing instruction in the register file. For example, if the second element corresponding to the current cycle is v0, then after receiving the second instruction stream, the conversion processing unit 20 will read the first data elements d0, d2, d8, and d10 from the register file.

[0212] In an optional implementation, the conversion processing unit may further include: a second reading logic circuit 202 .

[0213] Regarding the second reading logic circuit 201 , when the control unit 10 sends the second instruction stream to the conversion processing unit 20 , specifically, it sends instructions to the second reading logic circuit 202 included in the conversion processing unit 20 .

[0214] After receiving the second instruction stream, the second reading logic circuit 202 reads the plurality of first data elements corresponding to the second data elements from the register file based on the second instruction stream. The specific execution method can be referred to the execution method of the conversion processing unit 20 after receiving the second instruction stream, and will not be repeated here.

[0215] The specific structure of the second logic circuit 202 is not limited in this disclosure. As long as the circuit structure or other hardware unit that can implement the above functions can be regarded as part of the structure of the conversion processing unit 20 in this device, it can be regarded as part of the structure of the conversion processing unit 20 in this device.

[0216] In an optional implementation, the conversion processing unit further includes: a conversion circuit configured to perform conversion processing on the first data element to obtain a second data element.

[0217] In a specific implementation, when the data processing instruction is a fast convolution instruction, the conversion process may include but is not limited to: performing pre-processing corresponding to the fast convolution process on the data to be processed.

[0218] At this time, the conversion circuit for converting the first data element to obtain the second data element may include, but is not limited to, a negation circuit 203 and an adder 204. The negation circuit 203 is used to negate the data to be subtracted during data conversion, and the adder 204 is used to add the data during data conversion.

[0219] It can be seen from the above disclosed embodiments that in one example, to implement B T For the conversion of DB, the accumulation unit can be implemented by four accumulators. When the first data element data d0~d15 is input, a lookup table can be used to determine whether the accumulator performs an accumulation operation when d0~d15 is input.

[0220] For example, from the corresponding relationship between the first data element and the second data element in the above formula (1), it can be seen that, taking the second data element v0 as an example, its corresponding first data elements are d0, d2, d8, and d10, respectively. According to v0=d0-d2-d8+d10 in formula (1), it can be seen that at this time, the negation circuit 203 can be used to negate the first data elements d2 and d8, and the adder 204 can be used to add the two negated first data elements and the two first data elements that do not need to be negated to obtain the second data element v0. Other second data elements in formula (1) can be obtained by this method.

[0221] In an optional implementation, the data processing device may further include: a data processing unit.

[0222] After the conversion processing unit sends the second data element to the data processing unit, the data processing unit can be used to perform the processing indicated by the data processing instruction on the second data element in response to receiving the second data element sent by the conversion unit to obtain result data.

[0223] The data processing unit may include but is not limited to: a convolution module, a post-transformation unit, and an accumulation unit.

[0224] The convolution module may be configured to perform a convolution operation based on the second data element to obtain a convolution processing result of the converted data composed of the second data element.

[0225] The convolution operation may include but is not limited to ordinary convolution, fast convolution, dilated convolution and other convolution operations.

[0226] The post-transformation unit can be used to perform a post-transformation operation on the convolution processing result to obtain post-transformation data.

[0227] In a possible implementation, when the data processing device performs ordinary convolution, the post-transformation unit may directly transmit the first data element d as post-transformation data to the accumulation unit.

[0228] The accumulation unit can be used to perform accumulation processing on each data element in the post-transformation data to obtain result data of performing fast convolution on the data to be processed.

[0229] The accumulation unit can accumulate the dot product results of different points inside the same convolution kernel, as well as the dot product results of different channel groups corresponding to the same convolution kernel in the feature map, thereby reducing the possibility of writing the intermediate data after the dot product operation to the external cache, and further reducing the data interaction between the data processing device in the embodiment of the present disclosure and the external cache.

[0230] In one possible implementation, the accumulation operation performed by the accumulation unit may be accumulation of data input by the post-transform unit according to convolution requirements. In one possible implementation, the accumulation operation may include at least one of the following two types of accumulation: one type may be accumulation of different dot product operation results performed on the same convolution kernel after being processed by the post-transform unit; the other type may be accumulation of multiple dot product operation results corresponding to the same channel direction in the case of multiple dot product operations performed on the same channel direction after being processed by the post-transform unit.

[0231] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, the present disclosure will not elaborate on them.

[0232] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0233] Based on the same inventive concept, the embodiment of the present disclosure also provides a data processing method corresponding to the data processing device. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to that of the above-mentioned data processing device in the embodiment of the present disclosure, the implementation of the method can refer to the implementation of the device, and the repeated parts will not be repeated.

[0234] The present disclosure also provides a data processing method, including:

[0235] In response to receiving the data processing instruction, the control unit generates a first instruction stream based on a preset data element reading order, and sends the first instruction stream to the conversion processing unit;

[0236] In response to receiving the first instruction stream, the conversion processing unit reads the first data element in the data to be processed from a preset storage space based on the data element reading order indicated by the first instruction stream, and stores the read first data element in the register stack; after the first data element stored in the register stack meets the preset conversion condition, the first data element is converted to obtain a second data element; wherein each second data element is converted from multiple first data elements, and the number of registers in the register stack is determined based on the data element reading order.

[0237] In an optional embodiment, the first instruction stream includes first data read instructions corresponding to a plurality of data read cycles respectively; each first data read instruction carries address information of a first data element to be read in the corresponding data read cycle;

[0238] The control unit generates a first instruction stream based on a preset data element reading order, including: obtaining a read cycle sequence corresponding to the data element reading order; the read cycle sequence includes: data read cycles corresponding to a plurality of first data elements in the data to be processed;

[0239] For each data reading cycle in the plurality of data reading cycles, determining, from the sequence of reading cycle numbers, index information of a first data element corresponding to the reading cycle number of the data reading cycle; the index information being used to represent a position of the corresponding first data element in the data to be processed;

[0240] Determining address information of a first data element corresponding to each data reading cycle based on a starting address, an address bit width, and the index information of the data to be processed;

[0241] A first data read instruction corresponding to each data read cycle is generated based on the address information of the first data element corresponding to each data read cycle.

[0242] In an optional embodiment, the control unit sends the first instruction stream to the conversion processing unit, comprising: in each data read cycle of the plurality of data read cycles, sending the first data read instruction corresponding to the data read cycle to the conversion processing unit;

[0243] The conversion processing unit reads the first data element in the data to be processed from the preset storage space, including: in each data reading cycle, in response to receiving the first data reading instruction corresponding to the data reading cycle sent by the control unit, based on the address information carried in the received first data reading instruction, reading the first data element corresponding to the data reading cycle from the preset storage space.

[0244] In an optional embodiment, the conversion processing unit stores the read first data element in a register stack connected to the conversion processing unit, including: in a current data reading cycle, determining a target register address corresponding to the current data reading cycle based on the number of registers in the register stack, an initial register address corresponding to the register stack, an address bit width of the register, and a register identifier corresponding to a previous data reading cycle;

[0245] Based on the target register address corresponding to the current data read cycle, the data elements read in the current data read cycle are stored in the corresponding register.

[0246] In an optional implementation, determining the target register address corresponding to the current data read cycle based on the number of registers in the register file, the initial register address corresponding to the register file, the address bit width of the register, and the register identifier corresponding to the previous data read cycle includes:

[0247] Determining a current register identifier corresponding to a current data reading cycle based on the number of registers in the register file and the register identifier corresponding to a previous data reading cycle;

[0248] A target register address corresponding to the current data read cycle is determined based on the current register identifier corresponding to the current data read cycle, the initial register address corresponding to the register stack, and the address bit width of the register.

[0249] In an optional implementation, the conversion processing unit includes: a first reading logic circuit;

[0250] The control unit sends the first instruction stream to the conversion processing unit, including: sending the first instruction stream to the first reading logic circuit;

[0251] The first reading logic circuit includes: in response to receiving the first instruction stream sent by the control unit, based on the data element reading order indicated by the first instruction stream, reading the first data element in the data to be processed from a preset storage space, and storing the read first data element in the register stack.

[0252] In an optional embodiment, the control unit further includes: generating a second instruction stream based on a preset data element conversion order and the data element reading order; and sending the second instruction stream to the conversion processing unit after the first data element read from the register file meets a preset conversion condition;

[0253] The conversion processing unit performs conversion processing on the first data element to obtain a second data element, including: in response to receiving the second instruction stream, based on the second instruction stream, reading multiple first data elements corresponding to the second data element from the register file, and performing conversion processing on the read first data elements to obtain corresponding second data elements.

[0254] In an optional embodiment, the second instruction stream includes: second data reading instructions corresponding to multiple data conversion cycles respectively; wherein the multiple data conversion cycles are determined based on the data element reading order, and after it is determined based on the data element reading order that the first data elements stored in the register stack include all the first data elements required for the second data elements corresponding to the current data conversion cycle, it is judged that the current data conversion cycle has been reached.

[0255] In an optional embodiment, the control unit generates the second instruction stream based on a preset data element conversion order and the data element reading order, including: for each data conversion cycle in a plurality of data conversion cycles, determining, from each first data element of the data to be processed, a target first data element required for a second data element corresponding to the data conversion cycle;

[0256] Determining, based on the data element reading order, data reading cycles corresponding to the target first data elements and register addresses in the register file;

[0257] Determining a target data read cycle associated with each data conversion cycle based on the data read cycles corresponding to the target first data elements; wherein the target data read cycle is used to indicate that after the target data read cycle is reached, a second data read instruction corresponding to the data conversion cycle is sent to the conversion processing unit;

[0258] A second data read instruction corresponding to each data conversion cycle is generated based on a target data read cycle associated with each data conversion cycle and the register addresses of the target first data elements in the register file.

[0259] In an optional embodiment, the control unit sends the second instruction stream to the conversion processing unit, comprising: in response to a current data read cycle reaching a target data read cycle corresponding to the current data conversion cycle, sending a second data read instruction corresponding to the current data conversion cycle to the conversion processing unit;

[0260] The conversion processing unit, in response to receiving the second instruction stream, reads multiple first data elements corresponding to the second data elements from the register file based on the second instruction stream, including: in response to receiving the second data processing instruction corresponding to the current data conversion cycle, based on the register addresses of the target first data elements indicated by the received second data processing instruction in the register file, reading the target first data elements corresponding to the current data conversion cycle.

[0261] In an optional implementation, the conversion processing unit includes: a second reading logic circuit;

[0262] The control unit sends the second instruction stream to the conversion processing unit, including: sending the second instruction stream to the second reading logic circuit;

[0263] The second reading logic circuit includes: in response to receiving the second instruction stream, reading a plurality of first data elements corresponding to the second data elements from the register file based on the second instruction stream.

[0264] In an optional implementation manner, the conversion processing unit further includes: a conversion circuit;

[0265] The conversion circuit includes: performing conversion processing on the first data element to obtain a second data element.

[0266] In an optional embodiment, the data processing instruction includes: a fast convolution processing instruction; the conversion processing includes: performing pre-processing corresponding to the fast convolution processing on the data to be processed;

[0267] The conversion circuit includes: an inversion circuit and an adder;

[0268] The negation circuit includes performing a negation process on a first data element to be negated to obtain a negated data element;

[0269] The adder adds the inverted data element and the first data element that does not need to be inverted to obtain a second data element corresponding to the pre-processing result.

[0270] In an optional embodiment, the method further includes: a data processing unit;

[0271] The conversion processing unit further includes sending the second data element to the data processing unit;

[0272] The data processing unit includes, in response to receiving the second data element sent by the conversion processing unit, executing the processing indicated by the data processing instruction on the second data element to obtain result data.

[0273] In an optional implementation, the data processing unit includes: a convolution module, a post-transformation unit, and an accumulation unit;

[0274] The convolution module comprises performing a convolution operation according to the second data element to obtain a convolution processing result of the converted data composed of the second data element;

[0275] The post-transformation unit includes performing a post-transformation operation on the convolution processing result to obtain post-transformation data;

[0276] The accumulation unit performs accumulation processing on each data element in the post-transformation data to obtain result data of performing fast convolution on the data to be processed.

[0277] In an optional embodiment, the method further includes: a pre-processing unit;

[0278] The pre-processing unit comprises determining the order in which the data elements are read.

[0279] In an optional implementation, the preprocessing unit, when determining the data element reading order, includes:

[0280] During each of the plurality of genetic mutation cycles, performing:

[0281] Performing genetic variation processing on a reading order of parent data elements corresponding to a current genetic variation cycle to obtain a reading order of child data elements corresponding to the current genetic variation cycle; the parent data element reading order includes: an original data element reading order, and / or a reading order of child data elements in a historical genetic variation cycle corresponding to the current genetic variation cycle, and / or a reading order of parent data elements in the historical genetic variation cycle;

[0282] Determine a first minimum register cache depth corresponding to a descendant data element reading order;

[0283] In response to a current genetic variation cycle satisfying a preset iteration stop condition, determining, based on the current iteration cycle, a second minimum register cache depth corresponding to a parent generation data element reading order corresponding to the current genetic variation cycle, and a first minimum register cache depth, the data element reading order from a historical parent generation data element reading order corresponding to the current genetic variation cycle and a historical child generation data element reading order;

[0284] In response to the current genetic variation cycle not satisfying the iteration stop condition, entering the next genetic variation cycle.

[0285] In an optional embodiment, the preprocessing unit, before performing genetic variation processing on the parent data element reading order corresponding to the current genetic variation cycle to obtain the child data element reading order corresponding to the current genetic variation cycle, further includes:

[0286] In response to the current genetic variation cycle being the first genetic variation cycle, determining the original data element reading order to be the parent data element reading order corresponding to the current genetic variation cycle;

[0287] In response to the current genetic variation cycle not being the first genetic variation cycle, a parent data element reading order corresponding to the current genetic variation cycle is determined based on a first minimum register cache depth corresponding to a historical child data element reading order of the historical genetic variation cycle and a second minimum register cache depth corresponding to a historical parent data element reading order of the historical genetic variation cycle.

[0288] An embodiment of the present disclosure further provides a data processing chip, comprising the data processing device as described in any embodiment of the present disclosure.

[0289] The present disclosure also provides a board, which includes a packaging structure encapsulating at least one of the above chips. Figure 6 , which provides an exemplary board card, the board card includes the above chip and may also include other components, including but not limited to: a storage device 601 and an interface device 604.

[0290] The memory device is connected to the chip within the chip package structure via a bus for storing data. The memory device may include multiple groups of memory cells 602, such as DDR SDRAM (Double Data Rate SDRAM). Each group of memory cells is connected to the chip via a bus.

[0291] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to implement data transmission between the chip and an external device 605 (e.g., a terminal, server, camera, etc.). In one embodiment, the interface device may include a PCIE interface, a network interface, or other interface, which is not limited in this disclosure.

[0292] An embodiment of the present disclosure further provides an electronic device, comprising the data processing device as described in any embodiment of the present disclosure, or the data processing chip as described in an embodiment of the present disclosure, or the board as described in an embodiment of the present disclosure.

[0293] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program executes the steps of the data processing apparatus described in the above method embodiment. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0294] The embodiments of the present disclosure also provide a computer program product, which carries program code. The instructions included in the program code can be used to execute the steps of the data processing device described in the above method embodiment. For details, please refer to the above method embodiment and will not be repeated here.

[0295] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0296] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0297] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0298] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0299] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0300] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The scope of protection of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present disclosure, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope of protection of the claims.

Claims

1. A data processing device, characterized in that: include: A control unit, a conversion processing unit, and a pre-processing unit; The control unit is configured to, in response to receiving a data processing instruction, generate a first instruction stream based on a preset data element reading order, and send the first instruction stream to the conversion processing unit; The conversion processing unit is configured to, in response to receiving the first instruction stream, read a first data element in the to-be-processed data from a preset storage space based on the data element reading order indicated by the first instruction stream, and store the read first data element in a register file; After a first data element stored in the register file meets a preset conversion condition, converting the first data element to obtain a second data element; wherein each second data element is obtained by converting a plurality of first data elements, and the number of registers in the register file is determined based on the order in which the data elements are read; The preprocessing unit is configured to determine the data element reading order; when determining the data element reading order, the preprocessing unit is configured to perform, in each genetic variation cycle of a plurality of genetic variation cycles: performing genetic variation processing on the parent data element reading order corresponding to the current genetic variation cycle to obtain the child data element reading order corresponding to the current genetic variation cycle; the parent data element reading order includes: the original data element reading order, and / or the child data element reading order of the historical genetic variation cycle corresponding to the current genetic variation cycle, and / or the parent data element reading order of the historical genetic variation cycle; determining a first minimum register cache depth corresponding to the child data element reading order; and in response to the current genetic variation cycle satisfying a preset iteration stop condition, Based on the current iteration cycle, based on the second minimum register cache depth corresponding to the parent data element reading order corresponding to the current genetic variation cycle, and the first minimum register cache depth, the data element reading order is determined from the historical parent data element reading order and the historical child data element reading order corresponding to the current genetic variation cycle; in response to the current genetic variation cycle not satisfying the iteration stop condition, entering the next genetic variation cycle; based on the determined data element reading order, determining whether the processing condition of any second data element can be met after all first data elements required for calculating any second data element are cached in the register; and determining the data element conversion order according to the order of timing at which each second data element satisfies the processing condition.

2. The data processing device according to claim 1, wherein The first instruction stream includes first data read instructions corresponding to a plurality of data read cycles respectively; each first data read instruction carries address information of a first data element to be read in the corresponding data read cycle; The control unit is configured to, when generating the first instruction stream based on a preset data element reading order, obtain a read cycle sequence corresponding to the data element reading order; The read cycle sequence includes: data read cycles corresponding to a plurality of first data elements in the data to be processed; For each data reading cycle in the plurality of data reading cycles, determining, from the sequence of reading cycle numbers, index information of a first data element corresponding to the reading cycle number of the data reading cycle; the index information being used to represent a position of the corresponding first data element in the data to be processed; Determining address information of a first data element corresponding to each data reading cycle based on a starting address, an address bit width, and the index information of the data to be processed; A first data read instruction corresponding to each data read cycle is generated based on the address information of the first data element corresponding to each data read cycle.

3. The data processing device according to claim 2, characterized in that The control unit, when sending the first instruction stream to the conversion processing unit, is configured to: in each data reading cycle of the plurality of data reading cycles, send a first data reading instruction corresponding to the data reading cycle to the conversion processing unit; The conversion processing unit, when reading the first data element in the data to be processed from the preset storage space, is used to: in each data reading cycle, in response to receiving the first data reading instruction corresponding to the data reading cycle sent by the control unit, read the first data element corresponding to the data reading cycle from the preset storage space based on the address information carried in the received first data reading instruction.

4. The data processing device according to claim 2 or 3, characterized in that The conversion processing unit is configured to, when storing the read first data element into a register file connected to the conversion processing unit, determine, in a current data reading cycle, a target register address corresponding to the current data reading cycle based on the number of registers in the register file, an initial register address corresponding to the register file, an address bit width of the register, and a register identifier corresponding to a previous data reading cycle; Based on the target register address corresponding to the current data read cycle, the data elements read in the current data read cycle are stored in the corresponding register.

5. The data processing device according to claim 4, characterized in that The determining, based on the number of registers in the register file, an initial register address corresponding to the register file, an address bit width of the register, and a register identifier corresponding to a previous data reading cycle, a target register address corresponding to the current data reading cycle includes: Determining a current register identifier corresponding to a current data reading cycle based on the number of registers in the register file and the register identifier corresponding to a previous data reading cycle; A target register address corresponding to the current data read cycle is determined based on the current register identifier corresponding to the current data read cycle, the initial register address corresponding to the register stack, and the address bit width of the register.

6. The data processing device according to any one of claims 1 to 5, characterized in that: The conversion processing unit includes: a first reading logic circuit; The control unit is configured to send the first instruction stream to the first reading logic circuit when sending the first instruction stream to the conversion processing unit; The first reading logic circuit is used to respond to receiving the first instruction stream sent by the control unit, read the first data element in the data to be processed from a preset storage space based on the data element reading order indicated by the first instruction stream, and store the read first data element in the register stack.

7. The data processing device according to claim 1, wherein: The control unit is further configured to generate a second instruction stream based on the data element conversion order and the data element reading order; and send the second instruction stream to the conversion processing unit after the first data element read from the register file meets a preset conversion condition; The conversion processing unit is used, when performing conversion processing on the first data element to obtain the second data element, to respond to receiving the second instruction stream, read multiple first data elements corresponding to the second data element from the register file based on the second instruction stream, and perform conversion processing on the read first data elements to obtain corresponding second data elements.

8. The data processing device according to claim 7, characterized in that The second instruction stream includes: second data read instructions corresponding to multiple data conversion cycles respectively; wherein the multiple data conversion cycles are determined based on the data element reading order, and after it is determined based on the data element reading order that the first data elements stored in the register stack include all the first data elements required for the second data elements corresponding to the current data conversion cycle, it is determined that the current data conversion cycle has been reached.

9. The data processing device according to claim 8, characterized in that The control unit is configured to, when generating the second instruction stream based on the data element conversion order and the data element reading order, determine, for each data conversion cycle in a plurality of data conversion cycles, from each first data element of the data to be processed, a target first data element required for a second data element corresponding to the data conversion cycle; Determining, based on the data element reading order, data reading cycles corresponding to the target first data elements and register addresses in the register file; Determining a target data read cycle associated with each data conversion cycle based on the data read cycles corresponding to the target first data elements; wherein the target data read cycle is used to indicate that after the target data read cycle is reached, a second data read instruction corresponding to the data conversion cycle is sent to the conversion processing unit; A second data read instruction corresponding to each data conversion cycle is generated based on a target data read cycle associated with each data conversion cycle and the register addresses of the target first data elements in the register file.

10. The data processing device according to claim 8 or 9, characterized in that: The control unit, when sending the second instruction stream to the conversion processing unit, is configured to: in response to a current data read cycle reaching a target data read cycle corresponding to the current data conversion cycle, send a second data read instruction corresponding to the current data conversion cycle to the conversion processing unit; The conversion processing unit, in response to receiving the second instruction stream, reads multiple first data elements corresponding to the second data element from the register file based on the second instruction stream, and is used to: in response to receiving the second data processing instruction corresponding to the current data conversion cycle, read the target first data element corresponding to the current data conversion cycle based on the register addresses of the target first data elements indicated by the received second data processing instruction in the register file.

11. The data processing device according to claim 7, characterized in that The conversion processing unit includes: a second reading logic circuit; The control unit is configured to send the second instruction stream to the second reading logic circuit when sending the second instruction stream to the conversion processing unit; The second read logic circuit is configured to, in response to receiving the second instruction stream, read a plurality of first data elements corresponding to second data elements from the register file based on the second instruction stream.

12. The data processing device according to claim 1, wherein: The conversion processing unit further includes: a conversion circuit; The conversion circuit is used to perform conversion processing on the first data element to obtain a second data element.

13. The data processing device according to claim 12, characterized in that The data processing instructions include: fast convolution processing instructions; the conversion processing includes: performing pre-processing corresponding to the fast convolution processing on the data to be processed; The conversion circuit includes: an inversion circuit and an adder; The negation circuit is configured to perform a negation process on the first data element to be negated to obtain a negated data element; The adder is used to add the inverted data element and the first data element that does not need to be inverted to obtain a second data element corresponding to the pre-processing result.

14. The data processing device according to claim 1, wherein: Also includes: Data processing unit; The conversion processing unit is further configured to send the second data element to the data processing unit; The data processing unit is configured to, in response to receiving a second data element sent by the conversion processing unit, execute the processing indicated by the data processing instruction on the second data element to obtain result data.

15. The data processing device according to claim 14, characterized in that The data processing unit includes: a convolution module, a post-transformation unit, and an accumulation unit; The convolution module is configured to perform a convolution operation on the second data element to obtain a convolution processing result of the converted data composed of the second data element; The post-transformation unit is configured to perform a post-transformation operation on the convolution processing result to obtain post-transformation data; The accumulation unit is used to perform accumulation processing on each data element in the post-transformation data to obtain result data of performing fast convolution on the data to be processed.

16. The data processing device according to claim 1, characterized in that The pre-processing unit is further configured to: In response to the current genetic variation cycle being the first genetic variation cycle, determining the original data element reading order to be the parent data element reading order corresponding to the current genetic variation cycle; In response to the current genetic variation cycle not being the first genetic variation cycle, a parent data element reading order corresponding to the current genetic variation cycle is determined based on a first minimum register cache depth corresponding to a historical child data element reading order of the historical genetic variation cycle and a second minimum register cache depth corresponding to a historical parent data element reading order of the historical genetic variation cycle.

17. A data processing method, characterized in that: include: In response to receiving the data processing instruction, the control unit generates a first instruction stream based on a preset data element reading order, and sends the first instruction stream to the conversion processing unit; In response to receiving the first instruction stream, the conversion processing unit reads a first data element in the data to be processed from a preset storage space based on the data element reading order indicated by the first instruction stream, and stores the read first data element in a register file; After a first data element stored in the register file meets a preset conversion condition, the first data element is converted to obtain a second data element; wherein each second data element is converted from multiple first data elements, and the number of registers in the register file is determined based on the order in which the data elements are read.

18. A data processing chip, characterized in that: The data processing device comprises the data processing device according to any one of claims 1 to 16.

19. A board, characterized in that: The invention comprises a package structure encapsulating at least one chip according to claim 18.

20. An electronic device, characterized in that: include: The data processing device according to any one of claims 1 to 16, or comprising the data processing chip according to claim 18 or the board according to claim 19.

21. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program. When the computer program is executed by an electronic device, the electronic device performs the steps of the data processing method according to claim 17.

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