Managing data structures in a plurality of memory devices that are indicated as degraded after the data structures are initialized

Abstract

A computer program product, system, and method for managing a data structure in a plurality of memory devices is provided, the data structure being indicated to be degraded after initialization of the data structure. The data structure is indicated to be degraded from a first-level memory device to a second-level memory device after initialization. The first-level memory device has a lower latency than the second-level memory device. In response to completing initialization of the data structure in the first-level memory device, the data structure indicated to be degraded after initialization is copied from the first-level memory device to the second-level memory device, and the data structure indicated to be moved after initialization is removed from the first-level memory device.

Description

Technical Field

[0001] The present invention relates to computer program products, systems and methods for managing data structures in a plurality of memory devices, the data structures being indicated to be demoted after initialization of the data structures. Background Art

[0002] Storage class memory (SCM) systems utilize low latency dynamic random access memory (DRAM) and one or more higher latency flash NAND memory devices that are cheaper than DRAM to provide greater storage in memory or cache at a lower cost by using higher latency, lower cost NAND devices. SCM allows system memory to be extended with fast access non-volatile memory NAND devices.

[0003] Flash memory devices have less durability than DRAM because there is a finite number of erase cycles for a flash memory bit cell, which is much less than a DRAM cell. One prior art technique for reducing wear on flash memory devices is to use wear leveling techniques that distribute writes across multiple flash memory cells in the same or different devices to avoid overuse of a particular flash memory cell.

[0004] There is a need in the art for improved techniques for managing data storage in multiple memory devices in a memory subsystem, such as an SCM system. Summary of the invention

[0005] A computer program product, system, and method for managing a data structure in a plurality of memory devices is provided, the data structure being indicated to be degraded after initialization of the data structure. The data structure is indicated to be degraded from a first-level memory device to a second-level memory device after initialization. The first-level memory device has a lower latency than the second-level memory device. In response to completing initialization of the data structure in the first-level memory device, the data structure indicated to be degraded after initialization is copied from the first-level memory device to the second-level memory device, and the data structure indicated to be moved after initialization is removed from the first-level memory device.

[0006] Through the above-described embodiments, data structures that are less frequently accessed can be moved to lower-level memory devices for continuous storage because they are infrequently accessed and can serve read access from lower-level memory devices. However, if a data structure that is indicated as degraded after initialization needs to be written, the data structure can be moved to the first-level memory device for one or more write operations to the data structure. When the write operation is completed, the data structure can be degraded from the first-level memory device and moved to the lower-level memory device because the data structure will be less likely to be written to for a considerable period of time.

[0007] In a further embodiment, access counts are maintained for data structures stored in the first level memory device that are not indicated to be degraded after initialization, wherein access counts are not maintained for data structures that are indicated to be degraded after initialization.

[0008] For the above-described embodiments, there is no need to count accesses to data structures that are automatically degraded after being updated or initialized, because they are vacated from the first-level memory device after use without regard to access counts.

[0009] In a further embodiment, the access count is used to select a data structure to be removed from the first level memory device and retained in the second level memory device to free up space in the first level memory device. The access count is used to determine whether to remove the accessed data structure from the second level memory device.

[0010] Through the above-described embodiments, using access counts to determine whether to store a data structure in a low-latency memory device or a high-latency memory device allows optimizing system performance by placing high access count data in low-latency memory devices and improving system performance by placing low access count data in higher latency memory devices, which will have less impact on system performance because low access count data is accessed less frequently.

[0011] In another embodiment, an update to a data structure indicated to be downgraded after initialization is received. The data structure to be updated is copied from the second level memory device to the first level memory device for updating. The updated data structure is copied from the first level memory device to the second level memory device, and the updated data structure is deleted from the first level memory device.

[0012] With the above-described embodiments, system performance is improved by moving updated data structures indicated to be degraded after initialization to a lower latency memory device to perform the update. The data structures are then deleted from the first level memory device after the update because the data structures indicated to be degraded after initialization are assumed to be accessed very infrequently and are therefore unlikely to be accessed.

[0013] A computer program product, system, and method for managing data in a plurality of memory devices in a computing system are also provided. An update to a data structure indicating a downgrade from a first-level memory device is received. The data structure to be updated is copied from a second-level memory device to the first-level memory device for updating. The first-level memory device has a lower latency than the second-level memory device. In response to updating the data structure, the updated data structure is copied from the first-level memory device to the second-level memory device and deleted from the first-level memory device.

[0014] Using the above-described embodiments, system performance is improved by moving updated data structures indicated for degradation to lower latency memory devices to perform the update, and then deleting them from the first-level memory devices after the update, because the data structures indicated for degradation after initialization are assumed to be less frequently accessed and are less likely to be accessed. Removing infrequently accessed data structures from low-latency devices to higher-latency devices for storage improves system performance by maximizing free space in the low-latency devices to be available for more frequently accessed data structures.

[0015] In a further embodiment, the update to the data structure is an update to at least one field to be updated in the data structure that is less than all fields in the data structure. Copying the data structure includes copying only the at least one field to be updated from the data structure to the first level memory device, wherein copying the updated data structure includes copying the updated at least one field from the first level memory device to the second level memory device, and deleting the updated at least one field from the first level memory device.

[0016] Through the above embodiments, by only copying the fields to be updated from the data structure in the second-level memory device to the first-level memory device for updating, the low-latency first-level memory space is further saved and optimized.

[0017] In a further embodiment, the data structure to be updated is in a second-level memory device. A determination is made as to whether the update includes an update event from a plurality of predefined update events. In response to determining that the update includes an update event, the data structure is copied for updating to the first-level memory device. As part of the update event, a plurality of writes to the data structure are performed. The data structure updated as part of the update event is copied from the first-level memory device to the second-level memory device, and the updated data structure is deleted from the first-level memory device in response to completing the write to the update event.

[0018] For the above-described embodiment, if the data structure to be degraded after updating or initialization will be subjected to write burst, then they are copied to the first-level storage device, although usually it is not frequently accessed. As a part of the operation of updating the system configuration file, this data structure can be periodically classified in the first-level storage device, so that burst writes are carried out. Because this configuration file is not frequently updated, so after the update event, the system data structure can be moved back to the storage device of lower level for storage and access. This releases the space in the faster access first-level storage device for other more frequently accessed data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1An embodiment of a computing environment having a memory subsystem including multiple memory devices is shown.

[0020] Figure 2 Embodiments of data structure information for managing storage of data structures in a memory device are shown.

[0021] Figure 3 An embodiment of operations for performing system initialization to generate initial system data structures is shown.

[0022] Figure 4 An embodiment of operations for handling access requests for a single copy situation is shown, where only a single copy of a data structure is stored in the entire memory subsystem.

[0023] Figure 5 An embodiment of operations for performing memory management operations to free up space in a first-level memory device for a single copy case is shown, where only a single copy of a data structure is stored in the entire memory subsystem.

[0024] Figure 6 An embodiment of operations for handling access requests for a multiple copy situation is shown, where multiple copies of a data structure are stored throughout a memory subsystem.

[0025] Figure 7 An embodiment of operations for performing memory management operations to free up space in a first-level memory device for a multiple copy situation is shown, where multiple copies of a data structure are stored throughout a memory subsystem.

[0026] Figure 8 An embodiment of operations for handling access requests for a multiple copy situation is shown, where multiple copies of a data structure with separate update and read counts are stored throughout a memory subsystem.

[0027] Fig. 9 An embodiment of operations for performing memory management operations to free up space in a first-level memory device for a multiple copy situation is shown, where multiple copies of a data structure with separate update and read counts are stored throughout a memory subsystem.

[0028] Fig.10 An embodiment of operations for performing system initialization and generating data structures in a memory subsystem having multiple memory devices is shown.

[0029] Fig.11 Embodiments of operations for handling access to a data structure in a memory subsystem of multiple memory devices that is degraded after initialization are shown.

[0030] Fig.12It shows that it can be realized Figure 1 The computing environment of the components. DETAILED DESCRIPTION

[0031] System control structures used to define logical devices in a computing system can be maintained in main DRAM memory. However, as DRAM reaches nearly full levels, time-consuming memory management processes are used to move data structures in DRAM to lower-level memory devices, such as higher-latency NAND-type flash memory or disk storage devices.

[0032] The described embodiments provide improved computer techniques for managing data structures in a memory subsystem that includes multiple different levels of memory devices with different characteristics, such as a first-level memory device with the lowest latency, such as DRAM, and different higher latency, cheaper lower-level memory devices, such as NAND flash memory. For the described embodiments, access counts are used to determine when to move a data structure from a first-level memory device to a lower-level memory device with higher latency. Access counts can also be used to determine whether to maintain multiple copies of a data structure in a first-level memory device and a lower-level memory device based on access thresholds maintained for different lower-level memory devices to match the placement of the data structure in a lower-level memory device with an appropriate durability profile (e.g., number of erase cycles) to the access count profile of the data structure.

[0033] In further embodiments, access counts may be used to determine whether to maintain multiple copies of a data structure in multiple memory devices or to keep only in a first-level memory device when the data structure is accessed. Less frequently accessed data structures may be indicated as swappable compared to the most frequently updated data structures to allow storage in lower-level memory devices with higher latency, while the most frequently accessed data structures may not be swappable and maintained in the lowest latency first-level memory device.

[0034] In addition, the access counts may include separate read and update counts for determining whether to move less frequently updated data structures to lower-level memory devices. In addition, lower-level memory devices with higher endurance (e.g., allowing more erase cycles) may be more expensive, and only the data structures with the highest access counts are placed in those lower-level memory devices with higher endurance, and those data structures with lower update counts may be stored in cheaper lower-level memory devices with lower endurance (e.g., allowing fewer erase cycles). This allows for optimizing the placement of data structures in lower-level memory devices by matching data structures with update counts to lower-level memory devices based on the persistence of the lower-level memory devices.

[0035] Figure 1 An embodiment of a computing environment is shown. A plurality of hosts 102 may submit input / output (I / O) requests to a storage controller 104 over a network 106 to access data (e.g., logical unit numbers, logical devices, logical subsystems, etc.) at volumes 108 in a storage device 110. The storage controller 104 includes one or more processors 112 and a memory subsystem, such as a storage class memory (SCM) memory system, having a virtual memory manager 114 to manage placement of tracks in one of a plurality of memory devices, such as a first-level memory device 1161, a second-level memory device 1162, through an nth-level memory device 116. n The virtual memory manager 114 maintains data structure information 200 having information about data structures 1181, 1182, 1183, such as system data structures or objects generated by the operating system during system initialization, which the virtual memory manager 114 processes to determine one or more level memory devices 1161 on which to store system and other data structures. n The virtual memory manager 114 may also maintain an address translation table to provide translation services and map tracks in the volume 108 to the memory devices 1161 . . . 116 n The virtual memory manager 114 may also include an algorithm that performs wear leveling to distribute write operations to different memory devices 1162..116 n and different locations within memory devices such as solid state storage devices (SSD) or flash memory, which have a limited number of erase cycles to increase the availability of these lower level memory devices 1161..116 n In some embodiments, including a virtual memory manager 114 and a level memory device 1161 ... 116 n The memory subsystem may be used as a cache for the storage controller 104 or other computing devices.

[0036] Processor 112, virtual memory manager 114 and memory devices 1161..116 n The virtual memory manager 114 may communicate with different memory devices 116 1 . . . 116 through one or more bus interfaces 120 . In addition, the virtual memory manager 114 may communicate with different memory devices 116 1 . . . 116 through different types and separate bus and device interfaces. n For example, a local memory interface may be used to communicate with a first level memory device 1161, such as a DRAM, and a storage device interface may be used to communicate with lower level memory devices 1162..116 n Communications, such as Non-Volatile Memory Express (NVME) to communicate with flash memory and SSDs.

[0037] In one embodiment, the first level memory device 1161 may include high cost and very low latency devices such as dynamic random access memory (DRAM) or static random access memory (SRAM), and the lower level memory devices 1161..116 n May include cheaper and higher latency and higher capacity storage devices such as non-volatile random access memory (NVRAM), including magnetoresistive random access memory (MRAM), phase change memory (PCM), resistive random access memory (RRAM), spin transfer torque memory (STM-RAM), conductive bridge RAM (CBRAM), NAND memory devices such as flash memory and solid state drives (SSD), etc. In one embodiment, lower level memory 1162.......116 n may have different endurance profiles with different numbers of available erase cycles, such that the memory devices 1162..116 n A higher level in allows more memory than 1162..116 n The lower level in the memory device 116 has a greater number of erase cycles, i.e., greater endurance. i may have a lower level memory device 116 j Greater endurance, i.e., higher number of erase cycles, where i < j. There may be one or more lower-level memory devices 116 i .

[0038] The virtual memory manager 114 may include a separate process or hardware device implemented as microcode or firmware in a hardware device in the storage controller 104, such as in an application specific integrated circuit (ASIC). Alternatively, the virtual memory manager 114 may include a system having a processor that executes code loaded into a memory device. Further, the virtual memory manager 114 may be implemented as code loaded into the first level memory device 1161 and executed by the processor 112.

[0039] The storage device 110 may include one or more storage devices known in the art, such as solid-state storage devices (SSDs), magnetic hard disk drives, optical disks, tapes, etc. The storage device may also be configured as a device array, such as a just a bunch of disks (JBOD), a direct access storage device (DASD), a redundant array of independent disks (RAID), a virtualized device, etc. In addition, the storage device may include heterogeneous storage devices from different vendors or from the same vendor.

[0040] The network 106 may include a storage area network (SAN), a local area network (LAN), a wide area network (WAN), the Internet, an intranet, etc. Alternatively, the host 102 may be connected to the storage controller 104 via a bus interface, such as a peripheral component interconnect (PCI) bus interface and other interfaces known in the art.

[0041] Figure 2 Data structure information 200 showing the data structure i An example embodiment of an ... n an exchangeable tag 204 that is periodically moved between the first level memory devices 1161 and 1162, an update count 206 that indicates the number of times the data structure 202 is updated during the measurement period; a read count 208 that indicates the number of times the data structure 202 is read during the measurement period; a post-initialization degrade flag 210 that indicates whether the data structure 202 is degraded immediately after being generated in the first level memory device 1161; and a level memory device 1161..1162 that indicates the level memory device 1161..1162 in which the data structure 202 is currently stored. n The device pointer 212.

[0042] In one embodiment, the swappable flag 204 and the post-initialization degraded flag 210 may be set by an operating system developer or administrator based on an estimate of how often the data structures will be accessed. For example, the most frequently updated or accessed data structures may be marked as swappable to always remain in the fastest first-level memory device 1161. Less frequently accessed data structures 1181, 1182, 1183 may occasionally be swapped to lower-level memory devices 1162..116 n , to free up space in the first-level memory device 1161.

[0043] The update count 206 may be used to select a lower level memory device 116 i , on which data structures are stored to match the endurance or available erase cycles. For example, more frequently accessed data structures (those with higher update counts 206) may be placed on lower-level memory devices 116 with higher endurance. i In this way, the lower level memory devices 1162 . . . 116 n Each of the first level memory devices 1161 may be associated with a series of update counts. In an alternative embodiment, there may be only one access count for reading and / or writing, which is used to determine when to swap the data structure out of the first level memory device 1161 and select a lower level memory device 116. i To store the data structures being exchanged.

[0044] Data structure information 200 indicated as not exchangeable 204 i Access counts 206, 208 may not be maintained because the data structure is not managed between memory devices based on its accesses.

[0045] After initialization, the degraded flag 210 may be set for data structures that are also indicated as non-swappable 204, which are static and rarely but sometimes change. In this case, such infrequently accessed data structures may be moved to a lower-level memory device 116. i For continuous storage, there will be less frequent write accesses and read accesses from the lower level memory device 116. i However, if a write is required to a data structure indicated as degraded after initialization 210, the data structure may be moved to the first level memory device 1161 for one or more write operations to the data structure. When the write operation is complete, the data structure may be degraded from the first level memory device 1161 and moved to a lower level memory device 116. i , because the data structure will be unlikely to be accessed for a significant period of time.

[0046] In one embodiment, the data structures managed by the virtual memory manager 114 may include data structures generated during system initialization or initial microcode loading (IML), and include structures that provide configuration information for hardware devices and logical devices, paths and subsystems, device characteristics and settings. In alternative embodiments, the data structures may be generated by an application.

[0047] In some embodiments, the virtual memory manager 114 may periodically decrement access counts (such as update 206 and read 208 counts) to reduce the weight of accesses over time. This provides that the strength of the access counts is time sensitive and decays over time.

[0048] Figure 3 An embodiment of operations performed by the operating system of the storage controller 100 for system initialization of the storage controller 100 is shown, which may be maintained in the first-level memory device 1161 and the virtual memory manager 114. When the system initialization is initiated (at block 300), system data structures are generated (at block 302) and stored in the first-level memory device 1161. For each of the generated data structures that is indicated as degraded after initialization 210, the generated data structure is copied (at block 304) to the lowest-level memory device (e.g., the third level) and removed from the first-level memory device 1161.

[0049] Figure 4 shows that for the memory devices 1161..116n Only data structure 118 is kept i The single copy case of a copy of a data structure 118 is an embodiment of an operation performed by the virtual memory manager 114 to process an access request such as a read or write. When processing (at block 400) an access request, if (at block 402) the accessed data structure 118 i is not commutative 204, control passes to Fig.11 If (at block 402) the accessed data structure 118 i Data structure information 200 i The exchangeable tag 204 in the data structure 118 indicates i is exchangeable, then the access count is incremented (at block 406). Figure 4 and Figure 5 In some embodiments, there may be only one access count for read and / or write access.

[0050] If (at block 408) the accessed data structure 118 i In the first level memory device 1161, the access request is then executed (at block 410) at the first level memory device 1161. If the data structure 118 i If the data structure 118 is not in the first level memory device 1161, the virtual memory manager 114 will i From lower level memory device 116 i The first level memory device 1161 is copied (at block 412) from the lower level memory device 116 i Remove (at block 414) data structure 118 i , and updates the device pointer 212 to indicate the first-level memory device 1161.

[0051] for Figure 4 In one embodiment, the virtual memory manager 114 maintains data structures in the memory device 116. i A single copy in one of the 116 and when accessed, the swappable data structure is transferred from the lower level memory device 116 i Move to first level memory device 1161.

[0052] Figure 5 The memory device 116 is shown i One of the data structures 118 is maintained i1. The embodiment of the operation performed by the virtual memory manager 114 to free up space in the first-level memory device 1161 in the case of a single copy of the first-level memory device 1161. When starting (at block 500) memory management, if (at block 502) the amount of free space in the first-level memory device 1161 is above the memory threshold, then control ends. If (at block 502) the amount of free space is below the memory threshold, then the virtual memory manager 114 selects (at block 504) the data structure 118 in the first-level memory device 1161 that is indicated as swappable and has the lowest access count that satisfies the amount of free space. i The selected data structure is copied (at block 506) to the lower level memory device 116 i , removes it from the first level memory device 1161, and updates the device pointer 212 of the moved data structure to point to the lower level memory device 116 to which the data structure was added. i .

[0053] In one embodiment, the access count of the selected data structure may be used to determine the lower level memory device storing the data structure. i If the data structures are sorted by their durability in terms of erasure cycles, and lower numbered devices have higher durability than higher numbered devices (e.g., memory device 1162 has greater durability than memory device 1163), the data structure is placed in the memory device 116 that has the lowest level threshold that exceeds the data structure access count. i middle.

[0054] for Figure 5 In an embodiment, to free up space in the first level memory device 1161, the virtual memory manager 114 considers the data structure with the lowest access count because the data structure is updated and accessed less frequently and is most suitable for storage in the lower level memory devices 1162..116 n middle.

[0055] Figure 6 shows that the plurality of memory devices 1161..116 n Maintaining Data Structures in 118 i Embodiments of operations performed by virtual memory manager 114 to process access requests in the case of multiple copies of Figure 6 and Figure 7 In the embodiment of the present invention, there is an access count, including update 206 and / or read 208 counts. When processing (at block 600) an access request, if (at block 602) the accessed data structure 118 i is not commutative 204, control passes to Fig.11If (at block 602) the accessed data structure 118 i Data structure information 200 i The exchangeable tag 204 in the data structure 118 indicates i is exchangeable, then the access count is incremented (at block 606).

[0056] If (at block 608) the accessed data structure 118 i is in the first level memory device 1161, then the access request is executed (at block 610) at the first level memory device 1161. i If the data structure 118 is not in the first level memory device 1161, the virtual memory manager 114 will i From lower level memory device 116 i The data structure is copied (at block 612) to the first level memory device 1161, and the device pointer 212 is updated (at block 614) to indicate the first level memory device 1161. If (at block 616) the access request is an update, the copy of the data structure in the one or more memory devices is updated (at block 616).

[0057] The virtual memory manager 114 determines (at block 618) that there are more than 100 instances of the data structure 118. i The lower level memory device 116 with the lowest level threshold of access count j , which is the one having the most suitable data structure 118 for the selected i If (at block 620) data structure 118 i Not in the determined lower level memory device 116 j , the virtual memory manager 114 will store the data structure 118 i From the current data structure 118 i The lower level memory device 116 i The data is copied (at block 622) to the lower level memory device 116 having the determined lowest level threshold. j , and from the lower level memory device 116 from which the data structure is copied i Remove (at block 624) the data structure 118 i If (at block 620) the data structure 118 i The lower level memory device 116 has been determined i or has been copied to the determined lower level storage device 116 i (at block 622), the device pointer 212 is updated (at block 626) to indicate that the data structure 118 is now iThe lower level memory device 116 j .

[0058] for Figure 6 In an embodiment, the accessed data structure is moved to the first level memory device 1161 and is also retained in a lower level memory device having a durability commensurate with the access count of the data structure, which can be erased for a period of time. By matching the data structure by access count with the lower level memory device by durability, the data structure is stored in the lower level memory device having the durability level that best suits the access frequency of the data structure. In addition, if the access count of the data structure is above the highest level threshold of the second level memory device 1162, the data structure is removed from the memory device 1161 having the data structure. i The data structure is removed without moving the data structure to another memory level device because the access count is the same for the lower level memory device 1162..116 n Too high.

[0059] Figure 7 shows that when the multi-level memory devices 1161..116 n Maintaining Data Structures in 118 i 1161. When memory management is initiated (at block 700) for multiple copies, if (at block 702) the amount of free space in the first-level memory device 1161 is above the memory threshold, control ends. If (at block 702) the amount of free space is below the memory threshold, the virtual memory manager 114 selects (at block 704) the data structure 118 in the first-level memory device 1161 that is indicated as swappable and has the lowest access count that satisfies the amount of free space. i For each selected data structure 118 i The operations of blocks 706 through 718 are performed.

[0060] The virtual memory manager 114 determines (at block 708) that there are more than 100 instances of the data structure 118. i The lower level memory device 116 with the lowest level threshold of access count j , which is the one having the most suitable data structure 118 for the selected i If (at block 710) data structure 118 i Not in the determined lower level memory device 116 i , the virtual memory manager 114 will store the data structure 118 i The first level memory device 1161 is copied (at block 712) to a lower level memory device 116 having the determined lowest level threshold. iIf (at block 710) the data structure 118 i The lower level memory device 116 has been determined i or has been copied to the determined lower level memory device 116 i (at block 712), the data structure 118 is removed (at block 714) from the first level memory device 1161 i , and updates (at block 716) the device pointer 212 to indicate that the data structure 118 is now i The lower level memory device 116 i .

[0061] for Figure 7 In an embodiment, to free up space in the first level memory device 1161, the virtual memory manager 114 considers the data structure with the lowest access count because the data structure is less likely to be updated and accessed and is most suitable for storage in the lower level memory devices 1162..116 n The selected data structure with the lowest access count is removed from the first level memory device 1161 and retained in a lower level memory device 116 having a level threshold of access counts including the data structure to be moved. i middle.

[0062] Figure 8 shows that the plurality of memory devices 1161..116 n Maintaining Data Structures in 118 i 206 and read 208 counts. In processing (at block 800) an access request, if (at block 802) the accessed data structure 118 i is not commutative 204, control passes to Fig.11 If (at block 802) the accessed data structure 118 i Data structure information 200 i The exchangeable tag 204 in the data structure 118 indicates i If the access is commutative, then the update count 206 is incremented (at block 806) if the access is a write, and the read count 208 is incremented if the access is a read.

[0063] If (at block 808) the accessed data structure 118 i is in the first level memory device 1161, then an access (read or write) is performed (at block 810) at the first level memory device 1161. If (at block 808) the data structure 118 iIf the data structure 118 is not in the first level memory device 1161, the virtual memory manager 114 will i From lower level memory device 116 i The access request is copied (at block 812) to the first level memory device 1161, and the device pointer 212 is updated (at block 814) to indicate the first level memory device 1161. If (at block 816) the access request is an update, the first 1161 and lower level memory devices 1161 are updated (at block 818). i A copy of the data structure in .

[0064] If the access is to read (from block 816) or update data (from block 818), the virtual memory manager 114 determines (at block 820) whether there is more than one copy of the data structure 118. i The lower level memory device 116 that updates the lowest level threshold of the count 206 j , which is the one having the most suitable data structure 118 for the selected i If (at block 822) data structure 118 i Not in the determined lower level memory device 116 i , the virtual memory manager 114 will store the data structure 118 i From having data structure 118 i The lower level memory device 116 i The data is copied (at block 824) to the lower level memory device 116 having the determined lowest level threshold. j , and from the lower level memory device 116 i Remove (at block 826) data structure 118 i The data structure is in the lower level memory device 116 determined to have the lowest level threshold. j After the device pointer 212 is updated (at block 828) to indicate that the data structure 118 is now i The lower level memory device 116 j .

[0065] for Figure 8 In an embodiment, the accessed data structure is moved to the first level memory device 1161 and is also retained in a lower level memory device having a durability and erasable period commensurate with the update count of the data structure. By matching the data structure according to the update count with the lower level memory device according to the durability, the data structure is stored in the lower level memory device having the durability level most suitable for the update frequency of the data structure. In addition, if the update count of the data structure is higher than the highest level threshold of the second level memory device 1162, the data structure is removed from the memory level device 1161 having the data structure.i Remove the data structure without moving the data structure to another memory level device because the update count is for the lower level memory device 1162..116 n Too high for the durability profile.

[0066] Fig. 9 shows that when the multi-level memory devices 1161..116 n Maintaining Data Structures in 118 i 1161. When initiating (at block 900) memory management for a multiple copy situation with separate update and read counts, if (at block 902) the amount of free space in the first-level memory device 1161 is above the memory threshold, control ends. If (at block 902) the amount of free space is below the memory threshold, the virtual memory manager 114 selects (at block 904) a data structure 118 in the first-level memory device 1161 that is indicated as swappable and has the lowest update count 206 that satisfies the amount of free space. i For each selected data structure 118 i The operations of blocks 906 through 918 are performed.

[0067] The virtual memory manager 114 determines (at block 908) that there are more than 100 instances of the data structure 118. i The lower level memory device 116 that updates the lowest level threshold of the count 206 j , which is the one having the most suitable data structure 118 for the selected i If (at block 910) data structure 118 i Not in the determined lower level memory device 116 j , the virtual memory manager 114 will store the data structure 118 i The first level memory device 1161 is copied (at block 912) to a lower level memory device 116 having the determined lowest level threshold. j If (at block 910) the data structure 118 i The lower level memory device 116 has been determined j or has been copied to the determined lower level storage device 116 j (at block 912), the data structure 118 is removed (at block 914) from the first level memory device 1161 i , and updates (at block 916) the device pointer 212 to indicate that the data structure 118 is now i The lower level memory device 116 j .

[0068] for Fig. 9 In an embodiment, to free up space in the first level memory device 1161, the virtual memory manager 114 considers the data structure with the lowest update count because the data structure is updated less frequently and is most suitable for storage in the lower level memory devices 1162..116 n The selected data structure with the lowest update count is removed from the first level memory device 1161 and is retained in a lower level memory device 116 having a level threshold of update counts that includes the data structure to be moved. i middle.

[0069] Fig.10 An embodiment of operations performed by the virtual memory manager 114 is shown to generate data structures, such as a system type data structure during system initialization, including data structures that provide configuration information about logical subsystems, logical volumes, path groups, physical paths, logical paths, subsystem characteristics, and other configuration data. After performing system initialization (at block 1000), which may be initiated by a basic input operating system (BIOS), an initial microcode load (IML), or other boot device, the system data structure is generated and stored (at block 1002) in the first level memory device 1161 as part of the system initialization. The generated system data structure 118 is updated (at block 1004). i Data structure information 200 i 1006) the data structure 118. i , its data structure information 200 i Indicate in field 210 that the data structure is degraded after initialization. The determined data structure is copied (at block 1008) from the first level memory device 1161 to the selected lower level memory device 116 i The selected lower-level memory device may be selected based on the access count or update count to select a lower-level memory device having an endurance profile suitable for the access or update count of the data structure, such as with respect to Figure 7 and Fig. 9 as described.

[0070] The copied determined data structure 118 is removed (at block 1010) from the first level memory device 1161 i , and updates (at block 1012) the data structure 118 for the move i The device pointer 212 is used to indicate the selected lower level memory device to which the data structure is moved.

[0071] for Fig.10In an embodiment, data structures indicated for degradation (which may include those system data structures that are rarely accessed) are moved to the appropriate lower-level memory device 116. i , because their infrequent access pattern indicates that they will not need to be stored in the first-level memory device 1161 after being initialized during system initialization.

[0072] Fig.11 The process performed by the virtual memory manager 114 to process the non-swappable data structure 118 is shown. i (For example, in Figure 4 , 6 8 and 404, 604 and 804 call) of the access operation. In initiating (at block 1100) the non-exchangeable data structure 118 i , if (at block 1102) the non-exchangeable data structure 118 i If the degraded after initialization is not indicated in field 210, the virtual memory manager 114 provides (at block 1104) access to the data structure 118 in the first level memory device 1161. i If (at block 1102) data structure 118 i is in a degraded state after initialization, then if (at block 1106) the access is a read, the virtual memory manager 114 provides (at block 1108) a reference to the data structure 118 being accessed. i Data structure information 200 i The device pointer 212 in the level memory device 116 indicates i Data structures in 118 i Read access to the .

[0073] If (at block 1106) the access is a write, and if (at block 1110) the access to data structure 118 is i The update is not a member of a set of defined update events, then in data structure 118 i The lower level memory device 116 indicated by the device pointer 212 i The requested write is performed (at block 1112) at the virtual memory manager 114. If (at block 1110) the update is a member of a set of defined update events, the virtual memory manager 114 writes the data structure 114 to the virtual memory manager 114. i (or the specific field or portion to be updated) is copied (at block 1114) to the first level memory device 1161 and the device pointer 212 is updated to indicate the first level memory device 1161. Then, as part of the event, the data structure 118 is updated. iWhen the event-related write is completed (at block 1118), the virtual memory manager 114 updates the data structure 118. i or only the updated fields and portions are copied (at block 1120) from the first level memory device 1161 to the selected lower level memory device 116 i (eg, selected to reduce the lowest level of wear leveling, etc.), remove data structure 118 from first level memory device 1161 i , and updates the device pointer 212 to indicate the selected lower-level memory device 116 i .

[0074] In one embodiment, a defined set of events that triggers moving data structures to first-level storage device 1161 may include data structures that are less frequently updated as system configuration files, such as the addition or removal of logical subsystems, volumes, path groups, physical paths, and logical paths. Update events may also include updating configuration information with new subsystem characteristics and other information.

[0075] use Fig.11 The operation may be performed by degrading the memory device 116 which is primarily stored in the lower-level memory device 116 after being indicated as initialized. i Data structures in 118 i Periodically staged into the first level memory device 1161 for write bursts as part of an operation to update a system configuration file. Because the configuration file is updated less frequently, after an update event, the system data structure can be moved back to a lower level memory device for storage and access. This frees up space in the faster access first level memory device 1161 for other more frequently accessed data.

[0076] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0077] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0078] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0079] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, programming languages ​​include object-oriented programming languages, such as Java, Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" programming language or similar programming languages. The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider through the Internet). In some embodiments, in order to perform various aspects of the present invention, the electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0080] Aspects of the present invention are described herein with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to embodiments of the present invention. It will be understood that each frame of the flow chart and / or block diagram and the combination of frames in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0081] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0082] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0083] Flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in flow chart or block diagram can represent the module, segment or part of instruction, and it comprises one or more executable instructions for realizing the logical function of appointment.In some alternative embodiments, the function mentioned in the frame may not occur in the order mentioned in the figure.For example, two frames shown continuously can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved.It will also be noted that the combination of the frame in each frame of block diagram and / or flow chart illustration and block diagram and / or flow chart illustration can be realized by the dedicated hardware-based system of performing specified function or action or performing the combination of special hardware and computer instruction.

[0084] Figure 1 The computing components (including host 102 and storage controller 104) may be implemented in one or more computer systems, such as Fig.12 Computer system 1202 is shown. Computer system / server 1202 may be described in the general context of computer system executable instructions, such as program modules, executed by the computer system. In general, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer system / server 1202 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in local and remote computer system storage media including memory storage devices.

[0085] like Fig.12 As shown, computer system / server 1202 is shown in the form of a general-purpose computing device. Components of computer system / server 1202 may include, but are not limited to, one or more processors or processing units 1204, system memory 1206, and a bus 1208 that couples various system components including system memory 1206 to processor 1204. Bus 1208 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, these architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0086] Computer system / server 1202 typically includes a variety of computer system readable media. The media can be any available media that can be accessed by computer system / server 1202, and it includes volatile and nonvolatile media, removable and non-removable media.

[0087] System memory 1206 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 1210 and / or cache memory 1212. Computer system / server 1202 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 1213 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, and commonly referred to as a "hard drive"). Although not shown, a disk drive for reading from and writing to a removable, non-volatile disk (e.g., a "floppy disk") may be provided, as well as an optical drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media. In this example, each may be connected to bus 1208 via one or more data media interfaces. As will be further depicted and described below, memory 1206 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of an embodiment of the present invention.

[0088] By way of example and not limitation, a program / utility 1214 having a set (at least one) of program modules 1216, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in memory 1206. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. The components of computer 1202 may be implemented as program modules 1216 that generally perform the functions and / or methods of embodiments of the present invention as described herein. Figure 1 The systems may be implemented in one or more computer systems 1202, where if they are implemented in multiple computer systems 1202, the computer systems may communicate via a network.

[0089] The computer system / server 1202 may also communicate with one or more external devices 1218 such as a keyboard, a pointing device, a display 1220, etc., one or more devices that enable a user to interact with the computer system / server 1202, and / or any device that enables the computer system / server 1202 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 1222. In addition, the computer system / server 1202 may communicate with one or more networks via a network adapter 1224, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet). As shown, the network adapter 1224 communicates with other components of the computer system / server 1202 via a bus 1208. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with the computer system / server 1202. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0090] The terms “embodiment,” “embodiments,” “the embodiment,” “these embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments of the invention,” unless expressly stated otherwise.

[0091] The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless expressly stated otherwise.

[0092] Unless expressly stated otherwise, the enumerated listing of items does not imply that any or all of the items are mutually exclusive.

[0093] The terms "a", "an" and "the" mean "one or more" unless expressly stated otherwise.

[0094] Unless expressly stated otherwise, devices that are in communication with each other need not be in continuous communication with each other. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0095] The description of an embodiment with several components in communication with each other does not imply that all such components are required. Rather, various optional components are described to illustrate various possible embodiments of the invention.

[0096] When a single device or product is described herein, it will be apparent that more than one device / product (whether or not they collaborate) may be used in place of a single device / product. Similarly, where more than one device or product (whether or not they collaborate) is described herein, it will be readily apparent that a single device / product may be used in place of more than one device or product, or that a different number of devices / products may be used in place of the number of devices or programs shown. The functions and / or features of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such functions / features. Therefore, other embodiments of the present invention need not include the device itself.

[0097] For the purpose of illustration and description, the above description of various embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form disclosed. In light of the above teachings, many modifications and variations are possible. The scope of the present invention is not limited by this detailed description, but by the appended claims. The above description, examples and data provide a complete description of the manufacture and use of the composition of the present invention. Since many embodiments of the present invention can be made without departing from the scope of the present invention, the present invention lies in the appended claims.

Claims

1. A computer program product for managing data in a plurality of memory devices in a computing system, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein, the computer readable program code performing operations when executed, the operations comprising: indicating that a data structure as part of system initialization is downgraded from a first-level memory device to a second-level memory device, wherein the first-level memory device has lower latency than the second-level memory device, and wherein the data structure is identified as having a file or object name and includes configuration information of the system as part of the system initialization; and In response to generating the data structure in the first-level memory device, after completing system initialization, the data structure indicated as part of system initialization and downgraded is copied from the first-level memory device to the second-level memory device, and the data structure indicated as part of system initialization and downgraded is removed from the first-level memory device.

2. The computer program product of claim 1 , wherein the operations further comprise: receiving a read request for a data structure stored in the second level memory device; as well as Data is returned to the read request from the data structure stored in the second level memory device.

3. The computer program product of claim 1 , wherein the operations further comprise: Access counts of the data structures stored in the first level memory device that are not indicated as part of system initialization and degraded are maintained, wherein access counts of data structures indicated as part of system initialization and degraded are not maintained.

4. The computer program product of claim 3, wherein the operations further comprise: using the access count to select a data structure to remove from the first level memory device and retain in the second level memory device to free up space in the first level memory device; as well as The access count is used to determine whether to remove the accessed data structure from the second level memory device.

5. The computer program product of claim 1 , wherein the operations further comprise: receiving updates to data structures indicated as part of system initialization and degradation; copying the data structure to be updated from the second-level memory device to the first-level memory device for updating; as well as An updated data structure is copied from the first primary memory device to the second primary memory device, and the updated data structure is deleted from the first primary memory device.

6. A computer program product for managing data in a plurality of memory devices in a computing system, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein, the computer readable program code performing operations when executed, the operations comprising: receiving an update to a data structure indicated to be downgraded from a first-level storage device, wherein the data structure is identified as having a file or object name and includes configuration information of a system as part of system initialization, the data structure indicated to be downgraded from the first-level storage device to the second-level storage device as part of system initialization; copying a data structure to be updated from a second-level memory device to the first-level memory device for updating, wherein the first-level memory device has lower latency than the second-level memory device; and In response to updating the data structure, the updated data structure is copied from the first-level memory device to the second-level memory device, and the updated data structure is deleted from the first-level memory device.

7. A computer program product according to claim 6, wherein the update to the data structure is for at least one field in the data structure to be updated, which is less than all fields in the data structure, wherein copying the data structure includes copying only the at least one field to be updated from the data structure to the first-level memory device, wherein copying the updated data structure includes copying the updated at least one field from the first-level memory device to the second-level memory device and deleting the updated at least one field from the first-level memory device.

8. The computer program product of claim 6, wherein the data structure to be updated is in the second level memory device, wherein the operations further comprise: determining whether the update includes an update event from among a plurality of predefined update events; responsive to determining that the update includes the update event, copying the data structure to be updated to the first level memory device; performing a plurality of writes to the data structure as part of the update event; as well as In response to completing the writing of the update event, the data structure updated as part of the update event is copied from the first-level memory device to the second-level memory device, and the updated data structure is deleted from the first-level memory device.

9. The computer program product of claim 8, wherein the predefined update events include a plurality of update events that are members of a subset of update events including: adding or removing logical devices in the computing system, volumes in the computing system, path groups, physical paths, logical paths, and subsystem characteristics and other configuration changes.

10. The computer program product of claim 8, wherein the operations further comprise: In response to determining that the update does not include one of the plurality of predefined update events, performing the update of the data structure to be updated in the second level memory device.

11. A computer system comprising: a first level memory device; a second level memory device; A virtual memory manager that performs the following operations: indicating that a data structure as part of system initialization is downgraded from a first-level memory device to a second-level memory device, wherein the first-level memory device has lower latency than the second-level memory device, and wherein the data structure is identified as having a file or object name and includes configuration information of the system as part of the system initialization; as well as In response to generating the data structure in the first-level memory device, after completing system initialization, the data structure indicated as part of system initialization and downgraded is copied from the first-level memory device to the second-level memory device, and the data structure indicated as part of system initialization and downgraded is removed from the first-level memory device.

12. The system of claim 11, wherein the operations further comprise: receiving a read request for a data structure stored in the second level memory device; as well as Data is returned to the read request from the data structure stored in the second level memory device.

13. The system of claim 11, wherein the operations further comprise: Access counts of the data structures stored in the first level memory device that are not indicated as part of system initialization and degraded are maintained, wherein access counts of data structures indicated as part of system initialization and degraded are not maintained.

14. The system of claim 13, wherein the operations further comprise: using the access count to select a data structure to remove from the first level memory device and retain in the second level memory device to free up space in the first level memory device; as well as The access count is used to determine whether to remove the accessed data structure from the second level memory device.

15. The system of claim 11, wherein the operations further comprise: receiving updates to data structures indicated as part of system initialization and degradation; copying the data structure to be updated from the second-level memory device to the first-level memory device for updating; as well as An updated data structure is copied from the first primary memory device to the second primary memory device, and the updated data structure is deleted from the first primary memory device.

16. A computing system comprising: a first level memory device; a second level memory device; A virtual memory manager that performs the following operations: receiving an update to a data structure indicated to be downgraded from a first-level storage device, wherein the data structure is identified as having a file or object name and includes configuration information of a system as part of system initialization, the data structure indicated to be downgraded from the first-level storage device to the second-level storage device as part of system initialization; copying a data structure to be updated from a second-level memory device to the first-level memory device for updating, wherein the first-level memory device has lower latency than the second-level memory device; and In response to updating the data structure, the updated data structure is copied from the first-level memory device to the second-level memory device, and the updated data structure is deleted from the first-level memory device.

17. A system according to claim 16, wherein the update to the data structure is for at least one field in the data structure to be updated, which is less than all fields in the data structure, wherein copying the data structure includes copying only the at least one field to be updated from the data structure to the first-level memory device, wherein copying the updated data structure includes copying the updated at least one field from the first-level memory device to the second-level memory device and deleting the updated at least one field from the first-level memory device.

18. The system of claim 16, wherein the data structure to be updated is in the second level memory device, wherein the operations further comprise: determining whether the update includes an update event from among a plurality of predefined update events; responsive to determining that the update includes the update event, copying the data structure to be updated to the first level memory device; performing a plurality of writes to the data structure as part of the update event; as well as In response to completing the writing of the update event, the data structure updated as part of the update event is copied from the first-level memory device to the second-level memory device, and the updated data structure is deleted from the first-level memory device.

19. The system of claim 18, wherein the predefined update events include a plurality of update events that are members of a subset of update events including: adding or removing logical devices in the computing system, volumes in the computing system, path groups, physical paths, logical paths, and subsystem characteristics and other configuration changes.

20. The system of claim 18, wherein the operations further comprise: In response to determining that the update does not include one of the plurality of predefined update events, performing the update of the data structure to be updated in the second level memory device.

21. A method for managing data in a plurality of memory devices in a computing system, comprising: indicating that a data structure as part of system initialization is downgraded from a first-level memory device to a second-level memory device, wherein the first-level memory device has lower latency than the second-level memory device, and wherein the data structure is identified as having a file or object name and includes configuration information of the system as part of the system initialization; and In response to generating the data structure in the first-level memory device, after completing system initialization, the data structure indicated as part of the system initialization and downgraded is copied from the first-level memory device to the second-level memory device, and the data structure indicated as part of the system initialization and downgraded is removed from the first-level memory device.

22. The method according to claim 21, further comprising: receiving a read request for a data structure stored in the second level memory device; as well as Data is returned to the read request from the data structure stored in the second level memory device.

23. The method according to claim 21, further comprising: Access counts of the data structures stored in the first level memory device that are not indicated as part of system initialization and degraded are maintained, wherein access counts of data structures indicated as part of system initialization and degraded are not maintained.

24. The method according to claim 23, further comprising: using the access count to select a data structure to remove from the first level memory device and retain in the second level memory device to free up space in the first level memory device; as well as The access count is used to determine whether to remove the accessed data structure from the second level memory device.

25. The method of claim 23, further comprising: receiving updates to data structures indicated as part of system initialization and degradation; copying the data structure to be updated from the second-level memory device to the first-level memory device for updating; as well as An updated data structure is copied from the first primary memory device to the second primary memory device, and the updated data structure is deleted from the first primary memory device.

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