Memory array structure and method for determining resistance characteristics of access lines

Abstract

A memory array structure providing determination of resistance characteristics of access lines can include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and optionally a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. A method for determining resistance characteristics of access lines can include connecting the particular access line of the first block of memory cells to a driver and determining the resistance characteristics in response to a current level through the access line and a voltage level of the access line.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 954,057, filed on December 27, 2019, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to integrated circuits, and more particularly, in one or more embodiments, to memory array structures and methods for determining the resistance characteristics of access lines. Background Technology

[0004] Integrated circuit devices are ubiquitous in various electronic devices. A specific type includes memory devices, often simply referred to as memory. Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has become a ubiquitous source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high storage density, high reliability, and low power consumption. The data state (e.g., data value) of each memory cell is determined by changes in the threshold voltage (Vt) of the memory cell, through programming (often referred to as writing) via charge storage structures (such as floating gates or charge traps) or other physical phenomena (such as phase transitions or polarization). Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, thus requiring a logical arrangement of the basic memory cell configuration. Typically, the memory cell array of a NAND flash memory device is arranged such that the control gates of each memory cell in a row of the array are connected together to form access lines, such as word lines. Columns of the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates (such as source-select transistors and drain-select transistors). Each source-select transistor can be connected to a source, and each drain-select transistor can be connected to a data line, such as a column bit line. Variations in using more than one select gate between the memory cell string and the source, and / or between the memory cell string and the data line, are known.

[0007] Due to the inherent variability in memory manufacturing, the physical properties of various circuit components often vary between different memories or between different sections of a single memory. Therefore, different operating parameters, such as voltage levels or timing characteristics, can be used for different memories or different sections of a single memory to produce similar operational results. Determining these operating parameters may involve performing tests on a memory containing various access operations using an initial set of operating parameters to establish baseline operating characteristics and adjusting the operating parameters in response to the test results until the desired operating characteristics are obtained. Attached Figure Description

[0008] Figure 1 This is a simplified block diagram of a memory that communicates with a processor, which is part of an electronic system, according to an embodiment.

[0009] Figures 2A to 2C It can be used for reference. Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 It can be used for reference. Figure 1 A schematic block diagram of the memory cell array and the string driver portion of a memory device of the described type.

[0011] Figure 4A is a conceptual perspective view of the memory array structure of the related technology.

[0012] Figure 4B This is a conceptual perspective view of a memory array structure according to an embodiment.

[0013] Figures 5A to 5B These are a side view and a plan view of the memory array structure according to the embodiment.

[0014] Figure 6 This illustrates a current path for testing according to an embodiment. Figure 4B A schematic diagram of the array structure.

[0015] Figure 7 This is a method for operating the memory according to an embodiment.

[0016] Figure 8A This is a schematic diagram of the connection from the embodiment to the memory array structure of the embodiment, which can be used for testing.

[0017] Figure 8B This is a schematic diagram of the connection to a memory array structure according to another embodiment, which can be used for testing.

[0018] Figure 8C This is a schematic diagram of the connection to a memory array structure according to another embodiment, which can be used for testing.

[0019] Figure 9 This is a method for operating the memory according to an embodiment.

[0020] Figure 10 Depicting according to the embodiment Figure 8B Timing of various parameters.

[0021] Figure 11 This is a method for operating the memory according to an embodiment.

[0022] Figure 12 Depicting according to the embodiment Figure 8C Timing of various parameters. Detailed Implementation

[0023] In the following detailed description, reference is made to the accompanying drawings, which form part of the description, and specific embodiments are illustrated by way of illustration. In the drawings, the same reference numerals describe substantially similar components throughout several views. Other embodiments may be utilized, and structural, logical, and electrical variations may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered as intended to be limiting.

[0024] As used herein, the term "semiconductor" may refer to, for example, a material layer, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referring to semiconductors in the following description, prior process steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term "semiconductor" may include an underlying layer containing such regions / junctions.

[0025] Unless otherwise understood from the context, the term “conductive” as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refers to electrical conductivity. Similarly, unless otherwise understood from the context, the term “connection” as used herein, and its various related forms (e.g., connect, via, connection, etc.), refers to electrical connection.

[0026] It should be recognized in this document that even if expected values ​​are equal, the variability and accuracy of industrial processing and operation can lead to values ​​different from their expected values. These variability and accuracy will typically depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if expected values ​​are equal, then the values ​​are considered equal, regardless of what they are obtained.

[0027] Figure 1 This is a simplified block diagram of a first device (in the form of a memory (e.g., a memory device) 100) communicating with a second device (in the form of a processor 130) that is part of a third device (in the form of an electronic system), according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0028] Memory device 100 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (typically called a word line), while memory cells in a logical column are typically selectively connected to the same data line (typically called a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) It can be programmed to one of at least two target data states.

[0029] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing commands, addresses, and data input to memory device 100 and data and status information output from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands. Trim register 127 may communicate with control logic 116. Trim register 127 may represent volatile memory, latches, or other storage locations, volatile or non-volatile. For some embodiments, trim register 127 may represent a portion of memory cell array 104. According to an embodiment, trim register 127 may store information related to the determination of the resistance value of the access line.

[0030] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and generates status information for external processor 130; that is, control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses. Control logic 116 may include instruction register 128, which may represent computer-usable memory for storing computer-readable instructions. For some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells of memory cell array 104, such as a reserved block of memory cells.

[0031] Control logic 116 also communicates with cache register 118. Cache register 118, guided by control logic 116, latches incoming or outgoing data to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 to memory cell array 104; subsequently, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to external processor 130; subsequently, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer for memory device 100 (e.g., may form a portion of the page buffer for memory device 100). The page buffer may further include sensing means for sensing the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells in the memory cell array 104. Figure 1 (Not shown in the image). Status register 122 can communicate with I / O control circuitry 112 and control logic 116 to latch status information for output to processor 130.

[0032] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Additional or alternative control signals (not shown) may be received via control link 132 depending on the nature of the memory device 100. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via I / O bus 134.

[0033] For example, commands can be received at I / O control circuitry 112 via I / O bus 134 input / output (I / O) pins [7:0] and then written to command register 124. Addresses can be received at I / O control circuitry 112 via I / O bus 134 input / output (I / O) pins [7:0] and then written to address register 114. Data can be received at I / O control circuitry 112 via 8-bit device input / output (I / O) pins [7:0] or 16-bit device input / output (I / O) pins [15:0] and then written to cache register 118. Data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device. Although references are made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections from an external device (e.g., processor 130) to the memory device 100.

[0034] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated into different components or component sections of the integrated circuit device. For example, a single component or component section of the integrated circuit device can be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0035] In addition, while specific I / O pins are described according to general conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0036] Figure 2A It can be used for reference. Figure 1 A schematic diagram of a portion (e.g., a portion of memory cell array 200A, such as a NAND memory array) of the described type of memory. Memory array 200A includes access lines (e.g., word lines 2020 to 202). N ) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected to in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. For some embodiments, the memory array 200A may be formed on a semiconductor, for example, the semiconductor may be conductively doped to have a conductivity type, such as p-type conductivity (e.g., for forming a p-well) or n-type conductivity (e.g., for forming an n-well).

[0037] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a series of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for data storage. The memory cell 208 of each NAND string 206 may be connected in series with select gate 210 (e.g., field-effect transistor) (e.g., select gates 2100 to 210). M One of them (for example, it could be a source-select transistor, often referred to as the selector source) and selector 212 (for example, a field-effect transistor) (for example, selectors 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain). Select gates 2100 to 210 M They can be connected together to select line 214 (e.g., source select line (SGS)), and select gates 2120 to 212. M They can be connected together to select line 215 (e.g., drain select line (SGD)). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, wherein each select gate in series is configured to receive the same or independent control signal.

[0038] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0039] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0040] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and substantially parallel to the plane containing the bit line 204.

[0041] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., through changes in a threshold voltage), and a control gate 236, such as... Figure 2A The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0042] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but is not required to) contain all memory cells 208 commonly connected to a given word line 202. Multiple rows of memory cells 208 may typically be divided into one or more physical page groups of memory cells 208, and the physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202... N Furthermore, the memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be memory cells 208 that comprise a single physical page (e.g., an even-numbered memory cell), while those commonly connected to word line 202... N Furthermore, the memory cells 208 selectively connected to odd-numbered bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be memory cells 208 of another physical page (e.g., odd-numbered memory cells). Although Figure 2A Although bit lines 2043 to 2045 are not explicitly depicted in the figure, it is evident from the diagram that bit lines 204 of the memory cell array 200A can be consecutively numbered from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For a given memory device, all memory cells commonly connected to a given word line can be considered physical pages of the memory cell. A portion of the physical page of a memory cell read during a single read operation or programmed during a single programmable operation (in some embodiments, this may still be an entire line) (e.g., the upper or lower page of the memory cell) can be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing common word line 202). Unless explicitly distinguished, the memory cell page referred to herein refers to the memory cell of the logical page of the memory cell.

[0043] although Figure 2A The examples are discussed in conjunction with NAND flash memory, but the embodiments and concepts described herein are not limited to a specific array architecture or structure, but may include other structures (such as SONOS or other data storage structures configured to store charge) and other architectures (such as AND arrays, NOR arrays, etc.).

[0044] Figure 2B It can be used for reference. Figure 1Another schematic diagram of a portion of the memory cell array 200B in a memory of the described type (e.g., a portion of the memory cell array 104). Figure 2B The same numbered elements in the text correspond to about Figure 2A The description provided. Figure 2B Additional details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, with portions of the pillars serving as channel regions for memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040 to 2046 via a select transistor 212 (e.g., a drain select transistor, commonly referred to as a select gate drain). M Furthermore, a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source) is selectively connected to a common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected by applying bias voltage to select lines 2150 to 215. K Selective selection transistors 212, each located between NAND string 206 and bit line 204, are selectively activated to connect to their respective bit lines 204. Selective transistors 210 can be activated by applying a bias voltage to select line 214. Each word line 202 can connect to multiple rows of memory cells in memory array 200B. Several rows of memory cells interconnected via specific word lines 202 can be collectively referred to as a hierarchy.

[0045] A three-dimensional NAND memory array 200B may be formed on a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used to access the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate, a process commonly referred to as CMOS or complementary metal-oxide-semiconductor. Although CMOS typically no longer utilizes strictly metal-oxide-semiconductor constructions due to advancements in integrated circuit manufacturing and design, the name CMOS is retained for convenience.

[0046] Figure 2C It can be used for reference. Figure 1 Another schematic diagram of a portion of the memory cell array 200C in the type of memory described (e.g., a portion of the memory cell array 104). Figure 2C The same numbered elements in the text correspond to about Figure 2AThe provided description indicates that the memory cell array 200C may include a series-connected string of memory cells (e.g., a NAND string) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as shown below. Figure 2A As depicted in the diagram. For example, a portion of memory cell array 200A may be a portion of memory cell array 200C. Figure 2C The NAND string 206 is divided into several memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may represent those NAND strings 206 that are commonly associated with a single select line 215 (e.g., select line 2150). The source 216 for memory cell block 2500 may be the same as that for memory cell block 250. L The source of 216. For example, each memory cell block 2500 to 250 L They can be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 may not be directly connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 for any other memory cell blocks.

[0047] Data cable 2040 to 204 M It can be connected (e.g., selectively connected) to buffer portion 240, which may be a portion of the data buffer of the memory. Buffer portion 240 may correspond to a memory plane (e.g., a set of memory cell blocks 2500 to 250). L ). Buffer section 240 may include sensing circuitry ( ). Figure 2C (Not shown) is used to sense the data value indicated on the corresponding data line 204.

[0048] Figure 3 It can be used for reference. Figure 1 A schematic diagram of a portion of the memory cell array and a string driver in a memory device of the described type, and depicts a many-to-one relationship between local access lines (e.g., local word lines) 202 and global access lines (e.g., global word lines) 302.

[0049] like Figure 3 As depicted, multiple memory cell blocks 250 can selectively connect their local access lines (e.g., local word lines) 202 to multiple global access lines (e.g., global word lines) 302. For simplicity, drain select lines and source select lines and their corresponding transistors are not depicted. Although Figure 3Only memory cell blocks 2500 and 250 are depicted. L (Blocks 0 and L), but the additional memory unit block 250 can have its local access lines 202 connected to the global access line 302 in the same manner. Similarly, although Figure 3 Only four local access lines 202 are depicted, but memory cell block 250 may contain fewer or more local access lines 202. Memory cell blocks 2500 to 250 L It can be a single plane belonging to a memory cell.

[0050] To facilitate memory access operations on a specific memory cell block 250 that is co-coupled to a given set of global access lines 302, each memory cell block 250 may have a set of corresponding block select transistors 346 that are one-to-one with its local access line 202. The control gates of the set of block select transistors 346 for a given memory cell block 250 may be connected together to the corresponding block select line 348. For example, for memory cell block 2500, local access line 202 00 Transistor 346 can be selected via block. 00 Selectively connect to global access line 3020 and local access line 202. 10 Transistor 346 can be selected via block. 10 Selectively connect to global access line 3021 and local access line 202. 20 Transistor 346 can be selected via block. 20 Selectively connected to global access line 3022, and local access line 202 30 Transistor 346 can be selected via block. 30 Selectively connected to global access line 3023, while block select transistor 346 00 Up to 346 30 In response to a control signal received on block select line 3480, the block select transistors 346 for memory cell block 250 may be collectively referred to as a string driver or simply a driver circuit system. For example, this driver circuit system may be formed in peripheral circuit system 226. Each block select transistor 346 may represent a selective connection from a local access line to its corresponding global access line. Voltage generation system 344 may be connected (e.g., selectively connected) to each global access line 302 to apply a corresponding voltage level to each global access line 302 for performing an access operation.

[0051] Figure 4A is a conceptual perspective view of a memory array structure related to the technology. (For example, regarding...) Figure 2B It is noted that the memory array structure can be hierarchical, with multiple rows of memory cells sharing a common access line. This can be achieved using several conductive plates. Figure 4A illustrates how such conductive plates can be connected to the global access line.

[0052] Figure 4A depicts two levels of two different memory blocks, for example, two levels corresponding to two corresponding global access lines (e.g., global access line 302a and global access line 302(a+1)) of each of two different memory blocks (e.g., memory blocks 250n and 250(n+1)). For example, memory block 250n in Figure 4A may correspond to... Figure 3 The memory cell block 2500, and the memory cell block 250(n+1) in Figure 4A can correspond to Figure 3 250 memory cell blocks L Similarly, for example, global access line 302(a+1) in Figure 4A can correspond to Figure 3 Global access line 3023, while global access line 302a in Figure 4A can correspond to Figure 3 Global access line 3022.

[0053] Global access line 302a can be selectively connected to local access line 202a-n of memory cell block 250n via block select transistors 346a-n, and can be selectively connected to local access line 202a-(n+1) of memory cell block 250(n+1) via block select transistors 346a-(n+1). Global access line 302(a+1) can be selectively connected to local access line 202(a+1)-n of memory cell block 250n via block select transistors 346(a+1)-n, and can be selectively connected to local access line 202(a+1)-(n+1) of memory cell block 250(n+1) via block select transistors 346(a+1)-(n+1). Block select transistors 346a-n and 346(a+1)-n can connect their control gates to block select line 348n. Block select transistors 346a-(n+1) and 346(a+1)-(n+1) can connect their control gates to block select line 348(n+1).

[0054] Local access lines 202a-n can be connected to conductive plates 452a-n, forming a portion of local access line 202a-n. Local access lines 202(a+1)-n can be connected to conductive plates 452(a+1)-n, forming a portion of local access line 202(a+1)-n. Local access lines 202a-(n+1) can be connected to conductive plates 452a-(n+1), forming a portion of local access line 202a-(n+1). Local access lines 202(a+1)-(n+1) can be connected to conductive plates 452(a+1)-(n+1), forming a portion of local access line 202(a+1)-(n+1). Conductive plates 452a-n and 452a-(n+1) can be manufactured as continuous conductive plates, and then isolated from each other by removing portions of the continuous conductive plates along their length 468 and filling the resulting gaps with a dielectric material to form an isolation region 454a. For example, the isolation region 454a can be formed of a dielectric material. Conductive plates 452a(a+1)-n and 452(a+1)-(n+1) can be manufactured as continuous conductive plates, and then isolated from each other by removing portions of the continuous conductive plates and filling the resulting gaps with a dielectric material to form an isolation region 454(a+1). For example, the isolation region 454(a+1) can be formed of a dielectric material.

[0055] Various embodiments facilitate the measurement of the resistance characteristics of the access line by providing a current loop through the access line. Measuring the resistance characteristics of the access line can be used to more accurately determine operating parameters, such as voltage level or timing characteristics, of other access lines considered to have similar characteristics. Figure 4B This is a conceptual perspective view of a memory array structure according to an embodiment. Figure 4B The same element symbols in the figure correspond to the description in Figure 4A.

[0056] like Figure 4BAs depicted, a conductive plate 452a can be utilized at the level corresponding to global access line 302a, wherein an isolation region 454a' extending the full length of the conductive plate 452a is not formed. In this way, a current path 456 (e.g., a direct electrical connection) can be formed between memory cell blocks 250n and memory cell blocks 250(n+1) of local access lines 202a-n and 202a-(n+1). In addition, a current path 458 (e.g., a direct electrical connection) can be formed between node 4600 of local access line 202a-(n+1) and node 4601 of local access line 202(a+1)-n. Node 460 can exist anywhere between its corresponding block select transistor 346 and its corresponding conductive plate 452 to form a portion of its corresponding local access line 202, which may be contained on its corresponding conductive plate 452. Isolation region 454(a+1)' can be similarly formed in conductive plate 452(a+1) to form a current path between memory cell block 250n and memory cell block 250(n+1) of local access lines 202(a+1) and 202(a+1)-(n+1) respectively.

[0057] A current path 456 can be formed for each level of memory cell blocks 250n and 250(n+1). Additionally, a current path 458 can be formed for each pair of levels of memory cell blocks 250n and 250(n+1). For example, refer to... Figure 3 Local access line 202 0L It can have access to local access line 202 10 Current path 458, local access line 202 1L It can have access to local access line 202 20 The current path 458, and the local access line 202 2L It can have access to local access line 202 30 The purpose of current paths 456 and 458 (e.g., intentional direct electrical connection of circuit elements that are normally electrically isolated from each other) will be described in more detail below.

[0058] It should be acknowledged that current paths 456 and 458 will typically render memory cell blocks 250n and 250(n+1) unusable for storing data. However, dummy memory cells are often used at the ends of series-connected memory cell strings to improve the operating characteristics of the memory cells in the series-connected memory cell strings where data is desired to be stored. These dummy memory cells typically have the same structure as the memory cells where data is desired to be stored. For similar reasons, dummy memory cell blocks can also be formed in memory cell arrays, wherein the dummy memory cell blocks are formed to have the same structure as the memory cell blocks where data is desired to be stored. Current paths 456 and 458 can therefore be formed in one or more dummy memory cell blocks without affecting the memory's storage capacity.

[0059] Figures 5A to 5B These are a side view and a plan view of the memory array structure according to the embodiment. Figures 5A to 5B Provide an example of forming a current path 458.

[0060] Three-dimensional memory array structures typically use a stepped structure for conductive plate 452. Figures 5A to 5B Four conductive plates 4520, 4521, 4522 and 4523 are depicted. For simplicity, the common source 216, select lines 214 and 215 and data line 204 are not depicted.

[0061] The conductive plate 4520 can be connected to the conductor 562 via the corresponding contact 5640. 0-0 And connected to conductor 562 via corresponding contact 5640. 0-1 562 per conductor 0-0 and 562 0-1 The two contacts 5640 can be connected to the peripheral circuit system 226, for example, to the corresponding block selection transistor. The conductive plate 4521 can be connected to the conductor 562 via the corresponding contacts 5641. 1-0 And connected to conductor 562 via corresponding contact 5641. 1-1 562 per conductor 1-0 and 562 1-1 The two contacts 5641 can be connected to the peripheral circuit system 226, for example, to the corresponding block selection transistor. The conductive plate 4522 can be connected to the conductor 562 via the corresponding contacts 5642. 2-0 And connected to conductor 562 via corresponding contact 5642. 2-1 562 per conductor 2-0 and 562 2-1 The two contacts 5642 can be connected to the peripheral circuit system 226, for example, to the corresponding block selection transistor. The conductive plate 4523 can be connected to the conductor 562 via the corresponding contacts 5643. 3-0 And connected to conductor 562 via corresponding contact 5643. 3-1 562 per conductor 3-0 and 562 3-1 The two contacts 5643 can be connected to the peripheral circuitry 226, for example, to the corresponding block select transistor. In this memory array structure, the current path 456 can be formed at the end of the corresponding conductive plate 452 opposite to the location where the conductive plate 452 provides a connection to its corresponding global access line 302.

[0062] Current path 458 0-1 Can be formed in conductor 562 0-1 With conductor 562 1-0 Between. Current path 458 1-2Can be formed in conductor 562 1-1 With conductor 562 2-0 Between. Current path 458 2-3 Can be formed in conductor 562 2-1 With conductor 562 3-0 Between. Current path 458 0-1 458 1-2 and 458 2-3 It can be formed by conductive material at the same level as conductor 562.

[0063] Current paths 456 and 458 provide current paths that can be used to determine the resistive characteristics of local access lines. Figure 6 This illustrates a current path for testing according to an embodiment. Figure 4B A schematic diagram of the array structure. Figure 6 The same reference element symbols in the figures correspond to their descriptions in Figures 4A and 4B.

[0064] refer to Figure 6 If block select line 348n receives a control signal with a logic high level to select memory cell block 250n, for example, and block select line 348(n+1) receives a control signal with a logic low level to deselect memory cell block 250(n+1), then current path 670 can be formed from global access line 302a through block select transistors 346a-n, through current path 456 to node 4600, through current path 458 to node 4601, and through block select transistors 346(a+1)-n to global access line 302(a+1). If a known voltage level is applied to global access line 302a when current path 670 is active, the resulting current level through global access line 302a can be used to calculate the resistance of current path 670, which can be used to provide an indication (e.g., an estimate) of the resistance of local access lines. For example, the resistance of current path 670 can be considered equal to the known voltage level divided by the resulting current level. Since the current path 670 passes essentially through two local access lines of two lengths (e.g., local access line 202a-(n+1) and local access line 202a-n), the resistance of the current path 670 can be divided by 2 to provide an indication (e.g., an estimate) of the resistance of local access lines 202a-n or 202a-(n+1). Similarly, the resistance characteristics of local access lines 202(a+1)-n and 202(a+1)-(n+1) can be determined by deactivating the active block select transistors 346a-n and 346(a+1)-n and 346(a+1)-(n+1).

[0065] Although the resistance of current path 670 includes only circuit elements other than conductive plate 452a, this is negligible compared to the resistance within conductive plate 452a alone. Nevertheless, refinement can be performed using the same circuit system. It should be noted that if both block select lines 348n and 348(n+1) receive a control signal with a logic high level, then the current path can be formed from global access line 302a through block select transistor 346a-(n+1) to node 4600, through current path 458 to node 4601, and through block select transistor 346(a+1)-n to global access line 302(a+1). If a known voltage level is applied to global access line 302a when this current path is active, the resulting current level through global access line 302a can be used to calculate the resistance of the current path without passing through conductive plate 452a. This resistor can be subtracted from the resistance of the current path 670, and it can be used to provide a refined or calibrated indication (e.g., an estimate) of the resistance of the portion of the local access line corresponding to its conductive plate.

[0066] Figure 7 This is a method for operating memory according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., related components of the memory) to perform the method.

[0067] At 701, each of the plurality of local access lines of the selected memory cell block can be connected to a corresponding global access line of the plurality of global access lines. At 703, the selected global access line of the plurality of global access lines can be connected to a driver. The driver can apply a known voltage level to the selected global access line or apply a known current level to the selected global access line. A first current path (e.g., current path 456) can be formed between the corresponding local access line of the selected memory cell block of the selected global access line and the local access line of an unselected memory cell block. A second current path (e.g., current path 458) can be formed between the local access line of an unselected memory cell block and a different local access line of the selected memory cell block. The unselected memory cell block can be adjacent to (e.g., immediately adjacent to) the selected memory cell block. The different local access lines of the selected memory cell block can be adjacent to (e.g., immediately adjacent to) the corresponding local access lines of the selected memory cell block of the selected global access line. At 705, a resistance value can be determined in response to the current level and voltage level of the selected global access line. The resistance value can be used to determine an indication of the resistance of the corresponding local access line of the selected memory cell, for example, R ≈ 0.5 * V / I. Although the selected memory cell may be unavailable for data storage due to current paths 456 and 458, the measurement of its resistance characteristics can be considered applicable to other memory cells, such as those manufactured near the selected memory cell. The determined resistance value can be stored (for example) in trimming register 127 to determine operating parameters for performing access operations in the memory.

[0068] Figure 8A This is a schematic diagram of the connection from the embodiment to the memory array structure of the embodiment, which can be used for testing. Figure 8A The same reference element symbols in the figures correspond to their descriptions in Figures 4A and 4B. Resistors 462a-n may represent the resistance of conductive plate 452a for local access lines 202a-n. Resistors 462(a+1)-n may represent the resistance of conductive plate 452(a+1) for local access lines 202(a+1)-n. Resistors 462a-(n+1) may represent the resistance of conductive plate 452a for local access lines 202a-(n+1).

[0069] Global access line 302a can be selectively connected to driver 829 via transistors (e.g., nFET) 821 and 823. Driver 829 can be, for example, a voltage generator configured to generate a known voltage level. Alternatively, driver 829 can represent a voltage node configured to receive a supply voltage. For example, a voltage node can be configured to receive a top rail supply voltage, such as the supply voltage Vcc. It should be noted that, for simplicity, the connection of global access line 302a, for example, used to generate and apply voltage levels for normal access operation, to the voltage generation circuitry is... Figure 8A Not described in the text.

[0070] Transistor 821 may be a global access line select transistor for selectively connecting global access line 302a to other circuitry (e.g., a voltage generator configured to provide different voltage levels to access the memory cell array). Transistor 821 may be responsive to a control signal received at node 825. Transistor 823 may be an enable transistor for the tests described herein. Transistor 823 may be responsive to a control signal received at node 827.

[0071] Global access line 302(a+1) can be selectively connected to node 835 via a transistor (e.g., an nFET) 831. Transistor 831 can be a global access line select transistor that selectively connects global access line 302(a+1) to other circuitry (e.g., a voltage generator configured to provide different voltage levels to access the memory cell array). Transistor 831 can be responsive to a control signal received at node 833. Node 835 can be a conductive node providing an electrical connection to an external device. For example, node 835 can be accessed during manufacturing or after packaging. The resistance values ​​of the current paths through resistors 462a-n, current path 456, resistor 462a-(n+1), and current path 458 to node 835 can be determined in response to the voltage level of driver 829 (e.g., the voltage difference between driver 829 and the voltage level of node 835) and the current level that can be measured at node 835.

[0072] Figure 8B This is a schematic diagram of the connection to a memory array structure according to another embodiment, which can be used for testing. Figure 8B The same reference element symbols in Figures 4A and 4B correspond to their symbols in Figures 4A and 4B. Figure 8A The description in [the text]. Although Figure 8A The circuitry provides a known voltage level to drive the global access line 302a, but Figure 8B The circuitry can provide a known current level to drive the global access line 302a.

[0073] Global access line 302a can be selectively connected to a driver, such as current source 841, via transistors (e.g., nFET) 821 and 823. Current source 841 (e.g., current mirror) can be connected to voltage node 843, which can be configured to receive a top rail supply voltage, such as the supply voltage Vcc. Current source 841 can generate a known current level Iref. It should be noted that, for simplicity, the connection of global access line 302a, for example, used to generate and apply voltage levels for normal access operation, to the voltage generation circuitry is... Figure 8B Not described in the text.

[0074] Transistor 821 may be a global access line select transistor for selectively connecting global access line 302a to other circuitry (e.g., a voltage generator configured to provide different voltage levels to access the memory cell array). Transistor 821 may be responsive to a control signal received at node 825. Transistor 823 may be an enable transistor for the tests described herein. Transistor 823 may be responsive to a control signal received at node 827.

[0075] Global access line 302(a+1) can be selectively connected to voltage node 845 via a transistor (e.g., an nFET) 831. Transistor 831 can be a global access line select transistor that selectively connects global access line 302(a+1) to other circuitry (e.g., a voltage generator configured to provide different voltage levels to access the memory cell array). Transistor 831 can be responsive to a control signal received at node 833. Voltage node 845 can be configured to receive a bottom rail supply voltage, such as a reference potential, for example, a supply voltage Vss, which can be ground or 0V.

[0076] After transistors 821 and 823 are activated, node 847 can be connected to global access line 302a and current source 841. Node 847 can be further connected to a first input (e.g., a non-inverting input) of comparator 849. A second input (e.g., an inverting input) of comparator 849 can be connected to voltage node 851. Voltage node 851 can be configured to receive a variable voltage level. Comparator 849 further includes an output 853. By changing the voltage level of voltage node 851 while applying a current level Iref to global access line 302a, the transition of output 853 of comparator 849 can be used to indicate the voltage level of global access line 302a in response to the application of current level Iref. The resistance values ​​of the current path through resistors 462a-n, current path 456, resistors 462a-(n+1), and current path 458 to voltage node 845 can be determined in response to the voltage level of voltage node 851 and the current level Iref determined in response to the transition of comparator 849.

[0077] Figure 8CThis is a schematic diagram of the connection to a memory array structure according to another embodiment, which can be used for testing. Figure 8C The same reference element symbols in Figures 4A and 4B correspond to their symbols in Figures 4A and 4B. Figure 8A The description in [the text]. Although Figure 8A The circuitry provides a known voltage level to drive the global access line 302a, but Figure 8C The circuitry can provide a known current level to drive the global access line 302a.

[0078] Figure 8C The circuitry provides an alternative current path between global access line 302a and the voltage node. For example, instead of using... Figure 8B The current path 458 described in the text Figure 8C The circuit provides a connection from global access line 302a to voltage node 845 without requiring it to be connected to another global access line.

[0079] Global access line 302a can be selectively connected to a driver, such as current source 841, via transistors (e.g., nFET) 821 and 823. Current source 841 (e.g., current mirror) can be connected to voltage node 843, which can be configured to receive a top rail supply voltage, such as the supply voltage Vcc. Current source 841 can generate a known current level Iref. It should be noted that, for simplicity, the connection of global access line 302a, for example, used to generate and apply voltage levels for normal access operation, to the voltage generation circuitry is... Figure 8C Not described in the text.

[0080] Transistor 821 may be a global access line select transistor for selectively connecting global access line 302a to other circuitry (e.g., a voltage generator configured to provide different voltage levels to access the memory cell array). Transistor 821 may be responsive to a control signal received at node 825. Transistor 823 may be an enable transistor for the tests described herein. Transistor 823 may be responsive to a control signal received at node 827.

[0081] Local access line 202a-(n+1) allows node 855 to be connected (e.g., selectively connected) to voltage node 845 via transistor (e.g., nFET) 831, as shown in dashed outline 857. Transistor 831 may be responsive to a control signal received at node 833. Voltage node 845 may be configured to receive a bottom rail supply voltage, such as a reference potential, such as a supply voltage Vss, which may be ground or 0V. Alternatively, node 855 of local access line 202a-(n+1) may be connected (e.g., directly connected without intermediate selective elements) to voltage node 845, as shown in dashed outline 857'. Node 855 of local access line 202a-(n+1) may be positioned with block select transistor 346a-(n+1) and ( ) for local access line 202a-(n+1) Figure 4B The resistance of the conductive plate 452a is between 462a-(n+1).

[0082] After transistors 821 and 823 are activated, node 847 can be connected to global access line 302a and current source 841. Node 847 can be further connected to a first input (e.g., a non-inverting input) of comparator 849. A second input (e.g., an inverting input) of comparator 849 can be connected to voltage node 851. Voltage node 851 can be configured to receive a variable voltage level. Comparator 849 further includes an output 853. By changing the voltage level of voltage node 851 while applying a current level Iref to global access line 302a, the transition of output 853 of comparator 849 can be used to indicate the voltage level of global access line 302a in response to the application of current level Iref. The resistance value of the current path through resistors 462a-n, current path 456, and resistors 462a-(n+1) to voltage node 845 can be determined in response to the voltage level of voltage node 851 and the current level Iref determined in response to the transition of comparator 849.

[0083] Figure 9 This is a method for operating memory according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., related components of the memory) to perform the method.

[0084] At 911, each of the plurality of local access lines of the selected memory cell block can be connected to a corresponding global access line of the plurality of global access lines. At 913, the selected global access line of the plurality of global access lines can be connected to a reference current and a first input of a comparator, the comparator having a second input connected to receive a reference voltage. A first current path (e.g., current path 456) can be formed between the corresponding local access line of the selected memory cell block of the selected global access line and the local access line of an unselected memory cell block. A second current path (e.g., current path 458) can be formed between the local access line of an unselected memory cell block and the corresponding local access line of the selected memory cell block of a different global access line of the plurality of global access lines. An unselected memory cell block can be adjacent to (e.g., immediately adjacent to) the selected memory cell block. The corresponding local access lines of the selected memory cell blocks of different global access lines can be adjacent to (e.g., immediately adjacent to) the corresponding local access lines of the selected memory cell blocks of the selected global access lines.

[0085] In 915, different global access lines can be connected to voltage nodes. Voltage nodes can be configured to receive a bottom rail supply voltage, such as a reference potential, for example, a supply voltage Vss, which can be ground or 0V. In 917, the voltage level of the reference voltage can be changed (e.g., increased) until the comparator output makes a specific transition. For example, if the comparator output has a first logic level (e.g., logic low) when the reference voltage level is lower than the voltage level of the selected global access line while a reference current is applied, and a second logic level (e.g., logic high) when the reference voltage level is higher than the voltage level of the selected global access line while a reference current is applied, then the specific transition of the comparator can be a transition from its first logic level to its second logic level in response to increasing the reference voltage level.

[0086] In 919, for example, in response to a specific transition of the comparator, the resistance value of the corresponding local access line of the selected memory cell block of the selected global access line can be determined in response to the current level of the reference current and the voltage level of the reference voltage that are considered to cause a specific transition of the comparator's output. For example, when the current level of the reference current is Iref and the voltage level of the reference voltage that is considered to cause a specific transition of the comparator's output is Vdet, the resistance value of the corresponding local access line of the selected memory cell block of the selected global access line can be considered equal to 0.5*Vdet / Iref. (See reference...) Figure 6 The discussion can be corrected.

[0087] Figure 10 Depicting according to the embodiment Figure 8B Timing of various parameters. Figure 10 Can correspond to reference Figure 9 The discussion focuses on the type of method. Trace 1061 can correspond to the current level of the reference current Iref over time. Trace 1063 can correspond to the voltage level of the reference voltage Vref over time. Trace 1065 can correspond to the voltage level of global access line 302a over time. Trace 1067 can correspond to the voltage level of global access line 302(a+1) over time. Trace 1069 can correspond to the voltage level of block select line 348n over time. Trace 1071 can correspond to the voltage level of block select line 348(n+1) over time. Trace 1073 can correspond to the logic level of the output 853 of comparator 849 over time.

[0088] At time t0, each of the global access lines 302 can be connected to receive a reference potential, such as ground or 0V. The block select line 348 can each provide a control signal with a logic low level. And the comparator 849 can have a logic low level at its output 853.

[0089] At time t1, block select line 348n provides a control signal with a logic high level to connect the local access line 202 of the selected memory cell block 250n to its global access line 302. Block select line 438(n+1) can remain at a logic low level to deselect memory cell block 250(n+1). Simultaneously, global access line 302a can be connected to the reference current Iref, for example, activated by transistors 821 and 823. Therefore, its voltage level can begin to increase. At time t2, in response to the voltage level of global access line 302a increasing to a point higher than the reference voltage Vref, the logic level of the output 853 of comparator 849 can transition to a logic high level.

[0090] At time t3, the reference voltage Vref can be increased from the initial voltage level 1075. The initial voltage level 1075 can be selected to be less than the expected voltage level of the global access line 302a in response to the applied reference current Iref. The voltage level of the reference voltage Vref can be selected to be 0V or it can be selected to be a higher voltage level. Selecting an initial voltage level 1075 higher than 0V can reduce the number of increases in the reference voltage Vref required to cause the output 853 of comparator 849 to change. Similarly, a smaller step increase in voltage level can promote a higher accuracy in resistance determination, while a larger step increase in voltage level can promote a higher determination speed.

[0091] In response to the reference voltage Vref increasing at time t3, the output 853 of comparator 849 maintains its logic level, and the reference voltage Vref may increase again at time t4. This process may be repeated at times t5, t6, t7, and t8. At time t9, in response to the reference voltage Vref increasing to a point higher than the voltage level of global access line 302a, the logic level of the output 853 of comparator 849 may transition to a logic low level. For some embodiments, the reference voltage Vref that is considered to cause a specific transition of the output 853 of comparator 849 may be voltage level 1077, such as the voltage level to which the reference voltage Vref increases at time t8. For other embodiments, the reference voltage Vref that is considered to cause a specific transition of the output 853 of comparator 849 may be voltage level 1079, such as the voltage level of the reference voltage Vref before its increase at time t8. In another embodiment, the voltage level of the reference voltage Vref, which is considered to cause a specific transition in the output 853 of comparator 849, can be determined in response to voltage level 1077 (e.g., the voltage level to which the reference voltage Vref increases at time t8) and voltage level 1079 (e.g., the voltage level of the reference voltage Vref before its increase at time t8). In such embodiments, for example, the voltage level of the reference voltage Vref, which is considered to cause a specific transition in the output 853 of comparator 849, can be the average of voltage levels 1077 and 1079.

[0092] Figure 11 This is a method for operating memory according to an embodiment. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory (e.g., related components of the memory) to perform the method.

[0093] At 1121, each of the plurality of local access lines of the selected memory cell block can be connected to a corresponding global access line of the plurality of global access lines. At 1123, the selected global access line of the plurality of global access lines can be connected to a reference current and a first input of a comparator, the comparator having a second input connected to receive a reference voltage. A current path (e.g., current path 456) can be formed between the corresponding local access line of the selected memory cell block of the selected global access line and the local access line of an unselected memory cell block. The unselected memory cell block can be adjacent to (e.g., immediately adjacent to) the selected memory cell block. The corresponding local access lines of the selected memory cell blocks of different global access lines can be adjacent to (e.g., immediately adjacent to) the corresponding local access lines of the selected memory cell blocks of the selected global access lines.

[0094] At 1125, the voltage level of the reference voltage can be changed (e.g., increased) until the comparator output makes a specific transition when a local access line of an unselected memory cell block is connected to the voltage node. The voltage node can be configured to receive a bottom rail supply voltage, such as a reference potential, for example, a supply voltage Vss, which can be ground or 0V.

[0095] For example, if the comparator output has a first logic level (e.g., logic low) when the reference voltage level is lower than the voltage level of the selected global access line and a second logic level (e.g., logic high) when the reference voltage level is higher than the voltage level of the selected global access line, then a specific transition of the comparator can be a transition from its first logic level to its second logic level in response to an increase in the reference voltage level.

[0096] In 1127, for example, in response to a specific transition of the comparator, the resistance value of the corresponding local access line of the selected memory cell block of the selected global access line can be determined in response to the current level of the reference current and the voltage level of the reference voltage that are believed to cause a specific transition of the comparator's output. For example, when the current level of the reference current is Iref and the voltage level of the reference voltage that is believed to cause a specific transition of the comparator's output is Vdet, the resistance value of the corresponding local access line of the selected memory cell block of the selected global access line can be considered equal to 0.5*Vdet / Iref.

[0097] Figure 12 Depicting according to the embodiment Figure 8C Timing of various parameters. Figure 12 Can correspond to reference Figure 11 The discussion focuses on the type of method. Trace 1261 can correspond to the current level of the reference current Iref over time. Trace 1263 can correspond to the voltage level of the reference voltage Vref over time. Trace 1265 can correspond to the voltage level of the global access line 302a over time. Trace 1269 can correspond to the voltage level of the block select line 348n over time. Trace 1271 can correspond to the voltage level of the block select line 348(n+1) over time. Trace 1273 can correspond to the logic level of the output 853 of comparator 849 over time.

[0098] At time t0, each of the global access lines 302 can be connected to receive a reference potential, such as ground or 0V. The block select line 348 can each provide a control signal with a logic low level. And the comparator 849 can have a logic low level at its output 853.

[0099] At time t1, block select line 348n provides a control signal with a logic high level to connect the local access line 202 of the selected memory cell block 250n to its global access line 302. Simultaneously, global access line 302a can be connected to a reference current Iref, for example, activated by transistors 821 and 823. Therefore, its voltage level can begin to increase. At time t2, in response to the voltage level of global access line 302a increasing to a point higher than the reference voltage Vref, the logic level of the output 853 of comparator 849 can switch to a logic high level.

[0100] At time t3, the reference voltage Vref can be increased from the initial voltage level 1275. The initial voltage level 1275 can be selected to be less than the expected voltage level of the global access line 302a in response to the applied reference current Iref. The voltage level of the reference voltage Vref can be selected to be 0V or it can be selected to be a higher voltage level. Selecting an initial voltage level 1275 higher than 0V can reduce the number of increases in the reference voltage Vref required to cause the output 853 of comparator 849 to change. Similarly, a smaller step increase in voltage level can improve the accuracy of resistance determination, while a larger step increase in voltage level can improve the determination speed.

[0101] In response to the reference voltage Vref increasing at time t3, the output 853 of comparator 849 maintains its logic level, and the reference voltage Vref may increase again at time t4. This process may be repeated at times t5, t6, t7, and t8. At time t9, in response to the reference voltage Vref increasing to a point higher than the voltage level of global access line 302a, the logic level of the output 853 of comparator 849 may transition to a logic low level. For some embodiments, the reference voltage Vref that is considered to cause a specific transition of the output 853 of comparator 849 may be voltage level 1277, such as the voltage level to which the reference voltage Vref increases at time t8. For other embodiments, the reference voltage Vref that is considered to cause a specific transition of the output 853 of comparator 849 may be voltage level 1279, such as the voltage level of the reference voltage Vref before its increase at time t8. In another embodiment, the voltage level of the reference voltage Vref, which is considered to cause a specific transition in the output 853 of comparator 849, can be determined in response to voltage level 1277 (e.g., the voltage level to which the reference voltage Vref increases at time t8) and voltage level 1279 (e.g., the voltage level of the reference voltage Vref before its increase at time t8). In such embodiments, for example, the voltage level of the reference voltage Vref, which is considered to cause a specific transition in the output 853 of comparator 849, can be the average of voltage levels 1277 and 1279.

[0102] in conclusion

[0103] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. Those skilled in the art will appreciate many adaptations to the embodiments. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory array structure, comprising: A first memory cell block includes a first plurality of local access lines, wherein each of the first plurality of local access lines is connected to the control gate of a corresponding plurality of memory cells of the first memory cell block. A second memory cell block includes a second plurality of local access lines, wherein each of the second plurality of local access lines is connected to the control gate of a corresponding plurality of memory cells of the second memory cell block. Multiple data lines, wherein each of the multiple data lines is selectively connected to a memory cell in a corresponding plurality of memory cells of a first memory cell block of each of the first plurality of access lines, and is selectively connected to a memory cell in a corresponding plurality of memory cells of a second memory cell block of each of the second plurality of access lines. A first current path, which serves as a direct electrical connection between a specific local access line in the first plurality of local access lines and a specific local access line in the second plurality of local access lines; and The second current path serves as a direct electrical connection between a specific local access line in the first plurality of local access lines and different local access lines in the second plurality of local access lines.

2. The memory array structure according to claim 1, wherein the specific local access line in the second plurality of local access lines is adjacent to the specific local access line in the first plurality of local access lines.

3. The memory array structure according to claim 1, wherein the specific local access line in the first plurality of local access lines and the specific local access line in the second plurality of local access lines each have a corresponding selective connection to the same global access line.

4. The memory array structure of claim 3, wherein the first current path is formed between the end of a particular local access line among the first plurality of local access lines opposite to its selective connection to the global access line and the end of the particular local access line among the second plurality of local access lines opposite to its selective connection to the global access line.

5. The memory array structure of claim 4, wherein the specific local access line in the first plurality of local access lines and the specific local access line in the second plurality of local access lines comprise a continuous conductive plate having an isolation region formed between the selective connection of the specific local access line in the first plurality of local access lines and the selective connection of the specific local access line in the second plurality of local access lines, and extending a majority length of the continuous conductive plate in a direction away from the selective connection.

6. The memory array structure according to claim 1, wherein for each of the first plurality of local access lines, the memory array structure further comprises: The corresponding first current path serves as a direct electrical connection between the local access line in the first plurality of local access lines and the corresponding local access line in the second plurality of local access lines.

7. A memory array structure, comprising: A first memory cell block includes a first plurality of local access lines, wherein each of the first plurality of local access lines is connected to the control gate of a corresponding plurality of memory cells of the first memory cell block. A second memory cell block includes a second plurality of local access lines, wherein each of the second plurality of local access lines is connected to the control gate of a corresponding plurality of memory cells of the second memory cell block. A first current path, which lies between a specific local access line in the first plurality of local access lines and a specific local access line in the second plurality of local access lines; and A second current path, which is between a specific local access line in the second plurality of local access lines and a different local access line in the first plurality of local access lines.

8. The memory array structure of claim 7, wherein the specific local access line in the second plurality of local access lines is adjacent to the specific local access line in the first plurality of local access lines.

9. The memory array structure according to claim 7, wherein the specific local access line in the first plurality of local access lines and the specific local access line in the second plurality of local access lines each have a corresponding selective connection to the same global access line.

10. The memory array structure of claim 9, wherein the first current path is formed between an end of a particular local access line among the first plurality of local access lines opposite to its selective connection to the global access line and an end of the particular local access line among the second plurality of local access lines opposite to its selective connection to the global access line.

11. The memory array structure of claim 10, wherein the specific local access line in the first plurality of local access lines and the specific local access line in the second plurality of local access lines comprise a continuous conductive plate having an isolation region formed between the selective connection of the specific local access line in the first plurality of local access lines and the selective connection of the specific local access line in the second plurality of local access lines, and extending a majority length of the continuous conductive plate in a direction away from the selective connection.

12. The memory array structure of claim 7, wherein the particular local access line among the first plurality of local access lines is adjacent to the different local access lines among the first plurality of local access lines.

13. The memory array structure of claim 12, wherein the memory array structure is a vertical structure, and wherein the specific local access line among the first plurality of local access lines is formed below the different local access lines among the first plurality of local access lines.

14. The memory array structure of claim 7, wherein the specific local access line and the different local access lines among the first plurality of local access lines are selectively connected to a corresponding global access line in response to the same control signal.

15. The memory array structure of claim 7, wherein the second current path extends from the first node to the second node, the first node being between a conductive plate forming a portion of the particular local access line in the second plurality of local access lines and a first select transistor selectively connecting the particular local access line in the second plurality of local access lines to a corresponding global access line, and the second node being between a conductive plate forming a portion of the different local access lines in the first plurality of local access lines and a second select transistor selectively connecting the different local access lines in the first plurality of local access lines to a corresponding global access line.

16. The memory array structure of claim 15, wherein the first node is on the conductive plate forming a portion of a particular local access line in the second plurality of local access lines, and wherein the second node is on the conductive plate forming a portion of a different local access line in the first plurality of local access lines.

17. The memory array structure of claim 7, wherein for each of the first plurality of local access lines, the memory array structure further comprises: The corresponding first current path is between the local access line in the first plurality of local access lines and the corresponding local access line in the second plurality of local access lines.

18. The memory array structure of claim 7, wherein for each local access line of a subset of the second plurality of local access lines, the memory array structure further comprises: The second current path is between the local access line in the second plurality of local access lines and the corresponding local access line in the first plurality of local access lines.

19. The memory array structure of claim 18, wherein the subset of the second plurality of local access lines includes all local access lines of the second plurality of local access lines except for one local access line.

20. A memory comprising: A memory cell array comprising a plurality of memory cell blocks, wherein each of the plurality of memory cell blocks includes a corresponding plurality of local access lines; and Controller, wherein the controller is configured such that the memory: Each of the corresponding plurality of local access lines of the selected memory cell block in the plurality of memory cell blocks is connected to the corresponding global access line in the plurality of global access lines. The selected global access line of the plurality of global access lines is connected to a reference current and a first input of a comparator, wherein the comparator has a second input connected to receive a reference voltage, and wherein a current path is formed between a corresponding local access line of the corresponding plurality of local access lines of the selected memory cell block of the selected global access line and a corresponding local access line of the corresponding plurality of local access lines of the unselected memory cell block of the plurality of memory cell blocks; The voltage level of the reference voltage is changed until the output of the comparator makes a specific transition when one of the corresponding plurality of local access lines of the unselected memory cell block is connected to a voltage node; and The resistance value of the respective local access line among the respective plurality of local access lines of the selected memory cell block of the selected global access line is determined in response to the current level of the reference current and the voltage level of the reference voltage that are believed to cause the specific transition of the output of the comparator.

21. The memory of claim 20, wherein the controller is configured to cause the memory to change the voltage level of the reference voltage, including the controller being configured to cause the memory to increase the voltage level of the reference voltage in a plurality of voltage level step increases.

22. The memory of claim 21, wherein the specific transition of the output of the comparator indicates that the voltage level of the reference voltage transitions from a voltage level below the voltage level of the selected global access line to a voltage level above the voltage level of the selected global access line.

23. The memory of claim 21, wherein the voltage level of the reference voltage deemed to cause the specific transition of the output of the comparator is selected from the group consisting of: the voltage level of the reference voltage after the last voltage level step increase in the plurality of voltage level step increases, the voltage level of the reference voltage after different voltage level step increases in the plurality of voltage level step increases immediately preceding the last voltage level step increase, and the voltage level of the reference voltage between the voltage level of the reference voltage after the different voltage level step increases and the voltage level of the reference voltage after the last voltage level step increase.

24. The memory of claim 20, wherein the controller is further configured such that the memory connects one of the respective plurality of local access lines of the unselected memory cell block to the voltage node.

25. The memory of claim 20, wherein the local access lines of the respective plurality of local access lines of the unselected memory cell block are directly connected to the voltage node.

26. A memory comprising: A memory cell array comprising a plurality of memory cell blocks, wherein each of the plurality of memory cell blocks includes a corresponding plurality of local access lines; and Controller, wherein the controller is configured such that the memory: Each of the corresponding plurality of local access lines of the selected memory cell block in the plurality of memory cell blocks is connected to the corresponding global access line in the plurality of global access lines. Connect the selected global access line from the plurality of global access lines to the driver, wherein: The first current path is formed between a corresponding local access line of the corresponding plurality of local access lines of the selected memory cell block of the selected global access line and a corresponding local access line of the corresponding plurality of local access lines of the unselected memory cell block of the plurality of memory cell blocks; and The second current path is formed between the local access line of the corresponding plurality of local access lines of the unselected memory cell block and the different local access lines of the corresponding plurality of local access lines of the selected memory cell block. and The resistance value is determined in response to the current level and voltage level of the selected global access line.

27. The memory of claim 26, wherein the resistance value is a first resistance value, and wherein the controller is further configured such that the memory: Connect the local access line of the unselected memory cell block to the corresponding global access line; A second resistance value is determined in response to a second current level and a second voltage level of the selected global access line; and Subtract the second resistance value from the first resistance value.

28. The memory of claim 26, wherein the controller is configured such that the memory connects each of the respective plurality of local access lines of the selected memory cell block to a respective global access line of the plurality of global access lines, further comprising the controller being configured such that the memory isolates each of the respective plurality of local access lines of the unselected memory cell block from a respective global access line of the plurality of global access lines.

29. The memory of claim 26, wherein the controller is configured such that the memory connects the selected global access line to the driver, comprising the controller being configured such that the memory connects the selected global access line to a driver selected from a group consisting of voltage drivers and current sources.

30. A memory comprising: A memory cell array comprising a plurality of memory cell blocks, wherein each of the plurality of memory cell blocks includes a corresponding plurality of local access lines; and Controller, wherein the controller is configured such that the memory: Each of the corresponding plurality of local access lines of the selected memory cell block in the plurality of memory cell blocks is connected to the corresponding global access line in the plurality of global access lines. A selected global access line from the plurality of global access lines is connected to a reference current and a first input of a comparator, wherein the comparator has a second input connected to receive a reference voltage, and wherein: The first current path is formed between a corresponding local access line of the corresponding plurality of local access lines of the selected memory cell block of the selected global access line and a corresponding local access line of the corresponding plurality of local access lines of the unselected memory cell block of the plurality of memory cell blocks; and The second current path is formed between the local access lines of the corresponding plurality of local access lines of the unselected memory cell block and the different local access lines of the corresponding plurality of global access lines of the selected memory cell block; and Connect the different global access lines to the voltage nodes; Change the voltage level of the reference voltage until the comparator output makes a specific transition; and The resistance value of the respective local access line among the respective plurality of local access lines of the selected memory cell block of the selected global access line is determined in response to the current level of the reference current and the voltage level of the reference voltage that are believed to cause the specific transition of the output of the comparator.

31. The memory of claim 30, wherein the controller is configured to cause the memory to change the voltage level of the reference voltage, including the controller being configured to cause the memory to increase the voltage level of the reference voltage in a plurality of voltage level step increases.

32. The memory of claim 31, wherein the specific transition of the output of the comparator indicates that the voltage level of the reference voltage transitions from a voltage level below the voltage level of the selected global access line to a voltage level above the voltage level of the selected global access line.

33. The memory of claim 31, wherein the voltage level of the reference voltage that is considered to cause the specific transition of the output of the comparator is selected from the group consisting of: the voltage level of the reference voltage after the last voltage level step increase in the plurality of voltage level step increases, the voltage level of the reference voltage after different voltage level step increases in the plurality of voltage level step increases immediately before the last voltage level step increase, and the voltage level of the reference voltage between the voltage level of the reference voltage after the different voltage level step increases and the voltage level of the reference voltage after the last voltage level step increase.

34. The memory of claim 30, wherein the controller is configured such that the memory connects the different global access lines to the voltage node, comprising the controller being configured such that the memory connects the different global access lines to a voltage node configured to receive a bottom rail supply voltage.

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