An over-temperature frequency reduction protection circuit
By introducing over-temperature reduction protection circuit into the power supply chip, the temperature signal is processed using transconductance amplifiers and error operation amplifiers to control the power tube shutdown time, the problem of power chip failure at high temperatures is solved, and effective temperature regulation and stability improvement is achieved.
Patent Information
- Application Number
- CN202210648881.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-09
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2042-06-09
AI Technical Summary
Existing power chips are prone to failure at high temperatures, resulting in chip burnout, and the existing technology is difficult to effectively avoid chip transition heating.
The over-temperature frequency reduction protection circuit is adopted, including bipolar transistor BJT, transconductance amplifier OTA, error operation amplifier OP, field effect transistor MOS and current source. The temperature signal is converted and amplified through the transconductance amplifier and error operation amplifier to control the power tube’s turn-off time to achieve cooling.
It realizes simple, reliable and low-cost temperature regulation, avoids chip transition heating, improves the sensitivity and stability of temperature regulation, and prevents chip damage.
Smart Images
Figure CN114935959B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits (ICs), and in particular to an over-temperature frequency reduction protection circuit. Background Art
[0002] Since the power chip integrates high-voltage and high-current power switching tubes, the power consumption will increase, thereby increasing the temperature of the chip. Excessive temperature will cause the semiconductor devices in the chip, such as field-effect tubes and triodes, to fail. After the operating temperature of the chip exceeds a certain temperature value, the failure rate of the chip will increase exponentially, and it is very likely to cause the chip to burn out. Summary of the Invention
[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a simple, reliable, easy to implement, low-cost over-temperature and frequency reduction protection circuit that can avoid excessive temperature rise of the chip.
[0004] To achieve the above-mentioned purpose, the technical solution provided by the present invention is an over-temperature frequency reduction protection circuit, comprising a bipolar transistor BJT, a transconductance amplifier OTA, an error operational amplifier OP, a field-effect transistor MOS, and three current sources I0, I5, and I6; the base of the bipolar transistor BJT is connected to the collector, and the connection point between the base and the collector is also connected to the current source I0 and the reverse input terminal of the transconductance amplifier OTA; the positive input terminal of the transconductance amplifier OTA is connected to the temperature adjustment reference voltage Vref_Treg, the output terminal of the transconductance amplifier OTA is connected to one end of the resistor R, and the transconductance amplifier The connection point between OTA and the resistor R is also connected to the current source I5 and the inverting input terminal of the error operational amplifier OP; the positive input terminal of the error operational amplifier OP is connected to one end of the capacitor C, and the connection point between the error operational amplifier OP and the capacitor C is also connected to the current source I6 and the drain of the field-effect transistor MOS. The source of the field-effect transistor MOS is connected to the other end of the capacitor C and the other end of the resistor R. The gate of the field-effect transistor MOS is connected to the PWM drive control signal. The output terminal of the error operational amplifier OP is used to output a signal Toffmin for controlling the off time of the power tube.
[0005] Preferably, a mirror current source is further provided between the transconductance amplifier OTA and the resistor R.
[0006] Further preferably, the mirror current source includes a 1:K mirror current source and a 1:M mirror current source, the drain of I1 in the 1:K mirror current source is connected to the output end of the transconductance amplifier OTA, the drain of I1 is also connected to the gate of I1 and the gate of I2 in the 1:K mirror current source, the source of I1 is connected to the source of I2, the drain of I2 is connected to the source of I3 in the 1:M mirror current source, the source of I3 is also connected to the gate of I3 and the gate of I4 in the 1:M mirror current source, the drain of I3 is connected to the drain of I4, and the source of I4 is connected to one end of the resistor R.
[0007] Further preferably, the connection point between the I1 source and the I2 source is also connected to the emitter of the bipolar junction transistor (BJT).
[0008] Preferably, the source of the field effect transistor MOS, the other end of the capacitor C, and the other end of the resistor R are all grounded.
[0009] Preferably, the capacitor C includes a chip ceramic capacitor.
[0010] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:
[0011] The over-temperature frequency reduction protection circuit provided by the present invention includes a bipolar transistor (BJT), a transconductance amplifier (OTA), an error operational amplifier (OP), a field-effect transistor (MOS), and three current sources (I0, I5, and I6). The base of the bipolar transistor (BJT) is connected to the collector, the current source (I0), and the reverse input terminal of the transconductance amplifier (OTA). The positive input terminal of the transconductance amplifier (OTA) is connected to a temperature adjustment reference voltage (Vref_Treg). The output terminal of the transconductance amplifier (OTA) is connected to one end of a resistor (R), the current source (I5), and the reverse input terminal of the error operational amplifier (OP). The positive input terminal of the error operational amplifier (OP) is connected to one end of a capacitor (C), the current source (I6), and the drain terminal of the MOS field-effect transistor (MOS). The source terminal of the MOS field-effect transistor (MOS) is connected to the other end of the capacitor (C) and the other end of the resistor (R). The gate of the MOS field-effect transistor (MOS) is connected to a PWM drive control signal. The output terminal of the error operational amplifier (OP) outputs a signal (Toffmin) for controlling the off-time of the power transistor. The circuit has a simple structure, uses mature components, is stable and reliable, easy to implement, and has low cost, and can prevent excessive heating of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 1 is a circuit diagram of a preferred embodiment of the present invention.
[0013] Figure 2 、 Figure 3 yes Figure 1 Implementation effect diagram, among which, Figure 2 The operating temperature of the chip is in the normal range. Figure 3 The operating temperature of the chip is in a state of transitional heating.
[0014] Wherein: 101. Bipolar junction transistor (BJT); 102. Transconductance amplifier (OTA); 103. Error operational amplifier (OP); 104. Field effect transistor (MOS); 105.1: K mirror current source; 106.1: M mirror current source. DETAILED DESCRIPTION
[0015] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.
[0016] like Figure 1 As shown, the over-temperature frequency reduction protection circuit provided by the present invention includes a bipolar transistor BJT101, a transconductance amplifier OTA102, an error operational amplifier OP103, a field effect transistor MOS104, and three current sources I0, I5, and I6; the base of the bipolar transistor BJT101 is connected to the collector, and the connection point between the base and the collector is also connected to the current source I0 and the reverse input terminal of the transconductance amplifier OTA102. At this time, the bipolar transistor BJT101 is equivalent to a diode with a negative temperature coefficient, V BE is the voltage between the base and emitter of the bipolar transistor BJT101, which has a negative temperature characteristic, and the voltage V BE The signal is input into the transconductance amplifier OTA102 and converted into a current signal for output; the positive input terminal of the transconductance amplifier OTA102 is connected to the temperature adjustment reference voltage Vref_Treg, the output terminal of the transconductance amplifier OTA102 is connected to one end of the resistor R, and the connection point between the transconductance amplifier OTA102 and the resistor R is also connected to the current source I5 and the reverse input terminal of the error operational amplifier OP103; the positive input terminal of the error operational amplifier OP103 is connected to one end of the capacitor C, and the connection point between the error operational amplifier OP103 and the capacitor C is also connected to the current source I6 and the drain of the field-effect transistor MOS104. The source of the field-effect transistor MOS104 is connected to the other end of the capacitor C and the other end of the resistor R. The gate of the field-effect transistor MOS104 is connected to the PWM drive control signal. The output terminal of the error operational amplifier OP103 is used to output the signal Toffmin for controlling the off time of the power transistor.
[0017] The advantage of this setting is that the circuit structure is simple, stable, reliable, easy to implement, low cost, can avoid excessive temperature rise of the chip, and the signal V is controlled by the transconductance amplifier OTA and the error operational amplifier OP. BE By performing conversion and amplification, the signal Toffmin for controlling the off time of the power tube can be made more accurate, thereby improving the sensitivity of temperature control.
[0018] In this embodiment, a mirror current source is further provided between the transconductance amplifier OTA102 and the resistor R. The mirror current source includes a 1:K mirror current source 105 and a 1:M mirror current source 106. The drain of I1 in the 1:K mirror current source 105 is connected to the output end of the transconductance amplifier OTA102, the drain of I1 is also connected to the gate of I1 and the gate of I2 in the 1:K mirror current source 106, the source of I1 is connected to the source of I2, the drain of I2 is connected to the source of I3 in the 1:M mirror current source 105, the source of I3 is also connected to the gate of I3 and the gate of I4 in the 1:M mirror current source 106, the drain of I3 is connected to the drain of I4, the source of I4 is connected to one end of the resistor R, and the connection point between the source of I1 and the source of I2 is also connected to the emitter of the bipolar transistor BJT101.
[0019] The advantage of this setting is that the output signal of the bipolar transistor BJT101 can be further amplified by using the 1:K and 1:M two-stage mirror current sources, further improving the accuracy of the signal Toffmin that controls the power tube turn-off time, further improving the sensitivity of temperature control, and can also enhance the stability of the entire circuit by connecting the emitter of the bipolar transistor BJT101 to the mirror current source.
[0020] In this embodiment, the source of the field effect transistor MOS104, the other end of the capacitor C, and the other end of the resistor R are all grounded, and the capacitor C is a surface mount ceramic capacitor.
[0021] The whole working process of the present invention is described below.
[0022] 1): When the operating temperature of the chip does not reach the temperature set by the over-temperature protection point, the emitter voltage V BE With negative temperature characteristics, voltage V BE There is no change, the output current of the transconductance amplifier OTA remains unchanged, and the output current after the 1:K and 1:M two-stage mirror current sources also remains unchanged, that is, the voltage signal Vref connected to the error operational amplifier OP remains unchanged, and the output Toffmin of the error operational amplifier OP remains unchanged, such as Figure 2 shown.
[0023] 2): When the operating temperature of the chip exceeds the temperature set by the over-temperature protection point, due to the negative temperature characteristic, the voltage V BE The output current of the transconductance error amplifier OTA becomes larger. After further amplification by the two-stage cascade mirror current source of 1:K and 1:M, the current output by the source of I4 becomes larger and flows into the resistor R. The reference voltage Vref generated on it becomes larger. After the error amplifier OP operational amplification, the output Toffmin becomes larger and the turn-off time becomes longer, thereby reducing the switching frequency. Figure 3 As shown, a cooling effect is achieved.
[0024] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable people familiar with this technology to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of protection of the present invention.
Claims
1. An over-temperature frequency reduction protection circuit, comprising a bipolar transistor (BJT), a transconductance amplifier (OTA), an error operational amplifier (OP), a field-effect transistor (MOS), and three current sources (I0, I5, and I6); characterized in that: The base and collector of the bipolar transistor BJT are connected, and the connection point between the base and the collector is also connected to the current source I0 and the inverting input terminal of the transconductance amplifier OTA; the positive input terminal of the transconductance amplifier OTA is connected to the temperature adjustment reference voltage Vref_Treg, the output terminal of the transconductance amplifier OTA is connected to one end of the resistor R, and the connection point between the transconductance amplifier OTA and the resistor R is also connected to the current source I5 and the inverting input terminal of the error operational amplifier OP; the positive input terminal of the error operational amplifier OP is connected to one end of the capacitor C, and the connection point between the error operational amplifier OP and the capacitor C is also connected to the current source I6 and the drain of the field-effect transistor MOS; the source of the field-effect transistor MOS is connected to the other end of the capacitor C and the other end of the resistor R; the gate of the field-effect transistor MOS is connected to the PWM drive control signal, and the output terminal of the error operational amplifier OP is used to output a signal Toffmin for controlling the off time of the power transistor; A mirror current source is further provided between the transconductance amplifier OTA and the resistor R. The source of the field effect transistor MOS, the other end of the capacitor C, and the other end of the resistor R are all grounded.
2. The over-temperature frequency reduction protection circuit according to claim 1, characterized in that: The mirror current source includes a 1:K mirror current source and a 1:M mirror current source. The drain of the MOS transistor I1 in the 1:K mirror current source is connected to the output end of the transconductance amplifier OTA, the drain of the MOS transistor I1 is also connected to the gate of the MOS transistor I1 and the gate of the MOS transistor I2 in the 1:K mirror current source, the source of the MOS transistor I1 is connected to the source of the MOS transistor I2, the drain of the MOS transistor I2 is connected to the source of the MOS transistor I3 in the 1:M mirror current source, the source of the MOS transistor I3 is also connected to the gate of the MOS transistor I3 and the gate of the MOS transistor I4 in the 1:M mirror current source, the drain of the MOS transistor I3 is connected to the drain of the MOS transistor I4, and the source of the MOS transistor I4 is connected to one end of the resistor R.
3. The over-temperature frequency reduction protection circuit according to claim 2, characterized in that: The connection point between the source of the MOS transistor I1 and the source of the MOS transistor I2 is also connected to the emitter of the bipolar junction transistor BJT.
4. The over-temperature frequency reduction protection circuit according to claim 1, characterized in that: The capacitor C includes a chip ceramic capacitor.
Citation Information
Patent Citations
Over-temperature frequency reduction protection circuit
CN217443794U