Method and apparatus for storing data

Abstract

A method and apparatus for storing data are provided. The method comprises: in response to a write request of a host for data, determining a write priority of the data; in response to the write priority of the data being a first write priority, writing the data to a first type of storage unit; and in response to the write priority of the data being a second write priority, writing the data to a second type of storage unit, wherein the second write priority is higher than the first write priority, and a write speed of the second type of storage unit is higher than a write speed of the first type of storage unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, and more particularly, to a method and apparatus for storing data. BACKGROUND

[0002] Recently, storage devices such as a Solid State Drive (SSD), a Non-Volatile Memory express (NVMe), an Embedded Multi Media Card (eMMC), a Universal flash memory (UFS), etc. have been widely used. For example, the storage devices can be used in various types of devices such as a Personal Computer (PC), a server device, a mobile device, an embedded device, etc.

[0003] Based on the consideration of storage capacity and cost, many storage devices use storage cells of multiple processes (e.g., Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), Quad-Level Cell (QLC), etc.).

[0004] In a conventional storage device using storage cells of multiple processes, generally, the storage cells of one process are used to store data for a certain period of time, and the storage cells of another process are used to store data for another period of time. The above-described method of storing data selectively uses storage cells of different processes to store data according to time periods, and thus, it is difficult to improve the performance and / or user experience of the storage device. SUMMARY

[0005] The present application relates to the field of storage, and more particularly, to a method and apparatus for storing data.

[0006] According to an aspect of the present disclosure, there is provided a method of storing data, the method including determining a write priority of data in response to a write request of the data from a host, writing the data to a first type of storage cell in response to the write priority of the data being a first write priority, and writing the data to a second type of storage cell in response to the write priority of the data being a second write priority, wherein the second write priority is higher than the first write priority, and a write speed of the second type of storage cell is higher than a write speed of the first type of storage cell.

[0007] Optionally, the step of determining the write priority of the data comprises: obtaining a first data feature of the data, wherein the first data feature comprises a file type and a synchronous write proportion; and determining the write priority of the data based on the first data feature of the data.

[0008] Optionally, the first data feature of the data further comprises one or more of the following features: time attribute information, a file system type, a synchronization identifier of a database file, a data synchronization identifier, a master device number, a slave device number, a logical block address sector number, a write data size, and a process priority.

[0009] Optionally, the step of determining the write priority of the data based on the first data feature of the data comprises: determining an application to which the data belongs based on the first data feature of the data; and determining the write priority of the data based on the determined application.

[0010] Optionally, the step of determining the application to which the data belongs comprises: determining the application to which the data belongs by using an application recognition model based on the first data feature of the data, wherein the application recognition model is a pre-trained prediction model.

[0011] Optionally, the step of determining the write priority of the data based on the determined application comprises: obtaining a second data feature of the data based on the application to which the data belongs; and determining the write priority of the data based on the second data feature of the data and a preset write strategy of the application, wherein the preset write strategy of the application comprises a correspondence between the second data feature of the data of the application and at least one write priority, and the at least one write priority comprises a first write priority and a second write priority.

[0012] Optionally, the method is executed when a write booster function is enabled.

[0013] According to an aspect of the present disclosure, a device for storing data is provided, which comprises: a priority determination module configured to determine a write priority of the data in response to a write request of the data from a host; and a write module configured to: write the data to a first type of storage unit in response to the write priority of the data being a first write priority; and write the data to a second type of storage unit in response to the write priority of the data being a second write priority, wherein the second write priority is higher than the first write priority, and a write speed of the second type of storage unit is higher than a write speed of the first type of storage unit.

[0014] Optionally, the priority determination module comprises an obtaining unit and a determination unit, wherein the obtaining unit is configured to obtain a first data feature of the data, wherein the first data feature comprises a file type and a synchronous write proportion, and the determination unit is configured to determine the write priority of the data based on the first data feature of the data.

[0015] Optionally, the first data feature of the data further comprises one or more of the following features: time attribute information, a file system type, a synchronous identifier of a database file, a data synchronization identifier, a master device number, a slave device number, a logical block address sector number, a write data size, and a process priority.

[0016] Optionally, the determination unit is configured to determine an application to which the data belongs based on the first data feature of the data, and determine the write priority of the data based on the determined application.

[0017] Optionally, the determination unit is configured to determine the application to which the data belongs by using an application recognition model based on the first data feature of the data, wherein the application recognition model is a pre-trained prediction model.

[0018] Optionally, the determination unit is configured to obtain a second data feature of the data based on the application to which the data belongs, and determine the write priority of the data based on the second data feature of the data and a preset write strategy of the application, wherein the preset write strategy of the application comprises a correspondence between the second data feature of the data of the application and at least one write priority, and the plurality of write priorities comprises a first write priority and a second write priority.

[0019] Optionally, the priority determination module is configured to determine the write priority of the data in response to a write request of the data from a host when a write booster function is enabled.

[0020] According to an aspect of the present disclosure, there is provided a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, any method as described above is implemented.

[0021] According to an aspect of the present disclosure, there is provided an electronic system, comprising: a storage device comprising a first type of storage unit and a second type of storage unit; and a host processor configured to control the storage device to store data according to any method as described above.

[0022] According to an aspect of the present disclosure, a host storage system is provided, the host storage system comprising: a host; a storage device comprising a first type of storage unit and a second type of storage unit, wherein the host is configured to control the storage device to store data according to any of the methods described above.

[0023] According to an aspect of the present disclosure, a storage device is provided, the storage system comprising: a first type of storage unit and a second type of storage unit; a memory controller configured to control the storage device to store data according to any of the methods described above.

[0024] According to an aspect of the present disclosure, a universal flash storage (UFS) system is provided, the UFS system comprising: a UFS host; a UFS interface; a UFS unit comprising a first type of storage unit and a second type of storage unit, and configured to communicate with the UFS host via the UFS interface, wherein the UFS host is configured to control the UFS unit to store data according to any of the methods described above.

[0025] According to an aspect of the present disclosure, a data center is provided, the data center comprising: an application server; a storage server comprising a first type of storage unit and a second type of storage unit, and configured to communicate with the application server through a network, wherein the application server or the storage server is configured to store data according to any of the methods described above.

[0026] The method for storing data according to the example embodiments of the present disclosure can store data in a storage unit (e.g., a first type of storage unit or a second type of storage unit) corresponding to the write priority of the data according to the write priority of the data, and thus can improve the performance and / or user experience of a storage device using multiple types of storage units.

[0027] The method for storing data according to the example embodiments of the present disclosure can store data in a storage unit (e.g., a first type of storage unit or a second type of storage unit) corresponding to the write priority of the data according to the write priority of the data determined based on the first data characteristic of the data, and thus can employ different write strategies (e.g., write data requiring fast writing to a second type of storage unit having high writing speed, and write data not requiring fast writing to a first type of storage unit having low writing speed) according to different data, thereby achieving maximum utilization of the first type of storage unit and the second type of storage unit and improving writing performance.

[0028] The method of storing data according to an example embodiment of the present application can determine a write priority of data as a high write priority (e.g., a second write priority) and write the data to a second type of storage unit having a high write speed when an application to which the data belongs is an application requiring fast data write, and can determine the write priority of the data as a low write priority (e.g., a first write priority) and write the data to a first type of storage unit having a low write speed when the application to which the data belongs is an application not requiring fast data write, and thus, can more reasonably use the first type of storage unit and the second type of storage unit based on the application to which the data belongs.

[0029] The method of storing data according to an example embodiment of the present application can identify an application to which data belongs through a pre-trained application identification model, and thus, can accurately identify the application to which the data belongs.

[0030] The method of storing data according to an example embodiment of the present application can perform a write of data based on an optimal preset write strategy among a plurality of write strategies obtained through iterative testing, and thus, can improve performance of a storage device.

[0031] The method of storing data according to an example embodiment of the present application can further determine a write priority of data using a second data characteristic with respect to different applications, and thus, can optimize use of a first type of storage unit and a second type of storage unit, improve write performance, and improve lifespan.

[0032] The method of storing data according to an example embodiment of the present application can store data in a storage unit corresponding to a write priority of data according to the write priority of the data, rather than writing all of the data to a second type of storage unit (e.g., SLC) when a write booster function is turned on, and thus, can reduce an amount of data written to the second type of storage unit, thereby extending lifespan of the second type of storage unit and improving write performance. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other objects and features of the present application will become clearer from the following description of an example, given freely in conjunction with the accompanying drawings, wherein:

[0034] Figure 1 is a flowchart illustrating a method of storing data according to an example embodiment of the present application;

[0035] Figure 2 is a flowchart illustrating a method of determining a write priority of data based on a first data characteristic of the data according to an example embodiment of the present application;

[0036] Figure 3a flowchart illustrating a method of determining a write priority of application-determined data according to an example embodiment of the present application;

[0037] Figure 4 is a flowchart illustrating a method of storing data according to an example embodiment of the present application;

[0038] Figure 5 is a flowchart illustrating a Write Booster function according to the prior art;

[0039] Figure 6 is a block diagram of an apparatus for storing data according to an example embodiment of the present application;

[0040] Figure 7 is a schematic diagram of a system to which a storage apparatus is applied according to an embodiment;

[0041] Figure 8 is a block diagram of a host storage system according to an example embodiment;

[0042] Figure 9 is a block diagram of a storage system according to an embodiment of the present application;

[0043] Figure 10 is a block diagram of a UFS system according to an embodiment;

[0044] Figure 11 is a block diagram of a storage system according to an embodiment of the present application;

[0045] Figure 12 is a block diagram of a data center to which a storage apparatus is applied according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following detailed description is provided to aid in understanding the method, apparatus and / or system described herein. However, various changes, modifications and equivalents can be resorted to without departing from the disclosure disclosed herein. For example, the order in which the operations are described is merely an example and the operations can be changed, modified and / or augmented as will be apparent to those skilled in the art, except that some operations must occur before others, as will be clear from the disclosure. Furthermore, features known to those skilled in the art can be omitted in the interest of increased clarity and brevity.

[0047] The features described herein can be implemented in different forms and should not be construed as limited to the examples described herein. Rather, these examples have been provided so that this disclosure will be thorough and complete, and will fully convey the scope of the methods, apparatus and / or systems described herein to those skilled in the art. The examples described herein have been chosen for the purposes of illustration and explanation only, and are not intended to be limiting.

[0048] Throughout the specification, where assemblies are described as "connected" or "coupled" to another assembly, it can be directly "connected" or "coupled" to the other assembly, or one or more other assemblies can be interposed therebetween. On the contrary, where an element is described as being "directly connected" or "directly coupled" to another element, it can be directly connected or coupled to the other element without other elements interposed therebetween. Likewise, similar expressions, such as "between" and "immediately between," and "adjacent" and "immediately adjacent," should be interpreted in the same manner. As used herein, the term "and / or" includes any one of the referenced items or any combination of two or more of the referenced items.

[0049] Although terms such as "first", "second", and "third" can be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section referred to in the examples described herein can also be referred to as a second element, component, region, layer or section without departing from the teachings of the examples.

[0050] The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the disclosure. As used herein, singular forms are intended to include the plural forms as well unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has", "having" as used herein, specify the presence of stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the disclosure to which the disclosure belongs. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. The use of the term "may" (e.g., with respect to examples or embodiments can include or implement what) with respect to examples or embodiments herein indicates that at least one example or embodiment includes or implements the feature, and all examples are not limited to this.

[0052] Based on the storage capacity and cost considerations, many storage devices use multiple processes, such as at least two of Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), and Quad-Level Cell (QLC). Different process storage units have different storage performance, such as speed, and the balance between storage capacity cost and storage performance is a problem to be solved. Based on this, the present disclosure proposes a method for storing data, which will be described in detail below with reference to the accompanying drawings.

[0053] Figure 1 is a flowchart showing a method for storing data according to an example embodiment of the present application.

[0054] Referring to Figure 1 In step S110, in response to a write request of the host to the data, the write priority of the data is determined.

[0055] The write priority of the data can indicate the speed at which the data is expected to be written. For example, the write speed of data with a high write priority can be higher than the write speed of data with a low write priority.

[0056] In one embodiment, a first data feature of the data can be obtained, and the write priority of the data is determined based on the first data feature of the data. The first data feature can include a file type and a synchronous write proportion.

[0057] The file type can indicate the format and / or category of the data. In one example, the file type of the data can include a video file, a voice file, an image file, a text file, etc. However, the above examples are only examples, and the file type of the data of the present application is not limited thereto and can be one or more other file types related to the data.

[0058] In one example, the synchronous write proportion can be a synchronous write proportion in a single period. For example, the synchronous write proportion can include an fsync proportion. However, the synchronous write proportion of the present application is not limited thereto and can be a synchronous write proportion defined in any other way.

[0059] Optionally, the first data characteristic of the data can further include one or more of the following characteristics: time attribute information, file system type, synchronization identifier of a database file, data synchronization identifier, master device number, slave device number, logical block address sector number, write data size, process priority. However, the first data characteristic of the data of the present application is not limited to the above examples, and can also be one or more other characteristics related to the characteristics (e.g., writing or storage) of the data. For example, by way of example only, the first data characteristic of the data can include at least one of cold and hot data proportion, input and output size, and data size.

[0060] By way of example, the first data characteristic of the data can be obtained based on a write request of the host to the data. In one example, the first data characteristic of the data can be obtained by analyzing the write request of the host to the data or IO data. However, the manner of obtaining the first data characteristic of the data of the present application is not limited thereto and can be any other manner of obtaining known.

[0061] In operation S120, in response to the write priority of the data being the first write priority, the data is written to the first type storage unit; and in response to the write priority of the data being the second write priority, the data is written to the second type storage unit.

[0062] Here, the second write priority can be higher than the first write priority, and the write speed of the second type storage unit can be higher than the write speed of the first type storage unit. In one example, the first type storage unit and the second type storage unit can be two of SLC, MLC, TLC, and QLC. However, the present disclosure is not limited to the above examples.

[0063] According to the method of storing data of the present application, the data can be stored in a storage unit (e.g., a first type storage unit or a second type storage unit) corresponding to the write priority of the data according to the write priority of the data, and thus the performance and / or user experience of a storage device using multiple types of storage units can be improved.

[0064] In addition, according to the method of storing data of the present application, the data can be stored in a storage unit (e.g., a first type storage unit or a second type storage unit) corresponding to the write priority of the data according to the write priority of the data determined based on the first data characteristic of the data, and thus different write strategies (e.g., writing data requiring fast writing to a second type storage unit having a high write speed and writing data not requiring fast writing to a first type storage unit having a low write speed) can be employed according to different data, thereby achieving maximum utilization of the first type storage unit and the second type storage unit and improving write performance.

[0065] Figure 2A flow chart of a method of determining a write priority of data based on a first data feature of the data according to an example embodiment of the present application is shown.

[0066] Referring to Figure 2 In operation S210, an application to which the data belongs can be determined based on a first data feature of the data.

[0067] The application to which the data belongs can represent an application that uses the data, will use the data, or generates the data. The description of the first data feature is referred to the description of the example of Figure 1 and will not be repeated here.

[0068] Generally, data generated and / or used by different applications can have different data features (e.g., the first data feature). Therefore, it is feasible to determine the application to which the data belongs based on the first data feature of the data.

[0069] In one embodiment, the application to which the data belongs can be determined based on the first data feature of the data by using an application identification model, wherein the application identification model is a pre-trained prediction model. For example, the application identification model can be pre-trained to output an application corresponding to input data based on a data feature (e.g., the first data feature) of the input data. According to an example embodiment of the present application, the application to which the data belongs is identified by the pre-trained application identification model, and thus the application to which the data belongs can be accurately identified.

[0070] By way of example only, the application identification model can be obtained by offline data collection, data feature selection, and model training.

[0071] In offline data collection, tracking information (i.e., information corresponding to the first data feature) under different applications can be collected according to a collection period (by way of example only, 1 minute or 5 minutes), and the tracking information under different applications can be labeled according to the collection period.

[0072] In data feature selection, data under different applications can be processed, and feature engineering can be used to analyze feature relationships under different applications according to the labeled tracking information, and main features can be selected for application classification. In one example, when distinguishing between a first application and a second application, two features such as a synchronous write proportion within one period and a hot and cold frequency can be selected. However, the present application is not limited to selecting the two features of the synchronous write proportion within one period and the hot and cold frequency as features for determining the application. For example, any other first data feature can be selected to identify the application. Alternatively, more features can be selected when distinguishing between more applications.

[0073] In the model training, an application classification model based on machine learning (ML) can be built, data is processed according to the selected first data features (for example, only removing useless data, calculation, etc.), the parameters of the application recognition model are iteratively adjusted until the error converges, and the model recognition accuracy is analyzed using test data, so as to determine the final application recognition model.

[0074] In operation S220, the write priority of the data is determined based on the determined application.

[0075] In one embodiment, when the application to which the data belongs is an application that requires fast writing of data, the write priority of the data is determined as a high write priority (for example, a second write priority) and the data is written to a second type of storage unit with a high write speed; when the application to which the data belongs is an application that does not require fast writing of data, the write priority of the data is determined as a low write priority (for example, a first write priority) and the data is written to a first type of storage unit with a low write speed. Therefore, in this embodiment, distinguishing the application to which the data belongs can more reasonably use the first type of storage unit and the second type of storage unit.

[0076] That is, according to example embodiments of the present application, the type of storage unit to which data from the first application is written and the type of storage unit to which data from the second application is written can be different.

[0077] Optionally, according to example embodiments of the present application, when the same data is input under the first application and under the second application different from the first application, the result of writing data from the first application and the result of writing data from the second application can be different from each other. For example, the ratio between the amount of data in the data from the first application that is written to the first type of storage unit (for example, the storage unit corresponding to low-speed NAND) and the amount of data in the data from the first application that is written to the second type of storage unit (for example, the storage unit corresponding to high-speed NAND) can be different from the ratio between the amount of data in the data from the second application that is written to the first type of storage unit and the amount of data in the data from the second application that is written to the second type of storage unit.

[0078] Step S220 will be described more specifically later in connection with Figure 3

[0079] Figure 3 A flowchart showing a method of determining the write priority of data based on the determined application according to example embodiments of the present application is shown.

[0080] Referring to Figure 3 In operation S310, the second data features of the data are obtained based on the application to which the data belongs.

[0081] ​The second data characteristic of the data can be data related to a write strategy of the data. For example, the second data characteristic of the data can include one or more of the following characteristics: file type, synchronous write proportion time attribute information, file system type, synchronization identifier of a database file, data synchronization identifier, master device number, slave device number, logical block address sector number, write data size, process priority, cold and hot data proportion, input and output size, and data size. However, the second data characteristic of the data of the present disclosure is not limited to the above examples, and can be one or more other characteristics related to the writing of the data.

[0082] In operation S320, a write priority of the data is determined based on the second data characteristic of the data and a preset write strategy of an application to which the data belongs. The preset write strategy of the application can include a correspondence relationship between the second data characteristic of the data of the application and at least one write priority, and the plurality of write priorities include a first write priority and a second write priority.

[0083] For example, the write priority corresponding to the first value of the second data characteristic under the preset write strategy of the first application can be the same as or different from the write priority corresponding to the second value of the second data characteristic under the preset write strategy of the first application. For another example, the write priority of the data can be determined based on the second data characteristic of the data through a lookup table corresponding to the preset write strategy, which is established in advance.

[0084] In one embodiment, the preset write strategy can be obtained through iterative testing.

[0085] More specifically, a plurality of write strategies can be made for the second data characteristic before the iterative testing. Thereafter, the write strategy having the best write performance among the plurality of write strategies can be determined as the preset write strategy through the iterative testing.

[0086] In one example, assuming that the second data feature includes a first sub-data feature and a second sub-data feature, the first sub-data feature can have a first value or a second value, and the second sub-data feature can have a third value or a fourth value. In this example, formulating a plurality of write strategies can include, but is not limited to, at least one of the following strategies: (1) a first strategy: write data corresponding to the first sub-data feature with the first value and the second sub-data feature with the third value to the second type storage unit, and write the remaining data to the first type storage unit; (2) a second strategy: write data corresponding to the first sub-data feature with the second value and the second sub-data feature with the third value to the second type storage unit, and write the remaining data to the first type storage unit. Thereafter, the write performance under the first strategy and the write performance under the second strategy can be tested through iterative testing, so as to determine the strategy with better write performance from among the first strategy and the second strategy as the preset write strategy. For example, better write performance can indicate that the second type storage unit has a longer lifespan. The above example is only shown for ease of understanding, and the present disclosure is not limited thereto.

[0087] That is, the writing of data can be performed based on the optimal preset write strategy from among the plurality of write strategies obtained through iterative testing, and thus the performance of the storage device can be improved. For example, the lifespan of the second type storage unit under the preset write strategy can be higher than the lifespan of the second type storage unit under other write strategies.

[0088] For example, the iterative testing can be testing of several write strategies for a single application. In one example, for a single application, the features of the data of the application (i.e., the second data feature, such as, for example only, the proportion of input / output size (IO size), the proportion of synchronization (sync)) can be analyzed, and then several write strategies can be formulated for iterative verification. The iterative testing will be described below in conjunction with examples, but the iterative testing of the present disclosure is not limited to the description of the examples below. For example, the first strategy, the second strategy, and the features of the data used (e.g., input / output size and synchronization) in the examples below are exemplary, and the present disclosure is not limited thereto.

[0089] For example, in the iterative testing, when the primary weight is input / output size and the secondary weight is synchronization, the proportion of a predetermined size (e.g., 4 KB for example only) in the input / output size is the highest, and then the strategy includes, but is not limited to, the following first strategy: data with an input / output size of 4 KB and containing a synchronization identifier is written to the second type storage unit (e.g., a storage unit corresponding to a high-speed SLC NAND area), and the remaining data is written to the first type storage unit (e.g., a storage unit corresponding to a low-speed NAND area).

[0090] For example, in the iterative test, when the primary weight is synchronization and the secondary weight is input / output size, the strategy includes, but is not limited to, the following second strategy: data with a synchronization identifier and an input / output size of a predetermined size (for example, 4 KB as an example) is written to a second type of storage unit (for example, a storage unit corresponding to a high-speed SLC NAND area), and the rest of the data is written to a first type of storage unit (for example, a storage unit corresponding to a low-speed NAND area).

[0091] After each strategy (for example, the first strategy and the second strategy) is tested for a certain number of times, one of the first strategy and the second strategy can be determined as the preset write strategy for the application according to the performance (for example, the average performance) of the storage device under each strategy. The preset write strategy can finally send information about whether the data is to be written to the second type of storage unit to the storage device through an interface provided by the storage device (for example, a UFS device). In one example, the iterative test can be a dynamic test.

[0092] That is, according to the method of storing data according to the present application, the write priority of the data can be determined based on the application to which the data belongs and the second data feature. Therefore, in this embodiment, the first type of storage unit and the second type of storage unit can be more reasonably used according to the write priority of the data based on the application to which the data belongs and the second data feature. More specifically, even when the application to which the data belongs is the same, the data under the same application can have different requirements for the write speed. Therefore, using the second data feature for different applications to further determine the write priority of the data can optimize the use of the first type of storage unit and the second type of storage unit, thereby improving the write performance and the lifespan.

[0093] Figure 4 is a flowchart showing a method of storing data according to an example embodiment of the present application.

[0094] Referring to Figure 4 In operation S410, one or more data features of the data can be input to the application recognition model. The application recognition model can be pre-trained to output the application corresponding to the input data based on the data features of the input data.

[0095] However, since there are many types of applications, and the data used to train the application recognition model cannot possibly include data of all applications, the application recognition model can be trained to recognize a target application corresponding to the training data. For example, the application recognition model can be trained to recognize a first application and a second application. In this case, when the application recognition model is used to recognize data of a third application and data of a fourth application, the application recognition model can recognize the third application and the fourth application as other applications different from the target applications (for example, the first application and the second application).

[0096] In operation S420, whether the identified application is other application different from the target application can be determined based on the application identification model. More specifically, the application to which the data belongs can be identified based on the application identification model, and whether the application to which the data belongs is other application different from the target application can be determined.

[0097] When it is determined in operation S420 that the application to which the data belongs is other application, the data can be stored in a first type storage unit corresponding to the first write priority in operation S450. In Figure 4 In an example, the first type storage unit can be one or more of MLC, TLC, and QLC.

[0098] When it is determined in operation S420 that the application to which the data belongs is not other application (i.e., the application to which the data belongs is the target application), whether the preset write strategy of the application indicates fast write can be determined based on at least one data characteristic of the data in operation S430. The preset write strategy of the application can indicate a write strategy corresponding to different values of the data characteristic. For example, the preset write strategy can include writing the data to a first type storage unit corresponding to the first write priority or writing the data to a second type storage unit corresponding to the second write priority according to the value of the data characteristic.

[0099] When it is determined in operation S430 that the preset write strategy of the application does not indicate fast write, the data can be stored in the first type storage unit corresponding to the first write priority in operation S440.

[0100] When it is determined in operation S430 that the preset write strategy of the application indicates fast write, the data can be stored in the second type storage unit corresponding to the second write priority in operation S450. In Figure 4 In an example, the second type storage unit can be SLC.

[0101] Although in the example of Figure 4 In an example, the first type storage unit can be one or more of MLC, TLC, and QLC, and the second type storage unit can be SLC, but the present disclosure is not limited to the above-described example. For example, the first type storage unit and the second type storage unit can be two of SLC, MLC, TLC, and QLC, and the write speed of the second type storage unit can be higher than that of the first type storage unit.

[0102] Figure 5 is a flowchart illustrating a Write Booster function according to the related art.

[0103] Write booster is an important technology for storage devices (e.g., universal flash storage (UFS) (e.g., NAND flash)). When the write booster function is turned on, data from a host is written in SLC to improve write speed. However, the capacity of SLC is limited, and after that, the data in SLC is written to TLC / MLC or QLC, etc. low-speed NAND flash. Therefore, the write booster plays a crucial role in write requests from the host with high latency requirements.

[0104] When the write booster function is turned on, all data from the host is written to SLC without distinguishing the data when the capacity of SLC is fixed, and the amount of data written to SLC is greatly increased, resulting in reduced write performance, rapid depletion of the life of SLC, and poor user experience.

[0105] More specifically, the existing write booster can write data to SLC in three ways: 1. When the WriteBooster switch is turned on, all data is written to SLC; 2. When the Write Booster is turned on in time periods, all data in the on period is written to SLC; 3. When the data amount is large, all data is written to SLC. When the continuously written data is greater than the size of the SLC space, the data needs to be written to the storage space other than SLC, and at this time, the continuous write speed becomes the write speed of the real TLC / QLC NAND, and a fault-like drop occurs, thereby reducing the use experience.

[0106] As described above with reference to any one of Figures 1 to 5 According to the data storage method of the example embodiment of the present application, data can be stored in a storage unit (e.g., a first type storage unit or a second type storage unit) corresponding to the write priority of the data according to the write priority of the data.

[0107] In the case where the write booster function is turned on, data can be stored in a storage unit corresponding to the write priority of the data according to the write priority of the data, instead of writing all data to a second type storage unit (e.g., SLC), and thus, the amount of data written to the second type storage unit can be reduced, thereby prolonging the life of the second type storage unit and improving the write performance.

[0108] Figure 6 is a block diagram illustrating a data storage device according to an example embodiment of the present application.

[0109] Referring to Figure 6 The data storage device 600 according to the example embodiment of the present application can include a priority determination module 610 and a write module 620.

[0110] The priority determination module 610 can determine a write priority of data in response to a write request of the host for the data. For example, the priority determination module 610 can determine the write priority of the data with reference to at least one of the methods described in Figures 1 to 4

[0111] In one example, the priority determination module 610 can include an acquisition unit (not shown) and a determination unit (not shown). The determination unit can determine the priority of the data with reference to at least one of the methods described in Figures 1 to 4

[0112] The write module 620 can write the data to the first type storage unit in response to the write priority of the data being the first write priority. In addition, the write module 620 can write the data to the second type storage unit in response to the write priority of the data being the second write priority. The second write priority can be higher than the first write priority, and the write speed of the second type storage unit can be higher than the write speed of the first type storage unit. That is, the write module 620 can perform the writing of the data. For example, the write module 620 can perform the writing of the data with reference to at least one of the methods described in Figures 1 to 4

[0113] Figure 7 A schematic diagram of a system 1000 to which a storage device according to an embodiment is applied. Figure 7 The system 1000 (e.g., an electronic system) of FIG. 1 can be substantially a mobile system such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, the system 1000 of FIG. 1 is not necessarily limited to a mobile system, and can be a PC, a laptop computer, a server, a media player, or a car device (e.g., a navigation device). Figure 7 With reference to FIG. 1,

[0114] The system 1000 can include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b) with reference to FIG. 1. Also, the system 1000 can include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480. Figure 7

[0115] ​​​​In some embodiments, the memory (e.g., 1200a and 1200b) and / or the storage (e.g., 1300a and 1300b) can correspond to a storage or a device for storing data according to example embodiments of the present application. For example, the memory (e.g., 1200a and 1200b) and / or the storage (e.g., 1300a and 1300b) can store data in a method of storing data described with reference to at least one of FIGS. 1 to 3. Figures 1 to 5

[0116] The main processor 1100 can control all operations of the system 1000, and more particularly, can control operations of other components included in the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor, etc.

[0117] The main processor 1100 can include at least one central processing unit (CPU) core 1110, and further include a controller 1120 for controlling the memory 1200a and 1200b and / or the storage 1300a and 1300b. In some embodiments, the main processor 1100 can further include an accelerator 1130, which is a special-purpose circuit for high-speed data operations such as artificial intelligence (AI) data operations, etc. The accelerator 1130 can include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and is implemented as a chip physically separated from other components of the main processor 1100.

[0118] The memory 1200a and 1200b can serve as a main storage of the system 1000. Although the memory 1200a and 1200b can each include a volatile memory such as a static random access memory (SRAM) and / or a dynamic random access memory (DRAM), etc., the memory 1200a and 1200b can each include a non-volatile memory such as a flash memory, a phase change random access memory (PRAM), and / or a resistive random access memory (RRAM), etc. The memory 1200a and 1200b can be implemented in the same package as the main processor 1100.

[0119] ​The storage 1300a and 1300b can function as non-volatile storage configured to store data regardless of whether power is supplied, and have a larger storage capacity than the memories 1200a and 1200b. The storage 1300a and 1300b can include memory controllers (STRG CTRL) 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b, respectively, configured to store data via control of the memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b can include V-NAND flash memories having a two-dimensional (2D) or three-dimensional (3D) structure, the NVMs 1320a and 1320b can include other types of NVMs, such as PRAM and / or RRAM, etc.

[0120] The storage 1300a and 1300b can be physically separated from the main processor 1100 and included in the system 1000, or can be implemented in the same package as the main processor 1100. In addition, the storage 1300a and 1300b can have a type of a solid state device (SSD) or a memory card, and can be removably combined with other components of the system 1000 through an interface such as the connection interface 1480 to be described later. The storage 1300a and 1300b can be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or NVMe is applied, but are not limited thereto.

[0121] The image capture device 1410 can photograph still images or moving images. The image capture device 1410 can include a camera, a camcorder, and / or a web camera, etc.

[0122] The user input device 1420 can receive various types of data input by a user of the system 1000, and includes a touchpad, a keypad, a keyboard, a mouse, and a microphone, etc.

[0123] The sensor 1430 can detect various types of physical quantities that can be obtained from the outside of the system 1000, and convert the detected physical quantities into electrical signals. The sensor 1430 can include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biological sensor, and / or a gyroscope sensor, etc.

[0124] The communication device 1440 can transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 can include an antenna, a transceiver, or a modem, etc.

[0125] The display 1450 and the speaker 1460 can function as output devices configured to output visual information and auditory information, respectively, to a user of the system 1000.

[0126] The power supply 1470 can appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0127] The connection interface 1480 can provide a connection between the system 1000 and an external device that is connected to the system 1000 and capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 can be implemented by using various interface schemes, for example, an advanced technology attachment (ATA), a serial ATA (SATA), an external serial ATA (e-SATA), a small computer system interface (SCSI), a serial SCSI (SAS), a peripheral component interconnect (PCI), a PCI express (PCIe), an NVMe, an IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multimedia card (MMC) interface, an embedded multimedia card (eMMC) interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface, etc.

[0128] Figure 8 is a block diagram of a host storage system 8000 according to an exemplary embodiment.

[0129] The host storage system 8000 can include a host 8100 and a storage device 8200. Also, the storage device 8200 can include a memory controller 8210 and an NVM 8220. According to an exemplary embodiment of the present application, the host 8100 can include a host controller 8110 and a host memory 8120. The host memory 8120 can be used as a buffer memory configured to temporarily store data to be transmitted to the storage device 8200 or data received from the storage device 8200.

[0130] In some embodiments, the host 8100 and / or the storage device 8200 can correspond to a device for storing data according to an exemplary embodiment of the present application. For example, the storage device 8200 can include a first type of storage unit and a second type of storage unit.

[0131] The storage device 8200 can include a storage medium configured to store data in response to a request from the host 8100. As an example, the storage device 8200 can include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 8200 is an SSD, the storage device 8200 can be a device conforming to an NVMe standard. When the storage device 8200 is an embedded memory or an external memory, the storage device 8200 can be a device conforming to a UFS standard or an eMMC standard. The host 8100 and the storage device 8200 can each generate and transmit a packet according to a standard protocol adopted.

[0132] When the NVM 8220 of the storage device 8200 includes a flash memory, the flash memory can include a 2D NAND storage array or a 3D (or vertical) NAND (VNAND) storage array. As another example, the storage device 8200 can include various other kinds of NVMs. For example, the storage device 8200 can include a magnetic random access memory (MRAM), a spin-transfer torque MRAM, a conductive-bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and various other types of memory.

[0133] According to an embodiment, the host controller 8110 and the host memory 8120 can be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 8110 and the host memory 8120 can be integrated in the same semiconductor chip. As an example, the host controller 8110 can be any one of a plurality of modules included in an application processor (AP). The AP can be implemented as a system on chip (SoC). Further, the host memory 8120 can be an embedded memory included in the AP or a memory module external to the AP.

[0134] The host controller 8110 can manage an operation of storing data (e.g., write data) of a buffer region of the host memory 8120 in the NVM 8220 or an operation of storing data (e.g., read data) of the NVM 8220 in the buffer region.

[0135] The memory controller 8210 can include a host interface 8211, a memory interface 8212, and a CPU 8213. In addition, the memory controller 8210 can further include a flash translation layer (FTL) 8124, a packet manager 8215, a buffer memory 8216, an error correction code (ECC) engine 8217, and an advanced encryption standard (AES) engine 8218. The memory controller 8210 can further include a working memory (not shown) in which the FTL 8124 is loaded. The CPU 8213 can execute the FTL 8124 to control data write and read operations on the NVM 8220.

[0136] The host interface 8211 can transmit and receive a packet to and from the host 8100. The packet transmitted from the host 8100 to the host interface 8211 can include a command or data to be written to the NVM 8220, etc. The packet transmitted from the host interface 8211 to the host 8100 can include a response to the command or data read from the NVM 8220, etc. The memory interface 8212 can transmit data to be written to the NVM 8220 to the NVM 8220 or receive data read from the NVM 8220. The memory interface 8212 can be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0137] The FTL 8124 can perform various functions such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation can be an operation of converting a logical address received from the host 8100 to a physical address used to actually store data in the NVM 8220. The wear leveling operation can be a technique of preventing over-degradation of a specific block by allowing uniform use of blocks of the NVM 8220. As an example, the wear leveling operation can be implemented by a firmware technique of balancing erase counts of physical blocks. The garbage collection operation can be a technique of securing available capacity in the NVM 8220 by erasing an existing block after copying valid data of the existing block to a new block.

[0138] The packet manager 8215 can generate a packet according to a protocol of an interface of the host 8100, or parse various types of information from a packet received from the host 8100. In addition, the buffer memory 8216 can temporarily store data to be written to the NVM 8220 or data to be read from the NVM 8220. Although the buffer memory 8216 can be a component included in the memory controller 8210, the buffer memory 8216 can be external to the memory controller 8210.

[0139] The ECC engine 8217 can perform an error detection and correction operation on read data read from the NVM 8220. More specifically, the ECC engine 8217 can generate parity bits for write data to be written to the NVM 8220, and the generated parity bits can be stored in the NVM 8220 together with the write data. During reading of data from the NVM 8220, the ECC engine 8217 can correct errors in read data by using the read data and the parity bits read from the NVM 8220, and output the read data error-corrected.

[0140] The AES engine 8218 can perform at least one of an encryption operation and a decryption operation on data input to the memory controller 8210 by using a symmetric key algorithm.

[0141] Figure 9 A block diagram of a storage system 9000 according to an embodiment of the present application.

[0142] Referring to Figure 9 The storage system 9000 can include a storage device 9200 and a memory controller 9100. The storage system 9000 can support a plurality of channels CH1 to CHm, and the storage device 9200 can be connected to the memory controller 9100 through the plurality of channels CH1 to CHm. For example, the storage system 9000 can be implemented as a storage device such as an SSD.

[0143] In some embodiments, the storage system 9000 can correspond to a device for storing data according to an example embodiment of the present application. For example, the storage device 9200 can include first type storage units and second type storage units, and the memory controller 9100 can store data according to a method of storing data described in at least one of Referring to Figures 1 to 5

[0144] The storage device 9200 can include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm through a way corresponding thereto. For example, the NVM devices NVM11 to NVM1n can be connected to the first channel CH1 through ways W11 to W1n, and the NVM devices NVM21 to NVM2n can be connected to the second channel CH2 through ways W21 to W2n. In an exemplary embodiment, each of the NVM devices NVM11 to NVM1n can be implemented as an arbitrary storage element which can be operated according to a separate command from the memory controller 9100. For example, each of the NVM devices NVM11 to NVM1n can be implemented as a chip or a die, but the present application is not limited thereto.

[0145] The memory controller 9100 can transmit and receive signals to and from the storage device 9200 through the plurality of channels CH1 to CHm. For example, the memory controller 9100 can transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the storage device 9200 through the channels CH1 to CHm, or receive data DATAa to DATAm from the storage device 9200.

[0146] ​The memory controller 9100 can select one from among the NVM devices NVM11 to NVMmn connected to each of the channels CH1 to CHm by using a corresponding one of the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller 9100 can select the NVM device NVM11 from among the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 9100 can transmit a command CMDa, an address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0147] The memory controller 9100 can transmit and receive signals to and from the storage device 9200 through the channels different from each other in parallel. For example, the memory controller 9100 can transmit a command CMDb to the storage device 9200 through the second channel CH2 while transmitting a command CMDa to the storage device 9200 through the first channel CH1. For example, the memory controller 9100 can receive data DATAb from the storage device 9200 through the second channel CH2 while receiving data DATAa from the storage device 9200 through the first channel CH1.

[0148] The memory controller 9100 can control all operations of the storage device 9200. The memory controller 9100 can transmit signals to the channels CH1 to CHm, and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 9100 can transmit a command CMDa and an address ADDRa to the first channel CH1, and control one selected from among the NVM devices NVM11 to NVM1n.

[0149] Each of the NVM devices NVM11 to NVMmn can be operated via the control of the memory controller 9100. For example, the NVM device NVM11 can program data DATAa based on a command CMDa, an address ADDRa, and data DATAa provided to the first channel CH1. For example, the NVM device NVM21 can read data DATAb based on a command CMDb and an address ADDb provided to the second channel CH2, and transmit the read data DATAb to the memory controller 9100.

[0150] Although Figure 8 Although an example in which the storage device 9200 communicates with the memory controller 9100 through m channels and includes n NVM devices corresponding to each channel is illustrated, the number of channels and the number of NVM devices connected to one channel can be changed.

[0151] Figure 10 This is a block diagram of a UFS system 2000 according to an embodiment.

[0152] The UFS system 2000 may be a system conforming to the UFS standard announced by the Joint Electron Design and Development Association (JEDEC) and includes a UFS host 2100, a UFS device 2200, and a UFS interface 2300. (The last part is incomplete and likely refers to a separate concept.) Figure 10 Within the scope of the description conflict, for Figure 7 The above description of System 1000 can also be applied to... Figure 10 UFS system 2000.

[0153] In some embodiments, the UFS host 2100 and / or UFS device 2200 may correspond to a means for storing data according to an exemplary embodiment of the present invention. For example, the UFS device 2200 may include a first type of storage unit and a second type of storage unit.

[0154] Reference Figure 10 The UFS host 2100 can connect to the UFS device 2200 via the UFS interface 2300. When Figure 10 When the main processor 1100 is an application processor, the UFS host 2100 can be implemented as part of the application processor. The UFS host controller 2110 and host memory 2140 can respectively correspond to… Figure 7 The main processor 1100, controller 1120, and memory 1200a and 1200b are included. The UFS device 2200 can correspond to... Figure 7 The storage devices 1300a and 1300b, and the UFS device controller 2210 and NVM 2220 can respectively correspond to Figure 7 The memory controllers 1310a and 1310b, and NVM 1320a and 1320b.

[0155] The UFS host 2100 can include a UFS host controller 2110, an application 2120, a UFS driver 2130, a host memory 2140, and a UFS interconnect (UIC) layer 2150. The UFS device 2200 can include a UFS device controller 2210, an NVM 2220, a storage interface 2230, a device memory 2240, a UIC layer 2250, and a regulator 2260. The NVM 2220 can include a plurality of storage elements 2221. Although each storage element 2221 can include a V-NAND flash memory having a 2D structure or a 3D structure, each storage element 2221 can include another NVM such as a PRAM and / or a RRAM, etc. The UFS device controller 2210 can be connected to the NVM 2220 through the storage interface 2230. The storage interface 2230 can be set to comply with a standard protocol such as Toggle or ONFI.

[0156] The application 2120 can refer to a program that wants to communicate with the UFS device 2200 to use a function of the UFS device 2200. The application 2120 can send an input-output request (IOR) to the UFS driver 2130 for an input / output (I / O) operation on the UFS device 2200. The IOR can refer to a data read request, a data store (or write) request, and / or a data erase (or discard) request, but is not limited thereto.

[0157] The UFS driver 2130 can manage the UFS host controller 2110 through a UFS-host controller interface (UFS-HCI). The UFS driver 2130 can convert the IOR generated by the application 2120 into a UFS command defined by the UFS standard, and transmit the UFS command to the UFS host controller 2110. One IOR can be converted into a plurality of UFS commands. Although the UFS command can be basically defined by the SCSI standard, the UFS command can be a command dedicated to the UFS standard.

[0158] The UFS host controller 2110 can transmit the UFS command converted by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 through the UIC layer 2150 and the UFS interface 2300. The UFS host register 2111 of the UFS host controller 2110 can be used as a command queue (CQ) during transmission of the UFS command.

[0159] The UIC layer 2150 on the UFS host 2100 side can include a Mobile Industry Processor Interface (MIPI) M-PHY 2151 and a MIPI UniPro 2152, and the UIC layer 2150 on the UFS device 2200 side can also include a MIPI M-PHY 2251 and a MIPI UniPro 2252.

[0160] The UFS interface 2300 can include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n of the UFS device 2200, a pair of lines configured to transmit a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

[0161] The frequency of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be one of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 2100 can change the frequency of the reference clock signal REF_CLK during operation, i.e., during a data transmission / reception operation between the UFS host 2100 and the UFS device 2200. The UFS device 2200 can generate clock signals having various frequencies from the reference clock signal REF_CLK provided by the UFS host 2100 by using a phase-locked loop (PLL). Also, the UFS host 2100 can set a data rate between the UFS host 2100 and the UFS device 2200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate can be determined according to the frequency of the reference clock signal REF_CLK.

[0162] The UFS interface 2300 can support a plurality of lanes, each of which can be implemented as a pair of differential lines. For example, the UFS interface 2300 can include at least one receive lane and at least one transmit lane. In Figure 10 , the pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C can constitute a receive lane, and the pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C can constitute a transmit lane. Although one transmit lane and one receive lane are shown in Figure 9 , the number of transmit lanes and the number of receive lanes can be changed.

[0163] The receive channel and the transmit channel can transmit data based on a serial communication scheme. Due to the structure in which the receive channel and the transmit channel are separated, full-duplex communication between the UFS host 2100 and the UFS device 2200 can be enabled. That is, while data is received from the UFS host 2100 through the receive channel, the UFS device 2200 can transmit data to the UFS host 2100 through the transmit channel. In addition, control data (e.g., a command) from the UFS host 2100 to the UFS device 2200 and user data to be stored in or read from the NVM 2220 of the UFS device 2200 by the UFS host 2100 can be transmitted through the same channel. Therefore, between the UFS host 2100 and the UFS device 2200, in addition to a pair of receive channels and a pair of transmit channels, no separate channel for data transmission needs to be further provided.

[0164] The UFS device controller 2210 of the UFS device 2200 can control all operations of the UFS device 2200. The UFS device controller 2210 can manage the NVM 2220 by using a logical unit (LU) 2211, which is a logical data storage unit. The number of LUs 2211 can be 8, but is not limited thereto. The UFS device controller 2210 can include an FTL, and convert a logical data address (e.g., a logical block address (LBA)) received from the UFS host 2100 to a physical data address (e.g., a physical block address (PBA)) by using address mapping information of the FTL. A logical block configured to store user data in the UFS system 2000 can have a size within a predetermined range. For example, a minimum size of a logical block can be set to 4 Kbyte.

[0165] When a command from the UFS host 2100 is applied to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform an operation in response to the command, and transmit a completion response to the UFS host 2100 when the operation is completed.

[0166] As an example, when the UFS host 2100 intends to store user data in the UFS device 2200, the UFS host 2100 can transmit a data storage command to the UFS device 2200. When a response indicating that the UFS host 2100 is ready to receive user data (ready for transfer) ("ready for transfer" response) is received from the UFS device 2200, the UFS host 2100 can transmit user data to the UFS device 2200. The UFS device controller 2210 can temporarily store the received user data in the device memory 2240, and store the user data temporarily stored in the device memory 2240 in a selected location of the NVM 2220 based on the address mapping information of the FTL.

[0167] As another example, when the UFS host 2100 intends to read user data stored in the UFS device 2200, the UFS host 2100 can transmit a data read command to the UFS device 2200. The UFS device controller 2210 having received the command can read user data from the NVM 2220 based on the data read command, and store the read user data in the device memory 2240 temporarily. During the read operation, the UFS device controller 2210 can detect and correct errors in the read user data by using an ECC engine (not shown) embedded therein. More specifically, the ECC engine can generate parity bits for write data to be written into the NVM 2220, and the generated parity bits can be stored in the NVM 2220 together with the write data. During the reading of data from the NVM 2220, the ECC engine can correct errors in the read data by using the read data and the parity bits read from the NVM 2220, and output the error-corrected read data.

[0168] In addition, the UFS device controller 2210 can transmit the user data temporarily stored in the device memory 2240 to the UFS host 2100. Also, the UFS device controller 2210 can further include an AES engine (not shown). The AES engine can perform at least one of an encryption operation and a decryption operation on data transmitted to the UFS device controller 2210 by using a symmetric key algorithm.

[0169] The UFS host 2100 can store commands to be transmitted to the UFS device 2200 in the UFS host register 2111 which can be used as a common queue in order, and sequentially transmit the commands to the UFS device 2200. In this case, even when a previously transmitted command is still being processed by the UFS device 2200, that is, even before receiving a notification that the previously transmitted command has been processed by the UFS device 2200, the UFS host 2100 can transmit a next command pending in the CQ to the UFS device 2200. Accordingly, the UFS device 2200 can also receive the next command from the UFS host 2100 during the processing of the previously transmitted command. The maximum number of commands (or queue depth) that can be stored in the CQ can be, for example, 32. Also, the CQ can be implemented as a circular queue in which the beginning and end of a line of commands stored in the queue are indicated by a head pointer and a tail pointer.

[0170] Each of the plurality of storage elements 2221 can include a memory cell array (not shown) and a control circuit (not shown) configured to control an operation of the memory cell array. The memory cell array can include a 2D memory cell array or a 3D memory cell array. The memory cell array can include a plurality of memory cells. Although each memory cell is a single layer cell (SLC) set to store 1-bit information, each memory cell can be a cell set to store 2-bit or more information, such as a multi-layer cell (MLC), a triple layer cell (TLC), and a quad layer cell (QLC). The 3D memory cell array can include a vertical NAND string in which at least one memory cell is vertically oriented and located on another memory cell.

[0171] A voltage VCC, VCCQ, and VCCQ2, etc. can be applied to the UFS device 2200 as a power voltage. The voltage VCC can be a main power voltage for the UFS device 2200, and can be in a range of 2.4V to 3.6V. The voltage VCCQ can be a power voltage mainly used to supply a low voltage to the UFS device controller 2210, and can be in a range of 1.14V to 1.26V. The voltage VCCQ2 can be a power voltage used to mainly supply a voltage lower than the voltage VCC and higher than the voltage VCCQ to an I / O interface such as the MIPI M-PHY 2251, and can be in a range of 1.7V to 1.95V. The power voltages can be supplied to the respective components of the UFS device 2200 through a regulator 2260. The regulator 2260 can be implemented as a set of cell regulators connected to different ones of the above-described power voltages, respectively.

[0172] Figure 11 is a block diagram of a storage system 3000 according to an embodiment of the present application. Referring to Figure 11 , the storage system 3000 can include a storage device 3200 and a memory controller 3100. The storage device 3200 can correspond to one of the NVM devices NVM11 to NVMmn that communicates with the memory controller 9100 based on Figure 9 of the present application. The memory controller 3100 can correspond to the memory controller 9100 of Figure 9 the present application.

[0173] In some embodiments, the storage system 3000 can correspond to a device for storing data according to example embodiments of the present application. For example, the storage device 300 can include first type memory cells and second type memory cells, and the memory controller 3100 can store data according to the method of storing data described in reference to Figures 1 to 5 at least one of the present application.

[0174] The storage device 3200 can include first through eighth pins P11 through P18, a memory interface circuit 3210, a control logic circuit 3220, and a memory cell array 3330.

[0175] The memory interface circuit 3210 can receive a chip enable signal nCE from the memory controller 3100 through the first pin P11. The memory interface circuit 3210 can transmit and receive signals to and from the memory controller 3100 through the second through eighth pins P12 through P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit 3210 can transmit and receive signals to and from the memory controller 3100 through the second through eighth pins P12 through P18.

[0176] The memory interface circuit 3210 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 3100 through the second through fourth pins P12 through P14. The memory interface circuit 3210 can receive or transmit a data signal DQ to the memory controller 3100 through the seventh pin P17. Commands CMD, addresses ADDR, and data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 can include a plurality of pins corresponding to the plurality of data signals DQ, respectively.

[0177] The memory interface circuit 3210 can obtain a command CMD from the data signal DQ received in an enabled interval (e.g., a high level state) of the command latch enable signal CLE based on a switching time point of the write enable signal nWE. The memory interface circuit 3210 can obtain an address ADDR from the data signal DQ received in an enabled interval (e.g., a high level state) of the address latch enable signal ALE based on a switching time point of the write enable signal nWE.

[0178] In an exemplary embodiment, the write enable signal nWE can be maintained in a static state (e.g., a high level or a low level) and switched between a high level and a low level. For example, the write enable signal nWE can be switched in an interval in which a command CMD or an address ADDR is transmitted. Accordingly, the memory interface circuit 3210 can obtain the command CMD or the address ADDR based on a switching time point of the write enable signal nWE.

[0179] The memory interface circuit 3210 can receive a read enable signal nRE from the memory controller 3100 through the fifth pin P15. The memory interface circuit 3210 can receive or can transmit a data strobe signal DQS to the memory controller 3100 through the sixth pin P16.

[0180] In the data (DATA) output operation of the memory device 3200, the memory interface circuit 3210 can receive the read enable signal nRE toggled through the fifth pin P15 before outputting the data DATA. The memory interface circuit 3210 can generate the data strobe signal DQS toggled based on the toggling of the read enable signal nRE. For example, the memory interface circuit 3210 can generate the data strobe signal DQS toggled starting after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read enable signal nRE. The memory interface circuit 3210 can transmit a data signal DQ including the data DATA based on the toggling time point of the data strobe signal DQS. Accordingly, the data DATA can be aligned with the toggling time point of the data strobe signal DQS and transmitted to the memory controller 3100.

[0181] In the data (DATA) input operation of the memory device 3200, when receiving the data signal DQ including the data DATA from the memory controller 3100, the memory interface circuit 3210 can receive the data strobe signal DQS toggled as well as the data DATA. The memory interface circuit 3210 can obtain the data DATA from the data signal DQ based on the toggling time point of the data strobe signal DQS. For example, the memory interface circuit 3210 can sample the data signal DQ at the rising and falling edges of the data strobe signal DQS and obtain the data DATA.

[0182] The memory interface circuit 3210 can transmit state information of the memory device 3200 to the memory controller 3100 through the ready / busy output signal nR / B. When the memory device 3200 is in a busy state (i.e., when an operation is being performed in the memory device 3200), the memory interface circuit 3210 can transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 3100. When the memory device 3200 is in a ready state (i.e., when no operation is being performed or is completed in the memory device 3200), the memory interface circuit 3210 can transmit the ready / busy output signal nR / B indicating the ready state to the memory controller 3100. For example, when the memory device 3200 reads data DATA from the memory cell array 3330 in response to a page read command, the memory interface circuit 3210 can transmit the ready / busy output signal nR / B indicating the busy state (e.g., a low level) to the memory controller 3100. For example, when the memory device 3200 programs data DATA to the memory cell array 3330 in response to a program command, the memory interface circuit 3210 can transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 3100.

[0183] The control logic circuit 3220 can control all operations of the memory device 3200. The control logic circuit 3220 can receive the command / address CMD / ADDR obtained from the memory interface circuit 3210. The control logic circuit 3220 can generate control signals for controlling other components of the memory device 3200 in response to the received command / address CMD / ADDR. For example, the control logic circuit 3220 can generate various control signals for programming data DATA to the memory cell array 3330 or reading data DATA from the memory cell array 3330.

[0184] The memory cell array 3330 can store data DATA obtained from the memory interface circuit 3210 via control of the control logic circuit 3220. The memory cell array 3330 can output stored data DATA to the memory interface circuit 3210 via control of the control logic circuit 3220.

[0185] The memory cell array 3330 can include a plurality of memory cells. For example, the plurality of memory cells can be flash memory cells. However, the present application is not limited thereto, and the memory cells can be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, an embodiment in which the memory cells are NAND flash memory cells will be mainly described.

[0186] The memory controller 3100 can include first through eighth pins P21 through P28 and a controller interface circuit 3110. The first through eighth pins P21 through P28 can correspond to the first through eighth pins P11 through P18 of the memory device 3200, respectively.

[0187] The controller interface circuit 3110 can transmit a chip enable signal nCE to the memory device 3200 through the first pin P21. The controller interface circuit 3110 can transmit and receive a signal to and from the memory device 3200 through the second through eighth pins P22 through P28, in which the memory device 3200 is selected by the chip enable signal nCE.

[0188] The controller interface circuit 3110 can transmit a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 3200 through the second through fourth pins P22 through P24. The controller interface circuit 3110 can transmit or receive a data signal DQ to or from the memory device 3200 through the seventh pin P27.

[0189] The controller interface circuit 3110 can transmit a data signal DQ including a command CMD or an address ADDR together with a toggled write enable signal nWE to the memory device 3200. The controller interface circuit 3110 can transmit a data signal DQ including a command CMD to the memory device 3200 by transmitting a command latch enable signal CLE having an enable state. Also, the controller interface circuit 3110 can transmit a data signal DQ including an address ADDR to the memory device 3200 by transmitting an address latch enable signal ALE having an enable state.

[0190] The controller interface circuit 3110 can transmit a read enable signal nRE to the memory device 3200 through the fifth pin P25. The controller interface circuit 3110 can receive or transmit a data strobe signal DQS to or from the memory device 3200 through the sixth pin P26.

[0191] In a data (DATA) output operation of the memory device 3200, the controller interface circuit 3110 can generate a toggled read enable signal nRE and transmit the read enable signal nRE to the memory device 3200. For example, before outputting the data DATA, the controller interface circuit 3110 can generate the read enable signal nRE which changes from a static state (e.g., a high level or a low level) to a toggled state. Accordingly, the memory device 3200 can generate a toggled data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 3110 can receive the data signal DQ including the data DATA and the toggled data strobe signal DQS from the memory device 3200. The controller interface circuit 3110 can obtain the data DATA from the data signal DQ based on a toggling point of the data strobe signal DQS.

[0192] In a data (DATA) input operation of the memory device 3200, the controller interface circuit 3110 can generate a toggled data strobe signal DQS. For example, before transmitting the data DATA, the controller interface circuit 3110 can generate the data strobe signal DQS which changes from a static state (e.g., a high level or a low level) to a toggled state. The controller interface circuit 3110 can transmit the data signal DQ including the data DATA to the memory device 3200 based on a toggling point of the data strobe signal DQS.

[0193] The controller interface circuit 3110 can receive a ready / busy output signal nR / B from the memory device 3200 through an eighth pin P28. The controller interface circuit 3110 can determine state information of the memory device 3200 based on the ready / busy output signal nR / B.

[0194] Figure 12 A block diagram of a data center 4000 to which a memory device according to an embodiment of the present application is applied.

[0195] Referring to Figure 12 The data center 4000 can be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 4000 can be a system for operating a search engine and a database, and can be a computing system used by a company such as a bank or a government agency. The data center 4000 can include application servers 4100 to 4100n and storage servers 4200 to 4200m. According to an embodiment, the number of the application servers 4100 to 4100n and the number of the storage servers 4200 to 4200m can be variously selected. The number of the application servers 4100 to 4100n and the number of the storage servers 4200 to 4200m can be different from each other.

[0196] In some embodiments, the storage server 4200 and / or the application server 4100 can correspond to an apparatus for storing data according to example embodiments of the present application. For example, the storage server 4200 can include a first type of storage unit and a second type of storage unit, and the application server 4100 or the storage server 4200 can store data according to the method of storing data described with reference to at least one of FIGS. 1 to 3. Figures 1 to 5

[0197] The application server 4100 or the storage server 4200 can include at least one of a processor 4110 and 4210 and a memory 4120 and 4220. The storage server 4200 will now be described as an example. The processor 4210 can control all operations of the storage server 4200, access the memory 4220, and execute instructions and / or data loaded into the memory 4220. The memory 4220 can be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (NVMe DIMM). In some embodiments, the number of processors 4210 and memories 4220 included in the storage server 4200 can be variously selected. In an embodiment, the processor 4210 and the memory 4220 can provide a processor-memory pair. In an embodiment, the number of processors 4210 can be different from the number of memories 4220. The processor 4210 can include a single core processor or a multi-core processor. The above description of the storage server 4200 can be similarly applied to the application server 4100. In some embodiments, the application server 4100 can not include the storage 4150. The storage server 4200 can include at least one storage 4250. According to an embodiment, the number of storages 4250 included in the storage server 4200 can be variously selected.

[0198] The application servers 4100 to 4100n can communicate with the storage servers 4200 to 4200m through the network 4300. The network 4300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, the FC can be a medium for relatively high-speed data transmission, and an optical switch having high performance and high availability can be used. According to the access method of the network 4300, the storage servers 4200 to 4200m can be set as file storage, block storage, or object storage.

[0199] ​In an embodiment, the network 4300 can be a network dedicated for storage, such as a storage area network (SAN). For example, the SAN can be an FC-SAN, which uses an FC network and is implemented according to an FC protocol (FCP). As another example, the SAN can be an Internet Protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is implemented according to a SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In another embodiment, the network 4300 can be a general-purpose network, such as a TCP / IP network. For example, the network 4300 can be implemented according to a protocol such as Fibre Channel over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabric (NVMe-oF).

[0200] Hereinafter, the application server 4100 and the storage server 4200 will be mainly described. The description of the application server 4100 can be applied to another application server 4100n, and the description of the storage server 4200 can be applied to another storage server 4200m.

[0201] The application server 4100 can store data requested by a user or a client in one of the storage servers 4200 to 4200m through the network 4300. In addition, the application server 4100 can obtain data requested to be read by a user or a client from one of the storage servers 4200 to 4200m through the network 4300. For example, the application server 4100 can be implemented as a web server or a database management system (DBMS).

[0202] The application server 4100 can access the memory 4120n or the storage 4150n included in another application server 4100n through the network 4300. Alternatively, the application server 4100 can access the memory 4220 to 4220m or the storage 4250 to 4250m included in the storage servers 4200 to 4200m through the network 4300. Accordingly, the application server 4100 can perform various operations on data stored in the application servers 4100 to 4100n and / or the storage servers 4200 to 4200m. For example, the application server 4100 can execute an instruction for moving or copying data between the application servers 4100 to 4100n and / or the storage servers 4200 to 4200m. In this case, data can be moved from the storage 4250 to 4250m of the storage servers 4200 to 4200m through the memory 4220 to 4220m of the storage servers 4200 to 4200m or directly to the memory 4120 to 4120n of the application servers 4100 to 4100n. Data moved through the network 4300 can be data encrypted for security or privacy.

[0203] The interface 4254 can provide a physical connection between the processor 4210 and the controller 4251 and a physical connection between the network interface card (NIC) 4240 and the controller 4251. For example, the interface 4254 can be implemented using a direct attached storage (DAS) scheme in which the storage device 4250 is directly connected with a dedicated cable. For example, the interface 4254 can be implemented by using various interface schemes such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and CF card interface.

[0204] The storage server 4200 can further include a switch 4230 and a network interconnect (NIC) 4240. The switch 4230 can selectively connect the processor 4210 to the storage device 4250 or selectively connect the NIC 4240 to the storage device 4250 via control of the processor 4210.

[0205] In an embodiment, the NIC 4240 can include a network interface card and a network adapter. The NIC 4240 can be connected to the network 4300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 4240 can include an internal memory, a digital signal processor (DSP), and a host bus interface, and be connected to the processor 4210 and / or the switch 4230 through the host bus interface. The host bus interface can be implemented as one of the above-described examples of the interface 4254. In an embodiment, the NIC 4240 can be integrated with at least one of the processor 4210, the switch 4230, and the storage device 4250.

[0206] In the storage server 4200 to 4200m or the application server 4100 to 4100n, the processor can send a command to the storage device 4150 to 4150n and 4250 to 4250m or the memory 4120 to 4120n and 4220 to 4220m and program or read data. In this case, the data can be data whose error is corrected by the ECC engine. The data can be data to which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and can include cyclic redundancy code (CRC) information. The data can be data encrypted for security or privacy.

[0207] The storage devices 4150 through 4150n and 4250 through 4250m can transmit control signals and command / address signals to the NAND flash devices 4252 through 4252m in response to read commands received from the processor. Thus, when data is read from the NAND flash devices 4252 through 4252m, a read enable (RE) signal can be input as a data output control signal, and thus, data can be output to a DQ bus. A data strobe signal DQS can be generated using the RE signal. The command and address signals can be latched in a page buffer depending on a rising edge or a falling edge of a write enable (WE) signal.

[0208] The controller 4251 can control all operations of the storage device 4250. In an embodiment, the controller 4251 can include an SRAM. The controller 4251 can write data to the NAND flash devices 4252 in response to a write command or read data from the NAND flash devices 4252 in response to a read command. The write command and / or the read command can be provided, for example, from the processor 4210 of the storage server 4200, the processor 4210m of another storage server 4200m, or the processors 4110 and 4110n of the application servers 4100 and 4100n. The DRAM 3253 can temporarily store (or buffer) data to be written to the NAND flash devices 4252 or data read from the NAND flash devices 4252. Also, the DRAM 3253 can store metadata. Here, the metadata can be user data or data generated by the controller 4251 for managing the NAND flash devices 4252. The storage device 4250 can include a secure element (SE) for security or privacy.

[0209] Example embodiments of the inventive concept can be applied to any storage device including a nonvolatile memory device. For example, example embodiments of the inventive concept can be applied to an SSD, an NVMe, an eMMC, a UFS, etc.

[0210] The method of storing data according to example embodiments of the present invention can store data in a storage unit (e.g., a first type storage unit or a second type storage unit) corresponding to a write priority of the data according to the write priority of the data, and thus, can improve performance and / or user experience of a storage device using a plurality of types of storage units.

[0211] The method for storing data according to the example embodiments of the present application can store data in a storage unit (e.g., a first type storage unit or a second type storage unit) corresponding to the write priority of the data according to the write priority of the data determined based on the first data feature of the data, and thus, different write strategies can be used for different data (e.g., data requiring fast writing is written to the second type storage unit having a high write speed, and data not requiring fast writing is written to the first type storage unit having a low write speed), thereby maximizing the utilization of the first type storage unit and the second type storage unit and improving the write performance.

[0212] The method for storing data according to the example embodiments of the present application can determine the write priority of data as a high write priority (e.g., a second write priority) and write the data to the second type storage unit having a high write speed when the application to which the data belongs is an application requiring fast writing of data, and determine the write priority of data as a low write priority (e.g., a first write priority) and write the data to the first type storage unit having a low write speed when the application to which the data belongs is an application not requiring fast writing of data, and thus, the processor can more reasonably use the first type storage unit and the second type storage unit according to the application to which the data belongs.

[0213] The method for storing data according to the example embodiments of the present application can identify the application to which the data belongs using the pre-trained application recognition model, and thus, the application to which the data belongs can be accurately identified.

[0214] The method for storing data according to the example embodiments of the present application can perform the writing of data based on the optimal preset write strategy among a plurality of write strategies obtained through iterative testing, and thus, the performance of the storage device can be improved.

[0215] The method for storing data according to the example embodiments of the present application can further determine the write priority of data using the second data feature for different applications, and thus, the use of the first type storage unit and the second type storage unit can be optimized, and the write performance and the lifespan can be improved.

[0216] The method for storing data according to the example embodiments of the present application can store data in a storage unit corresponding to the write priority of the data according to the write priority of the data when the write booster function is turned on, instead of writing all data to the second type storage unit (e.g., SLC), and thus, the amount of data written to the second type storage unit can be reduced, thereby prolonging the lifespan of the second type storage unit and improving the write performance.

[0217] According to one or more example embodiments, the methods described above can be implemented using hardware, a combination of hardware and software, or non-transitory storage medium storing software executable to perform its functionality.

[0218] The hardware can be implemented using processing circuitry such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more systems on a chip (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more application-specific integrated circuits (ASICs), or any other device(s) capable of responding to and executing instructions in a defined manner.

[0219] The software can include computer programs, program code, instructions, or some combination thereof, for independently or collectively instructing or configuring a hardware device to perform desired functions. The computer programs and / or program code can include program or computer-readable instructions, software components, software modules, data files, data structures, and the like, capable of being implemented by one or more hardware devices such as one or more of the hardware devices mentioned previously. Examples of program code include both machine code generated by a compiler and higher level program code that is executed by an interpreter.

[0220] For example, when the hardware device is a computer processing device (e.g., one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device can be configured to execute program code that performs arithmetic, logical, and input / output operations by following the program code’s instructions. Once the program code is loaded into the computer processing device, the computer processing device can be programmed to execute the program code, thereby transforming the computer processing device into a special-purpose computer processing device. In a more particular example, when program code is loaded into a processor, the processor becomes programmed with the program code and the operations corresponding thereto, thereby transforming the processor into a special-purpose processor. In another example, the hardware device can be an integrated circuit (e.g., an ASIC) customized to be a special-purpose processing circuit.

[0221] A hardware device, such as a computer processing device, can run an operating system (OS) and one or more software applications running on the OS. In response to execution of software, the computer processing device can also access, store, manipulate, process, and create data. For the sake of simplicity, one or more example embodiments can be exemplified as one computer processing device, however, those skilled in the art will appreciate that a hardware device can include multiple processing elements and multiple types of processing elements. For example, a hardware device can include multiple processors or one processor and one controller. Further, other processing configurations are possible such as parallel processors.

[0222] Software and / or data can be permanently or transitorily embodied in any type of computer storage or data storage devices or mediums, including, but not limited to, one or more computer-readable or machine-readable storage media. Examples of computer-readable storage media include a hard disk, a floppy disk, magnetic tape, optical storage media such as compact disc (CD) or DVD, tape, flash memory, memristor, and / or electrical or optical-pixel storage. Use of the term "computer-readable storage media" or "computer-readable storage medium" herein can also be taken to

[0223] For example, according to an example embodiment of the present application, there is provided a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements at least a method of storing data, comprising: determining a write priority of data; in response to the write priority of the data corresponding to a first write priority, writing the data to a first type of storage unit; in response to the write priority of the data corresponding to a second write priority, writing the data to a second type of storage unit, wherein the second write priority is higher than the first write priority, and a write speed of the second type of storage unit is higher than a write speed of the first type of storage unit. Further, other methods of the present application can also be similarly implemented by a computer-readable storage medium storing a computer program.

[0224] The storage medium can also include one or more storage devices of the unit and / or apparatus according to one or more example embodiments. The one or more storage devices can be tangible or non-transitory computer-readable storage media such as random access memory (RAM), read only memory (ROM), a permanent mass storage device (such as a disk drive), and / or any other like data storage structure capable of storing and recording data. The one or more storage devices can be configured to store one or more operating systems and / or computer programs, program code, instructions, or some combination thereof for implementing the example embodiments described herein. A drive mechanism can also be used to load the computer programs, program code, instructions, or some combination thereof from the separate computer-readable storage medium into the one or more storage devices and / or the one or more computer processing devices. Such separate computer-readable storage medium can include a universal serial bus (USB) flash drive, memory stick, Blu-ray / DVD / CD-ROM drive, memory card, and / or other like computer-readable storage media. The computer programs, program code, instructions, or some combination thereof can be loaded via a network interface, rather than via a computer-readable storage medium, from a remote data storage device. Further, the computer programs, program code, instructions, or some combination thereof can be loaded from a remote computing system via a network, where the remote computing system is configured to transmit and / or distribute the computer programs, program code, instructions, or some combination thereof over the network. The remote computing system can transmit and / or distribute the computer programs, program code, instructions, or some combination thereof via a wired interface, a wireless interface, and / or any other like interface.

[0225] For the purpose of example embodiments, one or more hardware devices, storage media, computer programs, program code, instructions, or some combination thereof can be specially designed and constructed for the purposes of example embodiments, or they can be known devices that are altered and / or modified for the purposes of example embodiments.

[0226] The above description is for illustrative example embodiments and should not be construed as limiting the example embodiments. Although some example embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the example embodiments without materially departing from the novel teachings and advantages of the example embodiments of this disclosure. Accordingly, all such modifications are intended to be included within the scope of the example embodiments of this disclosure as defined in the claims. Therefore, it is to be understood that the foregoing description is illustrative of various example embodiments and should not be construed as limiting the example embodiments of the disclosure. Modifications can be made by those skilled in the art, particularly in light of the foregoing teachings. Therefore, without departing from the spirit of the disclosure, the present example embodiments can be implemented otherwise than as specifically described herein.

Claims

1. A method of storing data, the method comprising: determining a write priority of the data in response to a write request of the data by a host; writing the data to a first type of storage unit in response to the write priority of the data being a first write priority; writing the data to a second type of storage unit in response to the write priority of the data being a second write priority, wherein the second write priority is higher than the first write priority, and a write speed of the second type of storage unit is higher than a write speed of the first type of storage unit, wherein the step of determining the write priority of the data comprises: obtaining a first data feature of the data, wherein the first data feature comprises a file type and a synchronous write proportion; determining the write priority of the data based on the first data feature of the data, wherein the step of determining the write priority of the data based on the first data feature of the data comprises: determining an application to which the data belongs based on the first data feature of the data; determining the write priority of the data based on the determined application, wherein the determining the application to which the data belongs comprises: determining the application to which the data belongs based on the first data feature of the data by using an application recognition model, wherein the application recognition model is a pre-trained prediction model.

2. The method of claim 1, wherein, The first data feature of the data further comprises one or more of the following features: time attribute information, a file system type, a synchronous identifier of a database file, a data synchronization identifier, a master device number, a slave device number, a logical block address sector number, a write data size, and a process priority.

3. The method of claim 1, wherein, The step of determining the write priority of the data based on the determined application comprises: obtaining a second data feature of the data based on the application to which the data belongs; determining the write priority of the data based on the second data feature of the data and a preset write strategy of the application, wherein the preset write strategy of the application comprises a correspondence between the second data feature of the data of the application and at least one write priority, and the at least one write priority comprises the first write priority and the second write priority.

4. The method of claim 1, wherein, The method is executed when a write booster function is enabled.

5. An apparatus for storing data, the apparatus comprising: a priority determination module configured to determine a write priority of the data in response to a write request of the data by a host; a write module configured to: write the data to a first type of storage unit in response to the write priority of the data being a first write priority; write the data to a second type of storage unit in response to the write priority of the data being a second write priority, wherein the second write priority is higher than the first write priority, and a write speed of the second type of storage unit is higher than a write speed of the first type of storage unit, wherein the priority determination module comprises an obtaining unit and a determining unit, wherein the obtaining unit is configured to obtain a first data feature of the data, wherein the first data feature comprises a file type and a synchronous write proportion, wherein the determining unit is configured to determine the write priority of the data based on the first data feature of the data, wherein the determining unit is configured to: determine, based on the first data feature of the data, an application to which the data belongs; determine, based on the determined application, a write priority of the data, wherein the determining unit is configured to: determine, based on the first data feature of the data, the application to which the data belongs by using an application recognition model, wherein the application recognition model is a pre-trained prediction model.

6. The apparatus of claim 5, wherein, The first data feature of the data further includes one or more of the following features: time attribute information, file system type, database file synchronization identifier, data synchronization identifier, master device number, slave device number, logical block address sector number, write data size, process priority.

7. The apparatus of claim 5, wherein, The determining unit is configured to: obtain a second data feature of the data based on the application to which the data belongs; determine the write priority of the data based on the second data feature of the data and a preset write strategy of the application, wherein the preset write strategy of the application includes a correspondence between the second data feature of the data of the application and at least one write priority, and the multiple write priorities include a first write priority and a second write priority.

8. The apparatus of claim 5, wherein, The priority determination module is configured to determine the write priority of the data in response to a write request of the host to the data when the write booster is turned on.

9. A computer-readable storage medium storing a computer program, wherein, When the computer program is executed by the processor, the method for storing data according to any one of claims 1-4 is implemented.

10. An electronic system comprising: a storage device including first type storage units and second type storage units; a host processor configured to control the storage device to store data according to the method of any one of claims 1-4.

11. A host storage system comprising: a host; a storage device including first type storage units and second type storage units, wherein the host is configured to control the storage device to store data according to the method of any one of claims 1-4.

12. A storage device comprising: first type storage units and second type storage units; a memory controller configured to store data according to the method of any one of claims 1-4.

13. A Universal Flash Storage (UFS) system comprising: a UFS host; a UFS interface; UFS units including first type storage units and second type storage units and configured to communicate with the UFS host via the UFS interface, wherein the UFS host is configured to control the UFS units to store data according to the method of any one of claims 1-4.

14. A data center comprising: an application server; a storage server including first type storage units and second type storage units and configured to communicate with the application server via a network, wherein the application server or the storage server is configured to store data according to the method of any one of claims 1-4.

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