A mixed-size unit circuit layout design method based on Newton iteration method

Abstract

The present invention provides a mixed-size unit circuit layout design method based on the Newton iteration method. First, multiple row height units are preprocessed into single row height sub-units and placed on the nearest row that matches the power line. Then, a network flow model is established for all units, and they are diffused to avoid local congestion. Then, the legalization problem is expressed as a convex quadratic programming problem, and the quadratic programming problem is equivalently converted into a linear complementary problem. The linear complementary problem is then equivalently expressed as a generalized absolute value equation and solved using the Newton iteration method. Finally, the multiple row height standard units are restored and placed on the available positions in the row, and the remaining illegal units are processed. Compared with the prior art, the present invention solves the generalized absolute value equation equivalent to the legalization problem through the Newton iteration method, without considering the parameter setting, avoiding the limitation of being unable to effectively solve due to improper parameter selection. The present invention can effectively accelerate the convergence speed of the iterative process and quickly obtain a high-quality neighborhood solution to the legalization problem.

Description

Technical Field

[0001] The present invention relates to the field of very large scale integrated circuit physical design automation, and in particular to a mixed-size unit circuit layout design method based on Newton iteration method. Background Art

[0002] The physical design of very large-scale integrated circuit (VLSI) circuits is crucial to semiconductor chip manufacturing. With the advancement of VLSI advanced node technology, designing circuits with libraries of standard cells of varying heights has become mainstream. Standard cells with multiple row heights offer improved pin accessibility and reduced latency, but their emergence also presents greater challenges during the layout phase. Unlike single-row-height standard cells, where the movement only requires considering the overlap of cells within that row, the movement of multiple-row-height cells also requires considering the overlap of cells in adjacent rows. Furthermore, the layout of mixed-size cells must adhere to power rail matching constraints. The sheer number of standard cells in circuit design leads to a combinatorial explosion in the solution space, resulting in extremely high computational complexity. Therefore, the layout problem is considered NP-hard. For such problems, iterative solutions are often used to obtain approximate solutions. However, how to quickly and efficiently approach the optimal solution remains a pressing challenge.

[0003] Existing legalization algorithms are divided into heuristic algorithms and analytical algorithms. Heuristic algorithms have the advantage of fast solution speed, but are prone to getting stuck in local optimal solutions. Analytical methods usually establish a mathematical model for the legalization problem and then solve it. Chen Jianli et al. (CN 106971042 A) proposed to equivalently represent the quadratic programming problem in the legalization problem as a linear complementarity problem and apply the modular matrix splitting iteration method to solve the linear complementarity problem. Summary of the Invention

[0004] Purpose of the invention: The purpose of the present invention is to re-express the linear complementary problem generated in the legalization process of very large-scale integrated circuit design as an equivalent generalized absolute value equation. Therefore, a mixed-size unit circuit layout design method based on the Newton iteration method is provided, which mainly involves a solution method in the legalization stage of the layout process, by converting the linear complementary problem equivalent to the legalization problem into a generalized absolute value equation, and then using a Newton iteration method to solve it; compared with the existing method, this method does not require parameter determination, avoiding the problem of difficulty in convergence or slow convergence speed caused by improper parameter selection; the invention can greatly reduce the number of iterations and running time in the iterative solution process, and further improve the design efficiency of the layout stage.

[0005] To achieve the above objectives, the present invention provides a mixed-size unit circuit layout design method based on Newton iteration method, comprising the following steps:

[0006] S1: pre-processing the standard unit, dividing the multiple-row-height standard unit into multiple single-row-height standard sub-units;

[0007] S2: Diffusion of standard cells based on network flow algorithm;

[0008] S3: Formulate the mixed-size standard unit legalization problem as a quadratic programming mathematical model;

[0009] S4: Convert the quadratic programming model into a linear complementarity problem;

[0010] S5: Transform the linear complementarity problem into a generalized absolute value equation;

[0011] S6: Solve the generalized absolute value equation using Newton's iteration method;

[0012] S7: unify the x-coordinates of the sub-units divided into the multiple-row height standard unit and align them to the available positions in the row;

[0013] S8: Legalize the remaining illegal units.

[0014] Further preferably, the specific implementation of step S1 includes: given a rectangular layout area of a chip, (0, 0) and (W, H) are used to represent the coordinates of its lower left corner and upper right corner respectively; W represents the width of the layout area, and H represents the height of the layout area; the set of movable standard cells to be laid out is C = (c1, c2, ... c n ), where unit c i The initial lower left corner coordinate obtained from the global stage is The unit width and height are w i , h i , the coordinates after the legalization stage are (x i ,y i ) indicates; for multiple-row high standard units, they are represented as multiple sub-units, using (c i1 , c i2 ,…c it ), where t means the height of the standard cell is t times the row height.

[0015] Further preferably, the height of all cells is an integer multiple of the row height; then all standard cells are aligned to the nearest row that matches their power lines; the power lines and ground lines are arranged alternately in the row; for cells with odd multiples of row height, the power types at both ends are different, so as long as they do not exceed the layout area, they can be placed on any row, and the power type can be matched by flipping; for cells with even multiples of row height, the power types at both ends are the same, so they need to be placed on the row that matches their power type.

[0016] Further preferably, the specific implementation of step S2 includes: in order to avoid excessive crowding of standard cells in subsequent processing, the cells are diffused using a network flow algorithm to ensure that the width of cells in each row does not exceed the width of the row; the layout area is evenly divided into grids in the horizontal and vertical directions, and each grid constitutes a node in the network flow graph; in addition, two additional nodes are created, namely, super source nodes (N B ) and super sink nodes (N E ); Calculate the sum of the areas of the cells in each grid s C , and compare it with the grid area s G Compare; if s C >s G , then the grid is called the overflow grid and the overflow area s is recorded o ; if s C ≤s G , then the grid is called an idle grid and the remaining idle area s is recorded f ; For the overflow grid, set it to the source node N in the network flow s , and establish a line from N B to N s The arc, the capacity and cost on the arc are set to s o and zero; for an idle grid, set it to target node N t , and establish a line from N t to N E The arc, the capacity and cost on the arc are set to s f and 0; and for the overflow grid, find the free grid adjacent to it and establish s to N t The arc, the capacity and cost on the arc are set to infinity and the displacement of the unit moving between the two grids respectively; for the established network flow graph, the strategy of unit movement in the grid can be obtained, and the unit is moved according to the strategy. The unit after movement c i The coordinates are

[0017] Further preferably, the specific implementation of step S3 includes: the legalization process is to eliminate the overlap between cells, and minimize the total displacement of the standard cell as the optimization goal, and in the above steps, the cell has been moved in the minimum vertical direction, that is, aligned with the matching power rail, so the displacement in the vertical direction can be ignored, and the legalization problem is described as the following model (1):

[0018]

[0019] The above model is rewritten as the standard form of convex quadratic programming problem, namely:

[0020]

[0021] in, is an identity matrix, is a column vector whose components consist of the initial horizontal coordinates of the standard cells; any adjacent pair of standard cells should satisfy the inequality x j -x i ≥w i (x j ≥x i ), establish this inequality between all adjacent cells, and it can be written in matrix form Wx≥d, where W is a matrix containing only two elements -1 and 1 in each row, representing the cell c i and c j The horizontal coordinate x j , x i , d is a column vector, where the corresponding component represents the left unit c i The width w i ; Then the number of rows of W and d is the number of constraints, and the number of columns of W is the total number of standard cells, that is, the sum of the number of single-row-height cells and the number of sub-cells into which multiple-row-height cells are split. R is also a matrix consisting of -1 and 1 in each row, where -1 represents a multiple of the row height unit c. i Subunit c i1 , 1 represents c i Subunit c i2 , and so on; x i2 -x i1 =0 guarantee c i The horizontal coordinates of the subunits are equal, so the constraint matrix Rx=0 can be obtained, where Using a simple example diagram of a mixed-size standard cell layout, the matrices W, R, and vector d constructed based on this location are shown below:

[0022] R=(0 -1 1 0), d=(w1 w2);

[0023] By using the Lagrange multiplier method, the equality constraints in the quadratic programming are added to the objective function, and (3) can be expressed as:

[0024]

[0025] Here, λ is the Lagrange multiplier.

[0026] Further preferably, the specific implementation of step S4 is: using the Karush-Kuhn-Tucker (KKT) condition, the model (3) can be written as the KKT equations with the following conditions:

[0027]

[0028] Rewrite equation (4) into the following form:

[0029]

[0030] make The problem then becomes finding a pair of non-negative and orthogonal solution vectors The following conditions are met:

[0031] w=Az+q≥0,z≥0and w T z≥0. (6)

[0032] Problem (6) is a linear complementarity problem, where

[0033] Further preferably, the specific implementation of step S5 is as follows: since the (2, 2) block of the system matrix A in the linear complementarity problem is 0, it is a semi-positive definite matrix; a perturbation is added to the (2, 2) block of the matrix, i.e., εI m , then the blocks of matrix A are:

[0034]

[0035] in is the identity matrix, let z = (|v|-v), w = (|v|+v), then (6) can be transformed into the following equivalent generalized absolute value equation:

[0036] (A+I)v-(AI)|v|=q. (7)

[0037] Let C = A + I, B = AI, then (7) can be restated as follows:

[0038] Cv-B|v|=q. (8).

[0039] Further preferably, the specific implementation of step S6 is: let F(v) = Cv-B|v|-q, and let F(v) = 0; since F(v) is a piecewise linear vector function, it is not differentiable and the Newton iteration method cannot be directly applied to solve this equation. Therefore, based on the subgradient of the component of |v|, the generalized Jacobian of |v| is used. To obtain the approximate solution of the generalized absolute value equation (8); It can be represented by a diagonal matrix D(v), where and

[0040]

[0041] The Newton iteration method is defined as follows:

[0042] v k+1 =v k -F′(v k ) -1 F(v k ), k=0, 1, 2,…, (10)

[0043] As long as F(v k )'s Jacobian matrix F'(v k ) exists and is reversible, we can use (10) to solve F(v), that is,

[0044] v k+1 =v k -(C-BD(v k )) -1 (Cv k -B|v k |-q). (11)

[0045] Multiply both sides of the above formula (11) by (C-BD(v k )) can be obtained

[0046] (C-BD(v k ))v k+1 =(C-BD(v k ))v k -(Cv k -B|v k |-q). (12)

[0047] Since D(v k )v k =|v k |, after rearranging formula (12), we can get

[0048] (C-BD(v k ))v k+1 =q. (13)

[0049] Since C = A + I and B = AI, the linear complementarity problem equivalent to the legalization problem can be transformed into the following iterative format for solution:

[0050] v k+1 =((A+I)-(AI)D(v k )) -1 q. (14)

[0051] Given an arbitrary initial vector Compute v by iteratively solving the linear system k+1 The value of the absolute residual vector is RES(v( k )):=|z (k+1) -z (k)||2 is less than or equal to a given constant, then it can be considered an iterative sequence Converges, and z (k) =(|v (k) |-v (k) ), k=0, 1, 2,….

[0052] Further preferably, the specific implementation method of step S7 is: sorting the x-coordinates of all subunits of each multiple row height standard unit in ascending order, the median is the x-coordinate of the multiple row height unit, and then placing the unit at the closest available position to the obtained x-coordinate.

[0053] Further preferably, the specific implementation of step S8 is as follows: for a few standard cells that still overlap or exceed the right boundary of the layout area, starting from the upper right corner of the layout area, traverse the standard cells from right to left and from top to bottom. If the cell ci exceeds the right boundary, its coordinates are set to Ww i , if unit c i with c i-1 If they overlap, c i-1 Set the coordinate to x i -w i-1 Since moving multiple-row-height cells may cause cells in adjacent rows to overlap, multiple-row-height cells that have already been moved in the previous row will not be moved in the next row. Next, the standard cells are traversed again from left to right and from bottom to top according to the same rules. After this step, all cell overlaps can be eliminated.

[0054] The above technical solution of the present invention has the following advantages over the existing technology: a mixed-size unit circuit layout design method based on the Newton iteration method, first pre-processing the multiple row height units into single row height sub-units, and placing them on the nearest row that matches the power line, then establishing a network flow model for all units, diffusing them to avoid local congestion, then expressing the legalization problem as a convex quadratic programming problem, and equivalently converting the quadratic programming problem into a linear complementary problem, then equivalently expressing the linear complementary problem as a generalized absolute value equation, solving it using the Newton iteration method, finally restoring the multiple row height standard units and placing them on the placeable positions in the row, and processing the remaining illegal units. Compared with the existing technology, the present invention solves the generalized absolute value equation equivalent to the legalization problem through the Newton iteration method, without considering the parameter setting, avoiding the limitation of being unable to effectively solve due to improper parameter selection, and the present invention can effectively accelerate the convergence speed of the iterative process and quickly obtain a high-quality neighborhood solution to the legalization problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1It is a flow chart for legalization of mixed-size standard cell circuits;

[0056] Figure 2 This is a layout diagram that takes into account power rail constraints;

[0057] Figure 3 This is an example layout diagram of mixed-size standard cells.

[0058] Figure 4 This is a diagram of the steps for solving the problem using the Newton iteration method;

[0059] Figure 5 It is an iterative diagram of an embodiment of the Newton iteration method for solving the generalized absolute value equation derived from the legalization problem. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative work shall fall within the scope of protection of the present invention.

[0061] like Figure 1 As shown, a mixed-size unit circuit layout design method based on Newton iteration method includes the following steps:

[0062] S1: pre-processing the standard unit, dividing the multiple-row-height standard unit into multiple single-row-height standard sub-units;

[0063] S2: Diffusion of standard cells based on network flow algorithm;

[0064] S3: Formulate the mixed-size standard unit legalization problem as a quadratic programming mathematical model;

[0065] S4: Convert the quadratic programming model into a linear complementarity problem;

[0066] S5: Transform the linear complementarity problem into a generalized absolute value equation;

[0067] S6: Solve the generalized absolute value equation using Newton's iteration method;

[0068] S7: unify the x-coordinates of the sub-units divided into the multiple-row height standard unit and align them to the available positions in the row;

[0069] S8: Legalize the remaining illegal units.

[0070] The specific implementation of step S1 includes: given a rectangular layout area of a chip, (0, 0) and (W, H) are used to represent the coordinates of its lower left corner and upper right corner respectively; W represents the width of the layout area, and H represents the height of the layout area; the set of movable standard cells to be laid out is C = (c1, c2, ... c n ), where unit c i The initial lower left corner coordinate obtained from the global stage is The unit width and height are w i , h i , the coordinates after the legalization stage are (x i ,y i ) indicates; for multiple-row high standard units, they are represented as multiple sub-units, using (c i1 , c i2 ,…c it ), where t means the height of the standard cell is t times the row height; note that the height of all cells is an integer multiple of the row height; then align all standard cells to the nearest row that matches their power lines; the power lines and ground lines are staggered in the row; for cells with odd-numbered row heights, the power types at both ends are different, so as long as they do not exceed the layout area, they can be placed on any row, and the power type can be matched by flipping; for cells with even-numbered row heights, the power types at both ends are the same, so they need to be placed on the row that matches their power type; such as Figure 2 As shown, the red lines represent power lines, the blue lines represent ground lines, and the dotted lines represent the rows where the units can be placed;

[0071] The specific implementation of step S2 includes: to avoid excessive congestion of standard cells in subsequent processing, the network flow algorithm is used to diffuse the cells to ensure that the width of the cells in each row does not exceed the width of the row; the layout area is evenly divided into grids in the horizontal and vertical directions, and each grid constitutes a node in the network flow graph; in addition, two additional nodes are created, namely the super source node (N B ) and super sink nodes (N E ); Calculate the sum of the areas of the cells in each grid s C , and compare it with the grid area s G Compare; if s C >s G , then the grid is called the overflow grid and the overflow area s is recorded o ; if s C ≤s G , then the grid is called an idle grid and the remaining idle area s is recorded f ; For the overflow grid, set it to the source node N in the network flow s , and establish a line from N B to Ns The arc, the capacity and cost on the arc are set to s o and zero; for an idle grid, set it to target node N t , and establish a line from N t to N E The arc, the capacity and cost on the arc are set to s f and 0; and for the overflow grid, find the free grid adjacent to it and establish s to N t The arc, the capacity and cost on the arc are set to infinity and the displacement of the unit moving between the two grids respectively; for the established network flow graph, the strategy of unit movement in the grid can be obtained, and the unit is moved according to the strategy. The unit after movement c i The coordinates are

[0072] The specific implementation of step S3 includes: the legalization process is to eliminate the overlap between cells and minimize the total displacement of the standard cell as the optimization goal. In the previous step, the cell has been moved to the minimum in the vertical direction, that is, aligned with the matching power rail, so the displacement in the vertical direction can be ignored. The legalization problem is described as the following model (1):

[0073]

[0074] The above model is rewritten as the standard form of convex quadratic programming problem, namely:

[0075]

[0076] in, is an identity matrix, is a column vector whose components consist of the initial horizontal coordinates of the standard cells; any adjacent pair of standard cells should satisfy the inequality x j -x i ≥w i (x j ≥x i ), establish this inequality between all adjacent cells, and it can be written in matrix form Wx≥d, where A is a matrix containing only two elements -1 and 1 in each row, representing cell c i and c j The horizontal coordinate x j , x i , d is a column vector, where the corresponding component represents the left unit c i The width w i ; Then the number of rows of W and d is the number of constraints, and the number of columns of W is the total number of standard cells, that is, the sum of the number of single-row-height cells and the number of sub-cells into which multiple-row-height cells are split. R is also a matrix consisting of -1 and 1 in each row, where -1 represents a multiple of the row height unit c. i Subunit c i1 , 1 represents c i Subunit c i2 , and so on; x i2 -x i1 =0 guarantee c i The horizontal coordinates of the subunits are equal, so the constraint matrix Rx=0 can be obtained, where Figure 3 This is a simple example diagram of a mixed-size standard cell layout. The matrices W, R, and vector d constructed based on this position are shown below:

[0077] R=(0 -1 1 0), d=(w1 w2);

[0078] Using the Lagrange multiplier method, the equality constraints in the quadratic programming are added to the objective function, and (2) can be expressed as:

[0079]

[0080] Where λ is the Lagrange multiplier;

[0081] The specific implementation of step S4 is: using the Karush-Kuhn-Tucker (KKT) condition, model (3) can be written as the KKT equations with the following conditions:

[0082]

[0083] Rewrite equation (4) into the following form:

[0084]

[0085] make The problem then becomes finding a pair of non-negative and orthogonal solution vectors The following conditions are met:

[0086] w=Az+q≥0,z≥0and w T z≥0. (6)

[0087] Problem (6) is a linear complementarity problem, where

[0088] The specific implementation of step S5 is as follows: since the (2, 2) block of the system matrix A in the linear complementarity problem is 0, it is a semi-positive definite matrix; a perturbation is added to the (2, 2) block of the matrix, i.e., εI m , then the blocks of matrix A are:

[0089]

[0090] in is the identity matrix, let z = (|v|-v), w = (|v|+v), then (6) can be transformed into the following equivalent generalized absolute value equation:

[0091] (A+I)v-(AI)|v|=q. (7)

[0092] Let C = A + I, B = AI, then (7) can be restated as follows:

[0093] Cv-B|v|=q. (8)

[0094] The specific implementation of step S6 is as follows: let F(v) = Cv-B|v|-q, and let F(v) = 0; since F(v) is a piecewise linear vector function, it is not differentiable and the Newton iteration method cannot be directly applied to solve this equation; therefore, based on the subgradient of the component of |v|, the generalized Jacobian of |v| is used. To obtain the generalized absolute value equation

[0095] Approximate solution of (8); It can be represented by a diagonal matrix D(v), where and

[0096]

[0097] The Newton iteration method is defined as follows:

[0098] v k+1 =v k -F′(v k ) -1 F(v k ), k=0, 1, 2,..., (10)

[0099] As long as F(v k )'s Jacobian matrix F'(v k ) exists and is reversible, we can use (10) to solve F(v), that is,

[0100] v k+1 =v k -(C-BD(v k )) -1 (Cv k -B|v k |-q). (11)

[0101] Multiply both sides of the above formula (11) by (C-BD(v k )) can be obtained

[0102] (C-BD(v k ))v k+1 =(C-BD(v k ))v k -(Cv k -B|v k |-q). (12)

[0103] Since D(v k )v k =|v k |, after rearranging formula (12), we can get

[0104] (C-BD(v k ))v k+1 =q. (13)

[0105] Since C = A + I and B = AI, the linear complementarity problem equivalent to the legalization problem can be transformed into the following iterative format for solution:

[0106] v k+1 =((A+I)-(AI)D(v k )) -1 q. (14)

[0107] Given an arbitrary initial vector Compute v by iteratively solving the linear system k+1 The value of the absolute residual vector RES(v (k) ):=||z (k+1) -z (k) ||2 is less than or equal to a given constant, then it can be considered an iterative sequence Converges, and z (k) =(|v (k) |-v (k) ), k=0, 1, 2, ...; the specific solution process is as follows Figure 4 As shown; Figure 5 An example of solving a legalization problem by converting it into a generalized absolute value equation and applying the Newton iteration method is given. The horizontal axis represents the number of iterations and the vertical axis represents the two-norm of the absolute residual vector RES (v (k) ) value, the iterative convergence condition is RES(v (k) )≤10 -6 ;

[0108] The specific implementation of step S7 is as follows: sorting the x-coordinates of all sub-units of each multiple-row-height standard unit in ascending order, wherein the median is the x-coordinate of the multiple-row-height unit to be determined, and then placing the unit at the available position closest to the determined x-coordinate;

[0109] The specific implementation of step S8 is as follows: for a few standard cells that still overlap or exceed the right boundary of the layout area, traverse the standard cells from the upper right corner of the layout area in the order from right to left and from top to bottom. i If it exceeds the right boundary, its coordinates are set to Ww i , if unit c i with c i-1 If they overlap, c i-1 Set the coordinate to x i -w i-1 ; Since the movement of multiple-row-height cells may cause cells in adjacent rows to overlap, multiple-row-height cells that have already been moved in the previous row will not be moved again in the next row; then, traverse the standard cells again from left to right and from bottom to top according to the same rules. After this step, all cell overlaps can be eliminated.

[0110] The above description is merely an exemplary embodiment of the present invention and does not limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be included in the scope of patent protection of the present invention.

Claims

1. A mixed-size unit circuit layout design method based on Newton iteration method, characterized by: The steps include: S1: pre-processing the standard unit, dividing the multiple-row-height standard unit into multiple single-row-height standard sub-units; The specific implementation of step S1 includes: given a rectangular layout area of a chip, (0,0) and (W,H) are used to represent the coordinates of its lower left corner and upper right corner respectively; W represents the width of the layout area, and H represents the height of the layout area; the set of movable standard cells to be laid out is C = (c1, c2, ... c n ), where unit c i The initial lower left corner coordinate obtained from the global stage is The unit width and height are w i , h i , the coordinates after the legalization stage are (x i ,y i ) indicates; for multiple-row high standard units, they are represented as multiple sub-units, using (c i1 ,c i2 ,…c it ), where t means the height of the standard cell is t times the row height; All cells are an integer multiple of the row height. All standard cells are then aligned to the nearest row that matches their power line. Power and ground lines are staggered within the row. Cells with odd-numbered row heights have different power types at both ends, so they can be placed on any row as long as they do not exceed the layout area. Power type matching is achieved by flipping cells. Cells with even-numbered row heights have the same power type at both ends, so they need to be placed on the row that matches their power type. S2: Diffusion of standard cells based on network flow algorithm; S3: Formulate the mixed-size standard unit legalization problem as a quadratic programming mathematical model; S4: Convert the quadratic programming model into a linear complementarity problem; S5: Convert the linear complementarity problem into a generalized absolute value equation; The specific implementation of step S5 is as follows: since the (2,2) block of the system matrix A in the linear complementarity problem is 0, it is a semi-positive definite matrix; add a perturbation to the (2,2) block of the matrix, i.e., εI m , then the blocks of matrix A are: in is the identity matrix, let z = (|v|-v), w = (|v|+v), then (6) can be transformed into the following equivalent generalized absolute value equation: (A+I)v-(AI)|v|=q; (7) Let C = A + I, B = AI, then (7) can be restated as follows: Cv-B|v|=q;(8) S6: Solve the generalized absolute value equation using Newton's iteration method; The specific implementation of step S6 is as follows: let F(v) = Cv-B|v|-q, and let F(v) = 0; since F(v) is a piecewise linear vector function, it is not differentiable and the Newton iteration method cannot be directly applied to solve this equation. Therefore, based on the subgradient of the component of |v|, the generalized Jacobian of |v| is used. To obtain the approximate solution of the generalized absolute value equation (8); It can be represented by a diagonal matrix D(v), where and The Newton iteration method is defined as follows: v k+1 =v k -F′(v k ) -1 F(v k ),k=0,1,2,…,(10) As long as F(v k )'s Jacobian matrix F'(v k ) exists and is reversible, we can use (10) to solve F(v), that is, v k+1 =v k -(C-BD(v k )) -1 (Cv k -B|v k |-q);(11) Multiply both sides of the above formula (11) by (C-BD(v k )) can be obtained (C-BD(v k ))v k+1 =(C-BD(v k ))v k -(Cv k -B|v k |-q);(12) Since D(v k )v k =|v k |, after rearranging formula (12), we can get (C-BD(v k ))v k+1 =q;(13) Since C = A + I and B = AI, the linear complementarity problem equivalent to the legalization problem can be solved by converting it into the following iterative format: v k+1 =((A+I)-(A-I)D(v k )) -1 q;(14) Given an arbitrary initial vector Compute v by iteratively solving the linear system k+1 The value of the absolute residual vector RES(v (k) ):=||Cv (k) -B|v (k) |-q||2 is less than or equal to a given constant, then it can be considered an iterative sequence Converges, and z (k) =(|v (k) |-v (k) ), k=0,1,2,…; S7: unify the x-coordinates of the sub-units divided into the multiple-row height standard unit and align them to the available positions in the row; S8: Legalize the remaining illegal units.

2. The mixed-size unit circuit layout design method based on Newton iteration method according to claim 1, characterized in that: The specific implementation of step S2 includes: to avoid excessive crowding of standard cells in subsequent processing, the cells are diffused using the network flow algorithm to ensure that the cell width in each row does not exceed the width of the row; the layout area is evenly divided into grids in the horizontal and vertical directions, and each grid constitutes a node in the network flow graph; in addition, two additional nodes are created, namely the super source node (N B ) and super sink nodes (N E ); Calculate the sum of the areas of the cells in each grid s C , and compare it with the grid area s G Compare; if s C >s G , then the grid is called the overflow grid and the overflow area s is recorded o ; if s C ≤s G , then the grid is called an idle grid and the remaining idle area s is recorded f ; For the overflow grid, set it to the source node N in the network flow s , and establish a line from N B to N s The arc, the capacity and cost on the arc are set to s o and zero; for an idle grid, set it to target node N t , and establish a line from N t to N E The arc, the capacity and cost on the arc are set to s f and 0; and for the overflow grid, find the free grid adjacent to it and establish s to N t The arc, the capacity and cost on the arc are set to infinity and the displacement of the unit moving between the two grids respectively; for the established network flow graph, the strategy of unit movement in the grid can be obtained, and the unit is moved according to the strategy. The unit after movement c i The coordinates are 3. The mixed-size unit circuit layout design method based on Newton iteration method according to claim 2, characterized in that: The specific implementation of step S3 includes: the legalization process is to eliminate the overlap between cells and minimize the total displacement of the standard cell as the optimization goal. In the previous step, the cell has been moved to the minimum in the vertical direction, that is, aligned with the matching power rail, so the displacement in the vertical direction can be ignored. The legalization problem is described as the following model (1): The above model is rewritten as the standard form of convex quadratic programming problem, namely: in, is an identity matrix, is a column vector whose components consist of the initial horizontal coordinates of the standard cells; any adjacent pair of standard cells should satisfy the inequality x j -x i ≥w i (x j ≥x i ), establish this inequality between all adjacent cells, and it can be written in matrix form Wx≥d, where W is a matrix containing only two elements -1 and 1 in each row, representing the cell c i and c j The horizontal coordinate x j ,x i , d is a column vector, where the corresponding component represents the left unit c i The width w i ; Then the number of rows of W and d is the number of constraints, and the number of columns of W is the total number of standard cells, that is, the sum of the number of single-row-height cells and the number of sub-cells into which multiple-row-height cells are split. R is also a matrix consisting of -1 and 1 in each row, where -1 represents a multiple of the row height unit c. i Subunit c i1 , 1 represents c i Subunit c i2 , and so on; x i2 -x i1 =0 guarantee c i The horizontal coordinates of the subunits are equal, so the constraint matrix Rx=0 can be obtained, where Using a simple example diagram of a mixed-size standard cell layout, the matrices W, R, and vector d constructed based on this location are shown below: R=(0 -1 1 0), d=(w1 w2); Using the Lagrange multiplier method, the equality constraints in the quadratic programming are added to the objective function, and (2) can be expressed as: Here, λ is the Lagrange multiplier.

4. A mixed-size unit circuit layout design method based on Newton iteration method according to claim 3, characterized in that: The specific implementation of step S4 is: using the Karush-Kuhn-Tucker (KKT) condition, model (3) can be written as the KKT equations with the following conditions: Rewrite equation (4) into the following form: make The problem then becomes finding a pair of non-negative and orthogonal solution vectors The following conditions are met: <h2 style=";text-align:left;direction:ltr">w = Az + q ≥ 0, z ≥ 0 and w<h2 style=";text-align:left;direction:ltr"> T <h2 style=";text-align:left;direction:ltr"> z≥0;(6) Problem (6) is a linear complementarity problem, where 5. The method for designing a mixed-size unit circuit layout based on Newton's iteration method according to claim 4, characterized in that: The specific implementation method of step S7 is: sort the x-coordinates of all subunits of each multiple row height standard unit in ascending order, the median is the x-coordinate of the multiple row height unit, and then place the unit at the nearest available position to the obtained x-coordinate.

6. A mixed-size unit circuit layout design method based on Newton iteration method according to claim 5, characterized in that: The specific implementation of step S8 is as follows: for a few standard cells that still overlap or exceed the right boundary of the layout area, traverse the standard cells from the upper right corner of the layout area in the order from right to left and from top to bottom. i If it exceeds the right boundary, its coordinates are set to Ww i , if unit c i with c i-1 If they overlap, c i-1 Set the coordinate to x i -w i-1 ; Since the movement of multiple-row-height cells may cause cells in adjacent rows to overlap, the multiple-row-height cells that have already been moved in the previous row will not be moved again in the next row. Then, the standard cells are traversed again from left to right and from bottom to top according to the same rules. After this step, all cell overlaps can be eliminated.

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