A manufacturing method and structure of an IGBT device

Abstract

The present invention provides a manufacturing method and structure of an IGBT device. The method includes: providing a substrate, the substrate including an active region, a transition region and a terminal region, and including opposite first and second main surfaces; performing a first ion implantation on the first main surfaces of the transition region and the terminal region to form a doped terminal layer spanning the transition region and the terminal region, and performing a second ion implantation on the edge of the terminal region to form a cutoff ring, and then performing a thermal process push treatment; etching the first main surface of the terminal region to form a trench communicating the doped terminal layer and the cutoff ring, and forming a field oxide layer in the trench; performing a second ion implantation on the first main surface to form a carrier storage doped region, and then performing a thermal process push treatment; forming a front structure and a back structure. When manufacturing the carrier storage doped region in the active region in the present invention, implantation can be performed without a mask plate, thereby saving manufacturing costs and at the same time avoiding a great influence of the carrier storage layer on the breakdown voltage of the IGBT.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a manufacturing method and structure of an IGBT device. Background Art

[0002] As a hybrid power device, the IGBT has the characteristics of MOS structure input and bipolar structure output. Therefore, it has both the advantages of high input impedance of MOSFET, small driving circuit power, simple driving, fast switching speed, and small switching loss, and the advantages of large current density of bipolar power transistor, strong current handling ability, and low on-state saturation voltage drop. After nearly four decades of development, the IGBT has become the mainstream power device in power electronic systems. With the continuous development of IGBT technology, undoubtedly higher requirements are put forward for the performance and cost of IGBTs.

[0003] Currently, the terminals adopted by IGBTs are mainly field ring field plate terminals. This terminal has simple process and high reliability and is widely used. However, the utilization rate of this terminal is low, and the highest can only reach 70%-80%. With the increasingly fierce competition in the IGBT market, terminals with higher utilization rates are gradually adopted, such as junction terminal extension (JTE) terminals and vertical laterally diffused (VLD) terminals. The utilization rate of this terminal can reach more than 90%. Compared with the field ring field plate terminal, the same breakdown voltage can adopt a smaller-sized terminal, that is, the total size of the IGBT Die is reduced, thereby reducing the manufacturing cost of IGBTs.

[0004] By adding a carrier storage layer (CS) on the front of the IGBT, it has become a common method to reduce the on-state voltage drop of the IGBT, such as the CSTBT of Mitsubishi Corporation. The carrier storage layer is generally realized by phosphorus implantation on the front of the IGBT, and the implantation dose is generally 1e12 - 2e13 cm -2 , and the implantation dose of the field ring field plate terminal is generally 1e14 - 2e15 cm -2 , the implantation dose of the CS layer and the terminal implantation dose differ by two orders of magnitude. Therefore, the implantation dose of the CS layer has almost no influence on the doping concentration in the transition region of the IGBT. The terminal region is blocked by a thick oxide layer. Therefore, for an IGBT with a field ring field plate terminal structure, the CS layer can be directly implanted without a mask. However, the implantation dose of the JTE or VLD terminal is generally 1e12 - 2e13 cm -2, equivalent to the CS injection dose. Although the terminal region is also shielded by a thick oxide layer, the doping concentration in the transition region is significantly affected by the CS injection dose, and even the transition region of the IGBT may be inverted into an N-type. Experiments have shown that for IGBTs with JTE or VLD terminal structures, if CS is uniformly injected, the breakdown voltage of the IGBT device will be significantly reduced. To avoid the influence of the CS injection dose on the doping concentration in the IGBT transition region, for IGBTs with JTE or VLD terminal structures, a CS mask is generally added to cover the transition region and the terminal region during CS injection, so that CS is only injected into the active region. In this way, an additional CS mask is required during CS injection, increasing the manufacturing cost of the IGBT.

[0005] Therefore, for IGBTs with JTE or VLD terminal structures, how to inject phosphorus into the CS layer without using a CS mask and without affecting the breakdown voltage of the IGBT is an issue that needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a manufacturing method and structure for an IGBT device, which is used to solve the problem that an additional mask is required during the carrier storage doping region injection in the IGBT process with JTE or VLD terminal structures, resulting in an increase in the manufacturing cost of the IGBT.

[0007] To achieve the above purpose and other related purposes, the present invention provides a manufacturing method for an IGBT device, and the manufacturing method at least includes:

[0008] 1) Provide a substrate, the substrate includes an active region, a transition region and a terminal region, and the active region, the transition region and the terminal region all include opposite first main surfaces and second main surfaces;

[0009] 2) Perform a first ion implantation on the first main surfaces of the transition region and the terminal region to form a doped terminal layer spanning the transition region and the terminal region, and perform a second ion implantation on the edge of the terminal region to form a cutoff ring, and then perform a thermal process push treatment;

[0010] 3) Perform an etching process on the first main surface of the terminal region to form a trench connecting the doped terminal layer and the cutoff ring on the first main surface, and form a field oxide layer in the trench;

[0011] 4) Perform a second ion implantation on the first main surface to form a carrier storage doping region on the first main surface, and then perform a thermal process push treatment;

[0012] 5) Perform a front process on the first main surface and a back process on the second main surface to form a front structure and a back structure respectively, and complete the manufacturing of the IGBT device.

[0013] Optionally, in step 2), the first ion implantation dose is between 1e14 cm -2 ~2e15 cm -2 and the implantation energy is between 60 keV and 200 keV; the second ion implantation dose is between 1e15 cm -2 ~5e15 cm -2 and the implantation energy is between 60 keV and 200 keV.

[0014] Optionally, in step 2), the temperature of the thermal process promotion treatment is between 1100 °C and 1200 °C, and the time is between 10 min and 60 min.

[0015] Optionally, in step 3), the etching depth of the trench is between 0.5 μm and 1 μm.

[0016] Optionally, in step 3), dry etching process is used to etch on the first main surface of the terminal region to form a trench connecting the doped terminal layer and the cutoff ring, and the depth of each part of the trench is the same.

[0017] Optionally, in step 3), dry etching process is first used and then wet etching process is used to etch on the first main surface of the terminal region to form a trench connecting the doped terminal layer and the cutoff ring, and the depth of the trench gradually becomes deeper from the doped terminal layer to the cutoff ring direction.

[0018] Optionally, in step 3), the thickness of the field oxide layer is between 1.5 μm and 2.5 μm.

[0019] Optionally, in step 4), the implantation dose of the second ion implantation is between 1e12 cm -2 ~2e13 cm -2 and the implantation energy is between 60 keV and 200 keV.

[0020] Optionally, in step 4), the temperature of the thermal process promotion treatment is between 1100 °C and 1250 °C, and the time is between 200 min and 400 min.

[0021] The present invention also provides an IGBT device structure, which at least includes: a substrate, the substrate includes an active region, a transition region and a termination region, and the active region, the transition region and the termination region all include opposite first main surfaces and second main surfaces; a doped termination layer and a cutoff ring, the doped termination layer straddles the transition region and the termination region, and the cutoff ring is formed at the edge of the termination region; a trench, which is connected between the doped termination layer and the cutoff ring; a field oxide layer, which is formed in the trench; a carrier storage doped region, which is formed in the first main surface of the active region and the transition region; a front structure, which is formed on the first main surface; and a back structure, which is formed on the second main surface.

[0022] Optionally, the first ion doping concentration included in the doped termination layer of the transition region is between 1e13 cm -2 -1e16 cm -2 .

[0023] Optionally, the depth of the trench is between 0.5 μm and 1 μm.

[0024] Optionally, the depth of each part of the trench is the same or the depth of the trench gradually becomes deeper from the doped termination layer to the cutoff ring direction.

[0025] Optionally, the thickness of the field oxide layer is between 1.5 μm and 2.5 μm.

[0026] As described above, the manufacturing method and structure of the IGBT device of the present invention have the following beneficial effects:

[0027] By controlling the ion implantation dose of the doped termination layer (JTE or VLD termination) in the transition region and the termination region, the time of the thermal process advancement treatment before trench etching, and the trench etching depth, the doping concentration of the doped termination layer in the termination region is adjusted, so that the IGBT with a JTE or VLD termination structure can directly perform the general implantation of the carrier storage doped region without a mask during the ion implantation of the carrier storage doped region in the active region, without affecting the doping concentration of the transition region, thereby avoiding affecting the breakdown voltage value of the IGBT. At the same time, the height difference on the chip surface caused by the thick oxide layer in the termination region is reduced, which is more beneficial to the subsequent lithography process in IGBT manufacturing.

[0028] The process manufacturing method of the present invention can perform the general implantation of the carrier storage doped region for IGBTs with a JTE or VLD termination structure. This step does not require a mask, so a mask can be saved, saving manufacturing costs. In addition, the manufacturing method of the IGBT device of the present invention is compatible with the current IGBT process. Description of the Drawings

[0029] Figures 1 to 5cThe structural schematic diagram presented by the manufacturing method steps of the IGBT device according to the embodiment of the present invention is shown, where Figure 5a , Figure 5b , Figure 5c The structural schematic diagram of the IGBT device according to the embodiment of the present invention is shown.

[0030] Element number description

[0031] 101 Substrate

[0032] 102 Doped terminal layer

[0033] 103 Cutoff ring

[0034] 104 Trench

[0035] 105 Field oxide layer

[0036] 106 Carrier storage doped region

[0037] 107 Gate dielectric layer

[0038] 108 Polysilicon layer

[0039] 109 Source doped region

[0040] 110 Body doped region

[0041] 111 Insulating layer

[0042] 112 Front metal layer

[0043] 113 Collector region

[0044] 114 Hydrogen ion doped region

[0045] 115 Back metal Detailed implementation manners

[0046] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be locally enlarged in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0048] For ease of description, spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "on" etc. may be used herein to describe the relationship of one element or feature shown in the drawings with other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0049] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0050] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0051] Embodiment 1

[0052] This embodiment provides a method for manufacturing an IGBT device, and the manufacturing method at least includes the following steps:

[0053] As Figure 1 shown, first, step 1) is carried out, providing a substrate 101, where the substrate 101 includes an active region, a transition region, and a terminal region, and the active region, the transition region, and the terminal region all include opposite first main surfaces and second main surfaces.

[0054] The substrate 101 may be a single-crystalline silicon substrate. In some embodiments, the substrate 101 may also be made of other materials, such as but not limited to silicon germanium or germanium. In other embodiments, the substrate 101 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The doping concentration and thickness of the substrate 101 can be set according to the performance of the IGBT device, such as breakdown voltage.

[0055] As Figure 1 shown, then step 2) is carried out, performing a first ion implantation on the first main surfaces of the transition region and the terminal region to form a doped terminal layer 102 spanning the transition region and the terminal region, and performing a second ion implantation on the edge of the terminal region to form a cutoff ring 103, and then performing a thermal process push treatment.

[0056] As an example, first form a pattern mask on the first major surface of the substrate 101. The pattern mask exposes the transition region and the regions of the terminal region where the doped terminal layer 102 (JTE or VLD terminal) is to be formed. Then, perform a first ion implantation on the first major surface. The dose of the first ion implantation is between 1e14 cm -2 ~2e15 cm -2 and the implantation energy is between 60 keV and 200 keV. In a specific embodiment, the dose of the first ion implantation is 1e14 cm -2 , and the implantation energy is 100 keV. In another specific embodiment, the dose of the first ion implantation is 2e15 cm -2 , and the implantation energy is 150 keV.

[0057] As an example, the dose of the second ion implantation is between 1e15 cm -2 ~5e15 cm -2 and the implantation energy is between 60 keV and 200 keV. In a specific embodiment, the dose of the second ion implantation is 2e15 cm -2 , and the second ion implantation energy is 100 keV. In another specific embodiment, the dose of the second ion implantation is 4e15 cm -2 , and the second ion implantation energy is 150 keV.

[0058] It should be noted that the first ion implantation can be P-type boron implantation, and the corresponding second ion implantation is N-type phosphorus implantation. Of course, the first ion implantation can also be N-type phosphorus implantation, and the corresponding second ion implantation is P-type boron implantation. In this embodiment, the IGBT device is realized based on an N-type doped silicon wafer substrate, so the first ion implantation is P-type boron implantation, and the corresponding second ion implantation is N-type phosphorus implantation.

[0059] As an example, the temperature of the thermal process promotion treatment is between 1100 °C and 1200 °C, and the time is between 10 min and 60 min. In a specific embodiment, the temperature of the thermal process promotion treatment is 1150 °C, and the time is 30 min. In another specific embodiment, the temperature of the thermal process promotion treatment is 1180 °C, and the time is 50 min.

[0060] Figure 1 The doped terminal layer 102 in

[0061] is formed after the first ion implantation and the thermal process promotion treatment. The doping concentration of the doped terminal layer 102 can be controlled by the first ion implantation and the thermal process promotion treatment. Figure 2a and Figure 3As shown, then perform step 3), etching the first main surface of the terminal region to form a trench 104 in the first main surface that connects the doped terminal layer 102 and the cutoff ring 103, and forming a field oxide layer 105 in the trench 104.

[0062] As an example, the etching depth of the trench 104 is between 0.5 μm and 1 μm. In a specific embodiment, the etching depth of the trench 104 is 0.6 μm. In another specific embodiment, the etching depth of the trench 104 is 0.8 μm.

[0063] As an example, as Figure 2a shown, a dry etching process can be used to etch the first main surface of the terminal region to form a trench 104 that connects the doped terminal layer 102 and the cutoff ring 103, and the depth of each part of the trench 104 is the same.

[0064] In another specific embodiment, as Figure 2b and 2c shown, a dry etching process can be used first and then a wet etching process can be used to etch the first main surface of the terminal region to form a trench 104 that connects the doped terminal layer 102 and the cutoff ring 103, and the depth of the trench 104 gradually becomes deeper from the doped terminal layer to the cutoff ring direction. Specifically, as Figure 2b shown, multiple trenches 104 are etched and formed by using a dry etching process first, and the width of each trench 104 gradually becomes wider from the doped terminal layer 102 to the cutoff ring 103 direction. Due to the loading effect of dry etching, the wider the trench 104, the deeper the depth of the trench 104. Then, the separate trenches 104 are connected into one trench through isotropic wet etching, as Figure 2c shown.

[0065] By etching away part of the doped terminal layer 102 in the terminal region, the remaining doped ions in the doped terminal layer 102 can meet the doping concentration requirements of the terminal region after subsequent thermal process advancement. At the same time, the high concentration of the doped terminal layer 102 in the transition region can ensure that the transition region is not inverted during the subsequent general implantation of the carrier storage doping region 106. The breakdown voltage of the IGBT device is hardly affected, and the mask plate can be omitted for direct general implantation, greatly reducing the manufacturing cost.

[0066] As an example, as Figure 3As shown, a field oxide layer 105 can be formed through a furnace tube, and the thickness of the field oxide layer 105 is between 1.5 μm and 2.5 μm. In a specific embodiment, the thickness of the field oxide layer 105 is 2 μm. In another specific embodiment, the thickness of the field oxide layer 105 is 2.3 μm. The field oxide layer 105 can be used to shield the terminal region during subsequent general implantation of the carrier storage doping region 106.

[0067] As Figure 4 shown, then step 4) is carried out, and a second ion implantation is performed on the first main surface to form a carrier storage doping region 106 on the first main surface, and then a thermal process promotion treatment is carried out.

[0068] Since the field oxide layer 105 is formed on the first main surface of the terminal region and has a blocking effect during implantation, the carrier storage doping region 106 is only formed in the first main surface of the active region and the transition region.

[0069] As an example, the implantation dose of the second ion implantation is between 1e12 cm -2 ~2e13 cm -2 and the implantation energy is between 60 keV and 200 keV. In a specific embodiment, the implantation dose of the second ion implantation is 1e12 cm -2 , and the implantation energy is 100 keV. In another specific embodiment, the implantation dose of the second ion implantation is 2e12 cm -2 , and the implantation energy is 150 keV. In this embodiment, the second ion implantation is an N-type phosphorus ion implantation. The carrier storage doping region 106 is mainly formed in the active region, and the carrier storage doping region 106 formed in the transition region will not have a great impact on the doping concentration of the entire transition region.

[0070] As an example, the temperature of the thermal process promotion treatment is between 1100 °C and 1250 °C, and the time is between 200 min and 400 min. In a specific embodiment, the temperature of the thermal process promotion treatment is 1150 °C and the time is 250 min. In another specific embodiment, the temperature of the thermal process promotion treatment is 1200 °C and the time is 300 min. This thermal process promotion treatment makes the depth of the doped terminal layer 102 in the terminal region deeper, which can meet the doping concentration and depth requirements of the terminal region.

[0071] In view of the above, it can be seen that through etching and thermal process promotion treatment, the doping concentrations of the doped terminal layer 102 in the transition region and the terminal region can be made different, which can not only ensure the concentration requirements of the terminal region, but also greatly reduce the impact of the implantation of the carrier storage doping region 106 in the active region on the concentration of the transition region.

[0072] After the thermal process is advanced, a planarization process such as chemical mechanical polishing can be selected to make the top of the field oxide layer flush with the first main surface of the substrate. For the convenience of illustration, Figure 3 and Figure 4 both show the situation where the top of the field oxide layer is flush with the first main surface of the substrate.

[0073] As Figure 5a shown, finally, step 5) is performed. A front process is performed on the first main surface, and a back process is performed on the second main surface to form a front structure and a back structure respectively, completing the manufacture of the IGBT device.

[0074] Specifically, the front structure includes a trench gate structure disposed on the first main surface of the active region, a source doping region 109, a body doping region 110 disposed on the first main surfaces of the active region and the transition region, an insulating layer 111 and a front metal layer 112 disposed on the first main surface. The trench gate structure penetrates through the body doping region 110 to the substrate 101. The trench gate structure includes a trench extending below the body doping region 110, a gate dielectric layer 107 on the sidewall of the trench, and a polysilicon layer 108 filled in the trench. The source doping region 109 is disposed in the body doping region 110 and on the side of the trench gate structure. The body doping region 110 is disposed above the carrier storage doping region 106. The front metal layer 112 is connected to the source doping region 109 and the body doping region 110.

[0075] In this embodiment, the body doping region 110 is P-type doped, and the source doping region 109 is N-type doped.

[0076] The front metal layer 112 includes an emitter metal layer and a gate metal layer. The emitter metal is connected to the source doping region 109 and the body doping region 110 of the active region through a via, and is also connected to the body doping region 110 of the transition region through a via. The gate metal layer is connected to the polysilicon layer 108 in the trench gate structure. In this embodiment, the gate metal layer is disposed above the field oxide layer 105 in the terminal region to save the area of the active region and facilitate the electrical lead-out of the trench gate structure.

[0077] As an example, the front metal layer 112 can be AlCu or AlSiCu.

[0078] The back structure includes a collector region 113, a hydrogen ion doping region 114, and a back metal 115 formed on the second main surface. The collector region 113 can be a conductive doping ion, for example, it can be boron or a compound of boron.

[0079] As an example, the hydrogen ion doped region 114 has a plurality of hydrogen ion doped layers with different hydrogen ion doping concentrations, and the hydrogen ion doping concentrations of the plurality of hydrogen ion doped layers gradually decrease in the direction from the second main surface to the first main surface. The hydrogen ion implantation dose contained in the hydrogen ion doped region 114 is between 5e11 and 5e16 cm -2 ², and the hydrogen ion implantation energy is between 200 KeV and 1.5 MeV. Specifically, the hydrogen ion doped region 114 has 1 to 4 hydrogen ion doped layers with different hydrogen ion doping concentrations. In this embodiment, by adjusting the dose and energy of each hydrogen ion implantation, hydrogen ion doped layers with multiple different doping peaks can be formed in the substrate 101 after annealing. For example, in this embodiment, the hydrogen ion doped region 114 has four different doping peaks 141, 142, 143, and 144.

[0080] As an example, the back metal 115 can be an Al / Ti / Ni / Ag metal stack.

[0081] It should be noted that Figure 5a The IGBT device structure shown is the one where the field oxide layer 105 has undergone a planarization process. Figure 5b The IGBT device structure shown is the one where the thickness of the field oxide layer varies at different locations. Figure 5c The IGBT device structure shown is the one where the field oxide layer 105 has not undergone a planarization process.

[0082] Embodiment 2

[0083] As Figure 5a shown, the present invention also provides an IGBT device, which can be manufactured by the manufacturing method described in Embodiment 1. The device at least includes: a substrate 101, the substrate 101 includes an active region, a transition region, and a termination region, and the active region, the transition region, and the termination region all include opposite first main surfaces and second main surfaces; a doped termination layer 102 and a cutoff ring 103, the doped termination layer 102 straddles the transition region and the termination region, and the cutoff ring 103 is formed at the edge of the termination region; a trench 104, communicating between the doped termination layer 102 and the cutoff ring 103; a field oxide layer 105, formed in the trench 104; a carrier storage doped region 106, formed in the first main surface of the active region and the transition region; a front structure, formed on the first main surface; and a back structure, formed on the second main surface.

[0084] For example, the substrate 101 may be a single-crystalline silicon substrate. In some embodiments, the substrate may also be made of other materials, such as but not limited to silicon germanium or germanium. In other embodiments, the substrate 101 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The doping concentration and thickness of the substrate 101 may be set according to the performance of the IGBT device, such as breakdown voltage.

[0085] As an example, the first ion doping concentration included in the doping termination layer of the transition region is between 1e13 cm -2 -1e16 cm -2 .

[0086] As an example, the depth of the trench 104 is between 0.5 μm and 1 μm. In a specific embodiment, the etching depth of the trench 104 is 0.6 μm. In another specific embodiment, the etching depth of the trench 104 is 0.8 μm.

[0087] As an example, the depth of each part of the trench 104 is the same or the depth of the trench gradually becomes deeper from the doping termination layer 102 to the cutoff ring 103 direction. As Figure 5a shown is the structural diagram with the same depth of the trench 04; as Figure 5b shown is the structural diagram with the trench 104 gradually becoming deeper.

[0088] As an example, the thickness of the field oxide layer 105 is between 1.5 μm and 2.5 μm. In a specific embodiment, the thickness of the field oxide layer 105 is 2 μm. In another specific embodiment, the thickness of the field oxide layer 105 is 2.3 μm. The field oxide layer 105 can be used to shield the terminal region during the general implantation of the carrier storage doping region 106. As Figure 5c shown is the structural schematic diagram without planarization of the field oxide layer 105.

[0089] Specifically, the front structure includes a trench gate structure disposed on the first main surface of the active region, a source doping region 109, a body doping region 110 disposed on the first main surfaces of the active region and the transition region, an insulating layer 111 and a front metal layer 112 disposed on the first main surface. The trench gate structure penetrates through the body doping region 110 to the substrate 101. The trench gate structure includes a trench extending below the body doping region 110, a gate dielectric layer 107 located on the sidewall of the trench, and a polysilicon layer 108 filled in the trench. The source doping region 109 is disposed in the body doping region 110 and on the side of the trench gate structure. The body doping region 110 is disposed above the carrier storage doping region 106. The front metal layer 112 is connected to the source doping region 109 and the body doping region 110.

[0090] In this embodiment, the body doping region 110 is P-type doped, and the source doping region 109 is N-type doped.

[0091] The front metal layer 112 includes an emitter metal layer and a gate metal layer. The emitter metal is connected to the source doping region 109 and the body doping region 110 of the active region through vias, and is also connected to the body doping region 110 of the transition region through vias. The gate metal layer is connected to the polysilicon layer 108 in the trench gate structure. In this embodiment, the gate metal layer is disposed above the field oxide layer 105 in the terminal region to save the area of the active region and facilitate the electrical lead-out of the trench gate structure.

[0092] As an example, the front metal layer 112 can be AlCu or AlSiCu.

[0093] The back structure includes a collector region 113, a hydrogen ion doping region 114, and a back metal 115 formed on the second main surface. The collector region 113 can be a conductive doping ion, for example, it can be boron or a boron compound.

[0094] As an example, the hydrogen ion doping region 114 has a plurality of hydrogen ion doping layers with different hydrogen ion doping concentrations. The hydrogen ion doping concentrations of the plurality of hydrogen ion doping layers gradually decrease in the direction from the second main surface to the first main surface. The hydrogen ion implantation dose included in the hydrogen ion doping region 114 is between 5e11 and 5e16 cm -2 between, and the hydrogen ion implantation energy is between 200 KeV and 1.5 MeV. Specifically, the hydrogen ion doping region 114 has 1 to 4 hydrogen ion doping layers with different hydrogen ion doping concentrations. In this embodiment, by adjusting the dose and energy of each hydrogen ion implantation, hydrogen ion doping layers with multiple different doping peaks can be formed in the substrate 101 after annealing. For example, in this embodiment, the hydrogen ion doping region 114 has four different doping peaks 141, 142, 143, and 144.

[0095] As an example, the back metal 115 can be an Al / Ti / Ni / Ag metal stack.

[0096] In summary, the present invention provides a manufacturing method and structure for an IGBT device. By controlling the ion implantation dose of the doped terminal layer (JTE or VLD terminal) in the transition region and the terminal region, the time of the thermal process advancement treatment before trench etching, and the trench etching depth, the doping concentration of the doped terminal layer in the terminal region is adjusted, so that the IGBT with a JTE or VLD terminal structure can directly perform the general implantation of the carrier storage doping region without a mask during the ion implantation of the carrier storage doping region in the active region, without significantly affecting the doping concentration of the transition region, thereby avoiding affecting the breakdown voltage of the IGBT.

[0097] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0098] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of an IGBT device, characterized in that, The manufacturing method at least includes: 1) Providing a substrate, the substrate including an active region, a transition region, and a termination region, the active region, the transition region, and the termination region all including opposite first major surfaces and second major surfaces; 2) Performing a first ion implantation on the first major surfaces of the transition region and the termination region to form a doped termination layer spanning the transition region and the termination region, and performing a second ion implantation on the edge of the termination region to form a cutoff ring, and then performing a thermal process push treatment; 3) Performing an etching process on the first major surface of the termination region to form a trench connecting the doped termination layer and the cutoff ring in the first major surface, and forming a field oxide layer in the trench, the etching depth of the trench being between 0.5 μm and 1 μm; 4) Performing a second ion implantation on the first major surface to form a carrier storage doped region in the first major surface, and then performing a thermal process push treatment; 5) Performing a front process on the first major surface and a back process on the second major surface to form a front structure and a back structure respectively, completing the manufacturing of the IGBT device; The first ion implantation dose is between 1e14 cm -2 ~ 2e15 cm -2 and the implantation energy is between 60 keV and 200 keV; the second ion implantation dose is between 1e15 cm -2 ~ 5e15 cm -2 and the implantation energy is between 60 keV and 200 keV; In the step 4), the implantation dose of the second ion implantation ranges from 1e12 cm -2 to 2e13 cm -2 , and the implantation energy ranges from 60 keV to 200 keV.

2. The manufacturing method of the IGBT device according to claim 1, characterized in that: In the step 2), the temperature of the thermal process push treatment is between 1100 °C and 1200 °C, and the time is between 10 min and 60 min.

3. The manufacturing method of the IGBT device according to claim 1, characterized in that: In the step 3), a dry etching process is used to etch the first major surface of the termination region to form a trench connecting the doped termination layer and the cutoff ring, and the depth of each part of the trench is consistent.

4. The manufacturing method of the IGBT device according to claim 1, characterized in that: In the step 3), first a dry etching process and then a wet etching process are used to etch the first major surface of the termination region to form a trench connecting the doped termination layer and the cutoff ring, and the depth of the trench gradually becomes deeper from the doped termination layer towards the cutoff ring.

5. The manufacturing method of the IGBT device according to claim 1, characterized in that: In the step 3), the thickness of the field oxide layer is between 1.5 μm and 2.5 μm.

6. The manufacturing method of the IGBT device according to claim 1, wherein: In the step 4), the temperature of the thermal process push treatment is between 1100 °C and 1250 °C, and the time is between 200 min and 400 min.

7. An IGBT device structure prepared by the manufacturing method of the IGBT device according to any one of claims 1 to 6, characterized in that, The IGBT device structure at least includes: A substrate, the substrate including an active region, a transition region, and a termination region, the active region, the transition region, and the termination region all including opposite first major surfaces and second major surfaces; A doped termination layer and a cutoff ring, the doped termination layer spanning the transition region and the termination region, the cutoff ring being formed at the edge of the termination region; A trench, connecting between the doped termination layer and the cutoff ring; A field oxide layer, formed in the trench; A carrier storage doped region, formed in the first major surface of the active region and the transition region; A front structure, formed on the first major surface; A back structure, formed on the second major surface.

8. The IGBT device structure according to claim 7, characterized in that: The depth of each part of the trench is consistent or the depth of the trench gradually becomes deeper from the doped termination layer towards the cutoff ring.

9. The IGBT device structure according to claim 7, characterized in that: The thickness of the field oxide layer is between 1.5 μm and 2.5 μm.

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