Methods and systems for improving power delivery and signal transmission in stacked semiconductor devices.

Abstract

This invention relates to methods and systems for improving power delivery and transmission in stacked semiconductor devices. Semiconductor die assemblies comprising stacked semiconductor dies and associated systems and methods are disclosed herein, the stacked semiconductor dies having parallel-plate capacitors formed between adjacent pairs of semiconductor dies in the stack. In one embodiment, the semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked above the first semiconductor die. The first semiconductor die includes an upper surface on which a first capacitor plate is formed, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and on which a second capacitor plate is formed. A dielectric material is at least partially formed between the first and second capacitor plates. The first capacitor plate, the second capacitor plate, and the dielectric material together form a capacitor that locally stores charge within the stack and is accessible by the first and / or second semiconductor die.

Description

[0001] Information related to divisional application

[0002] This invention is a divisional application of Chinese Patent Application No. 201880054639.4, filed on June 4, 2018, entitled "Method and System for Improving Power Delivery and Transmission in Stacked Semiconductor Devices". Technical Field

[0003] This invention generally relates to stacked semiconductor devices. Several embodiments of this invention involve improving power delivery to stacked semiconductor devices by forming capacitors between adjacent semiconductor dies in a stack. Background Technology

[0004] Microelectronic devices (such as memory devices, microprocessors, and light-emitting diodes) typically comprise one or more semiconductor dies mounted to a substrate and encapsulated in a protective covering. These semiconductor dies contain functional features such as memory cells, processor circuitry, interconnect circuitry, etc. Semiconductor die manufacturers face increasing pressure to reduce the volume occupied by semiconductor dies while increasing capacity and / or the speed of the resulting encapsulated assemblies. To meet these demands, semiconductor die manufacturers typically stack multiple semiconductor dies vertically on top of each other to increase the capacity or performance of microelectronic devices within a limited volume on the circuit board or other components to which the semiconductor dies are mounted. In some semiconductor die stacks, through-silicon vias (TSVs) are used to electrically interconnect the semiconductor dies. TSVs allow semiconductor dies to be stacked close to each other, with adjacent semiconductor dies spaced only by a relatively small vertical distance. This, along with the relatively low inductance of TSVs, enables higher data transfer rates. Furthermore, because the dies are stacked vertically, the total area occupied by the stack corresponds to the area occupied by the largest die in the stack.

[0005] However, one problem with semiconductor die stacking is power delivery. For example, when semiconductor dies perform high-power operations, the current drawn from the dies in the stack can be enormous, which can lead to poor power delivery to, for example, the topmost die in the stack. Conventional methods for improving power delivery in semiconductor die stacks involve increasing the TSV count of each die in the stack to reduce the resistance of the power network. However, increasing the TSV count of a die typically requires increasing the size of the die. Therefore, there is still a need in this field for methods and systems to improve power delivery in semiconductor die stacks. Summary of the Invention

[0006] In one aspect, the present invention provides a semiconductor device comprising: a first semiconductor die having a lower surface and an upper surface opposite to the lower surface; a second semiconductor die having a lower surface and an upper surface opposite to the lower surface, wherein the second semiconductor die is stacked on top of the first semiconductor die such that the lower surface of the second semiconductor die faces the upper surface of the first semiconductor die; and a stacked capacitor having a first capacitor plate located on the upper surface of the first semiconductor die, a second capacitor plate located on the lower surface of the second semiconductor die, and a dielectric material located between the first capacitor plate and the second capacitor plate; A first metallization feature is located on the upper surface of the first semiconductor die, wherein the first metallization feature and the first capacitor plate are formed by the same process, wherein the first metallization feature has substantially the same thickness as the first capacitor plate, and wherein the first capacitor plate is electrically coupled to the first metallization feature via conductive traces; and a second metallization feature is located on the lower surface of the second semiconductor die, wherein the second metallization feature and the second capacitor plate are formed by the same process, wherein the second metallization feature has substantially the same thickness as the second capacitor plate, and wherein the second capacitor plate is electrically coupled to the second metallization feature via conductive traces.

[0007] In another aspect, the present invention provides a semiconductor device comprising: a semiconductor die stack; and between each adjacent pair of semiconductor dies in the semiconductor die stack: a plurality of interconnects electrically coupled to at least the adjacent pairs of semiconductor dies; a parallel-plate capacitor comprising: an upper plate formed on a lower surface of an upper portion of the adjacent pair of semiconductor dies; a lower plate formed on an upper surface of a lower portion of the adjacent pair of semiconductor dies; and a dielectric material located between the upper plate and the lower plate; wherein each interconnect comprises: an upper metal... The upper metallization feature is formed on the lower surface of the upper part of the adjacent pair of semiconductor dies, and the lower metallization feature is formed on the upper surface of the lower part of the adjacent pair of semiconductor dies. The upper metallization feature and the upper plate are formed by the same process, and the upper metallization feature has substantially the same thickness as the upper plate. The lower metallization feature and the lower plate are formed by the same process, and the lower metallization feature has substantially the same thickness as the lower plate.

[0008] In another aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a plurality of first metallization features on a surface of a first semiconductor die, the first metallization features being electrically coupled to a through-silicon via (TSV) extending through the first semiconductor die; simultaneously forming the plurality of first metallization features on the surface of the first semiconductor die, wherein the first capacitor plate is electrically coupled to at least one of the first metallization features, and wherein the plurality of first metallization features have a thickness substantially the same as the first capacitor plate; forming a plurality of second metallization features on a surface of a second semiconductor die; simultaneously forming the plurality of second metallization features on the surface of the second semiconductor die, wherein the second capacitor plate is electrically coupled to at least one of the second metallization features, and wherein the plurality of second metallization features have a thickness substantially the same as the second capacitor plate; stacking the second semiconductor die over the first semiconductor such that at least a portion of the second capacitor plate is located over the first capacitor plate; and forming a dielectric material at least partially between the first capacitor plate and the second capacitor plate.

[0009] In another aspect, the present invention provides a method of manufacturing a semiconductor device, the method comprising: providing a first semiconductor die having a first metal structure formed on a surface of the first semiconductor die; stacking a second semiconductor die over the first semiconductor die such that a second metal structure formed on a surface of the second semiconductor die is at least partially aligned with the first metal structure; forming a dielectric material at least partially between the first metal structure and the second metal structure, wherein the first metal structure, the second metal structure, and the dielectric material together form a parallel-plate capacitor; and forming a plurality of interconnects between the first semiconductor die and the second semiconductor die, wherein each interconnect includes a first metallization feature formed on the surface of the first semiconductor die and a second metallization feature formed on the surface of the second semiconductor die; wherein the first metallization feature and the first metal structure are formed by the same process, and wherein the first metallization feature has substantially the same thickness as the first metal structure; wherein the second metallization feature and the second metal structure are formed by the same process, and wherein the second metallization feature has substantially the same thickness as the second metal structure. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view of a semiconductor die assembly according to an embodiment of the present invention.

[0011] Figure 2A and 2BThese are, respectively, top and bottom views of a semiconductor die configured according to an embodiment of the present invention.

[0012] Figure 3A and 3B These are, respectively, a top view and a bottom view of a semiconductor die configured according to another embodiment of the present invention.

[0013] Figures 4A to 4C This is a cross-sectional view illustrating various manufacturing stages of a semiconductor die according to embodiments of the present invention.

[0014] Figure 5 This is a schematic diagram of a system comprising a semiconductor die assembly configured according to an embodiment of the present invention. Detailed Implementation

[0015] The following describes specific details of several embodiments of semiconductor dies and semiconductor die assemblies. In several embodiments described below, the semiconductor die assembly includes a semiconductor die stack having a capacitor formed between each adjacent pair of semiconductor dies in the stack. In some embodiments, the capacitor is a parallel-plate capacitor comprising: (a) an upper plate formed on the lower surface of the upper one of each adjacent pair of semiconductor dies; (b) a lower plate formed on the upper surface of the lower one of each adjacent pair; and (c) a dielectric material located between the upper plate and the lower plate. The parallel-plate capacitor can locally store charge within the semiconductor die stack. When an individual semiconductor die has a power demand spike, the individual semiconductor die can draw power from one or more of the parallel-plate capacitors to meet the demand. Furthermore, in some embodiments, the plates of the parallel-plate capacitor can be formed as part of an existing metallization process for forming interconnects between stacked semiconductor dies without adding significant cost or complexity to the manufacturing process.

[0016] As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to the relative orientation or position of a feature in the semiconductor die and semiconductor die assembly described herein, given the orientation shown in the figures. For example, “upper” or “topmost” can specify a feature that is closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor dies and semiconductor die assemblies having other orientations (e.g., flipped or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation).

[0017] Figure 1This is a cross-sectional view illustrating a semiconductor die assembly 100 (“Assembly 100”) configured according to an embodiment of the present invention. Assembly 100 includes a stack 105 of semiconductor dies 110 carried by a package substrate 120. The package substrate 120 may include an interposer, a printed circuit board, dielectric spacers, another semiconductor die (e.g., a logic die), or another suitable substrate. The package substrate 120 is connected to an electrical connector 122 (e.g., a solder ball) that electrically couples Assembly 100 to external circuitry (not shown). In some embodiments, Assembly 100 may include an interposer, another logic die, or other suitable structure between the package substrate 120 and the lowermost of the semiconductor dies 110.

[0018] Semiconductor dies 110 may each have integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. For example, semiconductor die 110 may include integrated memory circuitry and / or logic circuitry, which may include various types of semiconductor components and functional features, such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, other forms of integrated circuit memory, processing circuitry, imaging components, and / or other semiconductor features. In some embodiments, semiconductor dies 110 may be identical (e.g., memory dies fabricated to have the same design and specifications), but in other embodiments, semiconductor dies 110 may be different from each other (e.g., combinations of different types of memory dies or controller, logic, and / or memory dies). Furthermore, although assembly 100 includes four semiconductor dies 110 stacked on package substrate 120, in other embodiments assembly 100 may include fewer than four semiconductor dies (e.g., two or three dies) or more than four dies (e.g., five, six, eight, twelve, sixteen, thirty-two, etc.).

[0019] like Figure 1The diagram further illustrates that each semiconductor die 110 has an upper surface 113a and a lower surface 113b opposite to the upper surface 113a (collectively referred to as "surfaces 113a, 113b"). Some semiconductor dies 110 may further include a plurality of vias 112 (e.g., through-silicon vias (TSVs)) that extend at least substantially through the semiconductor die 110 (e.g., through its semiconductor substrate). In some embodiments, each via 112 includes a conductive material (e.g., copper) that extends completely through the individual semiconductor die 110, and an electrically insulating material surrounding the conductive material to electrically isolate the via 112 from the remainder of the semiconductor die 110. More specifically, the via 112 may extend completely through the semiconductor die 110 such that the upper portion of each via 112 is exposed at the upper surface 113a of the individual semiconductor die 110, and the lower portion of the via 112 is exposed at the lower surface 113b of the individual semiconductor die 110. In this manner, the via 112 is configured for mechanical and / or electrical connections to other semiconductor dies 110 and / or package substrates 120 in the stack 105. For example... Figure 1 As illustrated in the embodiments, the uppermost semiconductor die 110 in stack 105 may not have vias because electrical connections via the uppermost semiconductor die 110 (e.g., at the upper surface 113a of the uppermost semiconductor die 110) may not be necessary. In other embodiments, the uppermost semiconductor die 110 may also include multiple vias 112 to allow electrical coupling of the uppermost semiconductor die 110 to other circuitry (e.g., additional semiconductor dies, higher-level circuitry, etc.) at the upper surface 113a of the uppermost semiconductor die 110. In still other embodiments, the semiconductor dies 110 may be electrically coupled together using other interconnection methods well known to those skilled in the art (including, for example, lap wire bonding, face-to-face interconnects, etc.) without using TSVs.

[0020] Assembly 100 further includes a plurality of conductive interconnects 130 extending between and electrically coupling adjacent semiconductor dies 110 in stack 105. Each interconnect 130 may include an upper metallization feature 132, a lower metallization feature 134, and a conductive element 136 coupling the upper and lower metallization features 132 and 134 (collectively, “metallization features 132, 134”). Conductive element 136 may include a solder material, such as tin-silver, indium, or another suitable solder material for forming electrical and mechanical connections between metallization features 132, 134 on adjacent semiconductor dies 110. In other embodiments, conductive element 136 may be made of other suitable materials and / or have different structures (e.g., copper pillars, bumps on nitride structures, etc.).

[0021] Generally speaking, metallization features 132 and 134 can be any counterpart known in the art that is suitable for an under-bump metallization (UBM) structure and electrically coupled to the via 112 of the semiconductor die 110. The upper metallization feature 132 is formed on the lower surface 113b of the upper semiconductor die 110 of a pair of adjacent semiconductor dies 110 in the stack 105. Similarly, the lower metallization feature 134 is formed on the upper surface 113a of the lower semiconductor die 110 of the pair of adjacent semiconductor dies. More specifically, as... Figure 1 As shown, the upper metallization feature 132 may be formed above the lower portion of the via 112 exposed at the lower surface 113b of the upper semiconductor die 110 in the pair of adjacent semiconductor dies. Similarly, the lower metallization feature 134 may be formed above the upper portion of the via 112 exposed at the upper surface 113a of the lower semiconductor die 110 in the pair of adjacent semiconductor dies. Therefore, the interconnect 130 (i.e., the upper metallization feature 132, the conductive element, and the lower metallization feature 134) may be axially aligned with and electrically coupled to the pair of vias 112 in the pair of adjacent semiconductor dies. However, in other embodiments, the interconnect 130 need not be axially aligned with the vias 112. For example, the redistribution layer (RDL) or other conductive structures on the lower and / or upper semiconductor dies 110 of the adjacent semiconductor dies can provide different alignments and couplings between the vias 112 and the metallization features 132, 134 of the adjacent semiconductor dies.

[0022] Metallization features 132 and 134 may include any or a combination of suitable conductive materials such as copper, nickel, gold, silicon, and tungsten, and may have a thickness (e.g., height) between about 1 micrometer and 100 micrometers (e.g., less than about 10 micrometers). Furthermore, the shape and size of metallization features 132 and 134 may vary. For example, in some embodiments, metallization features 132 and 134 have a substantially cylindrical cross-sectional shape and form a columnar structure. In other embodiments, metallization features 132 and 134 may have other cross-sectional shapes, such as rectangular, regular polygonal, irregular polygonal, elliptical, etc.

[0023] Assembly 100 further includes a plurality of upper capacitor plates 142 and a plurality of lower capacitor plates 144 (collectively referred to as "capacitor plates 142, 144"). Each upper capacitor plate 142 is formed on the lower surface 113b of an upper semiconductor die 110 in a pair of adjacent semiconductor dies 110 in the stack 105, and each lower capacitor plate 144 is formed on the upper surface 113a of a lower semiconductor die 110 in the pair of adjacent semiconductor dies. Figure 1As illustrated in the embodiments, each upper capacitor plate 142 faces and is at least partially aligned with the corresponding lower capacitor plate 144. For example, such as Figure 1 As shown, each upper capacitor plate 142 is stacked over a corresponding lower capacitor plate 144 on an adjacent lower semiconductor die 110 (e.g., capacitor plates 142, 144 are substantially planar reflectively symmetrical about the space between adjacent semiconductor dies). At least one of the capacitor plates 142, 144 is electrically coupled to a power supply while the other is electrically coupled to ground. For example (e.g.) Figure 2A and 2B As shown in the diagram, capacitor plates 142 and 144 can each be electrically coupled to one or more of the interconnects 130 via conductive traces formed on surfaces 113a and 113b of the semiconductor die 110, thereby providing a power or ground signal. In other embodiments, capacitor plates 142 and 144 can be electrically coupled to a power supply or ground using other suitable electrical connectors (e.g., wire connections). Thus, a voltage difference can be provided between opposing capacitor plates 142 and 144 formed between each pair of adjacent semiconductor dies 110 in the stack 105.

[0024] See below for reference Figures 4A to 4C In further detail, capacitor plates 142 and 144 can be formed as an extension of the metallization process used to form metallization features 132 and 134 (e.g., at the same processing stage and / or simultaneously). Therefore, since metallization features 132 and 134 and capacitor plates 142 and 144 can be formed by the same process, at least some of their properties can be the same or substantially similar. For example, metallization features 132 and 134 can each have the same or substantially similar thickness as capacitor plates 142 and 144. Similarly, metallization features 132 and 134 can comprise the same material as capacitor plates 142 and 144 (e.g., copper, nickel, gold, silicon, tungsten, etc.).

[0025] Assembly 100 may further include a dielectric material 150 deposited or otherwise formed around the semiconductor dies 110, interconnects 130, and capacitor plates 142, 144 and / or between the semiconductor dies 110, interconnects 130, and capacitor plates 142, 144 to electrically isolate these components and / or enhance the mechanical connections between the semiconductor dies 110 in stack 105. The dielectric material 150 may be a non-conductive epoxy paste, a capillary underfill, a non-conductive film, a molded underfill, and / or contain other suitable electrically insulating materials.

[0026] In summary, each pair of opposing capacitor plates 142, 144 and the dielectric material 150 therebetween form a stacked capacitor (e.g., a parallel-plate capacitor) that stores charge within the stack 105. The charge stored on each parallel-plate capacitor is proportional to the capacitance (C) of the capacitor, C = k∈OA / d, where “k” is the relative permittivity of the dielectric material between the plates, “∈O” is the vacuum permittivity, “A” is the area of ​​the capacitor plates, and “d” is the spacing between the capacitor plates. In some embodiments, the stacked capacitors formed in the assembly 100 each have a capacitance of 10 to 100 picofarads (e.g., more than about 100 picofarads). Furthermore, since the capacitance (and therefore the charge stored by the capacitor) is inversely proportional to the distance between the capacitor plates 142, 144, the capacitance can increase as the vertical distance (e.g., the spacing) between the semiconductor dies 110 in the stack 105 decreases. The spacing between the semiconductor dies 110 in the stack 105 depends largely on the size of the interconnects 130. Therefore, as technology advances to reduce the size of interconnect 130 and thereby reduce the overall height of assembly 100, the capacitance of the capacitors in the stack described herein can be increased accordingly. Furthermore, in some embodiments, the dielectric material 150 can be selected based on its dielectric properties (e.g., its relative permittivity or other characteristics) to increase the capacitance of the capacitors in the stack.

[0027] Generally, each in-stack capacitor in stack 105 adds capacitance to the power network of stack 105, which can be drawn from semiconductor dies 110 when needed. For example, when an individual semiconductor die 110 in stack 105 has a power demand spike (e.g., when an individual semiconductor die 110 performs a power-intensive operation (e.g., a start access, read operation, etc.)), the individual semiconductor die 110 can draw some of its required power from one or more of the in-stack capacitors. The in-stack capacitors provide a more localized power supply than the power from an external power supply, which must be routed through the package substrate 120 and upwards through vias 112 and interconnects 130. Therefore, the in-stack capacitors can quickly address some short-term power needs of semiconductor dies 110, to which the power supply's response can be slow, depending on the power needs of other semiconductor dies 110 in stack 105 (e.g., the lower semiconductor dies in the stack). Conventional methods for improving power delivery in semiconductor die stacks increase the TSV count of each die in the stack to include more power and ground connections, thereby reducing the resistance of the power network. However, increasing the TSV count of a semiconductor die requires increasing its size. The present invention advantageously increases the capacitance of the power network in assembly 100 without increasing the TSV count and / or the size of the semiconductor die 110, allowing assembly 100 to better meet the power requirements of the semiconductor dies 110 in stack 105.

[0028] Furthermore, adding capacitors to the power network can improve the signal integrity of signals transmitted via one or more vias 112 through stack 105 and / or the performance of semiconductor die 110. For example, capacitors in the stack can act as decoupling capacitors to shunt noise that would otherwise be carried via stack 105 (e.g., voltage spikes or ground bounces caused by other dies in the stack) and could impede the performance of semiconductor die 110. Capacitors in the stack can also help address inductor ringing problems (e.g., ringing caused by encapsulated inductors in memory devices). For example, capacitors in the stack can help minimize inductor paths for power supply and ground connections, thereby improving the performance of semiconductor die 110.

[0029] like Figure 1As shown, in-stack capacitors are formed between each pair of adjacent semiconductor dies 110 in stack 105. The in-stack capacitors may be connected in parallel or in series, or electrically coupled in some combination thereof. However, in some embodiments, stack 105 may have only one in-stack capacitor formed between a single pair of adjacent semiconductor dies 110, or any other number of in-stack capacitors. In some embodiments, an additional capacitor may be formed between the package substrate 120 and the bottommost semiconductor die 110 in stack 105 by: (a) providing a lower capacitor plate 144 on the package substrate 120; (b) providing a corresponding upper capacitor plate 142 on the lower surface 113b of the bottommost semiconductor die 110; and (c) providing a dielectric material (e.g., dielectric material 150) between the lower capacitor plate 144 and the upper capacitor plate 142. Similarly, in some embodiments, capacitors may be formed between the upper surface 113a of the uppermost semiconductor die 110 in stack 105 and any external components connected thereto.

[0030] Figure 2A and 2B These are embodiments of the technology according to the present invention. Figure 1 The diagram shows a top and bottom view of one of the semiconductor dies 110 of the assembly 100, wherein each of the surfaces 113a and 113b of the semiconductor die 110 has metallization features and capacitor plates. The illustration suggests that the semiconductor die 110 may be one of the semiconductor dies 110 in the middle of the stack 105 (e.g., adjacent semiconductor dies 110 on both the top and bottom), because the bottommost and topmost semiconductor dies 110 in the stack 105 may be formed without capacitor plates and / or metallization features (e.g., capacitor plates) on their lower surface 113b and upper surface 113a, respectively. Figure 1 (Illustrated explanation).

[0031] More specifically, Figure 2A The diagram illustrates the upper surface 113a of a semiconductor die 110 having one or more peripheral regions 216 (e.g., lateral outer regions) and a central region 218. Lower metallization features 134 are formed on the peripheral regions 216, and a lower capacitor plate 144 is formed on the central region 218 of the upper surface 113a. The lower capacitor plate 144 can be electrically coupled to one or more of the lower metallization features 134 via conductive traces 238 (individually shown as conductive traces 238a and 238b). For example, such as Figure 2AAs illustrated in the embodiments, the lower capacitor plate 144 can be electrically coupled to a first lower metallization feature 134a via conductive trace 238a and to a second lower metallization feature 134b via conductive trace 238b. The first lower metallization feature 134a and the second lower metallization feature 134b can be electrically coupled to ground or to a power supply. In some embodiments, the conductive trace 238 is formed as part of the same metallization process as the lower metallization feature 134 and the lower capacitor plate 144.

[0032] Figure 2B The diagram illustrates the lower surface 113b of a semiconductor die 110 having one or more peripheral regions 226 (e.g., lateral outer regions) and a central region 228. An upper metallization feature 132 is formed on the peripheral regions 226, and an upper capacitor plate 142 is formed on the central region 228 of the lower surface 113b. The upper capacitor plate 142 can be electrically coupled to one or more of the upper metallization features 132 via conductive traces 248 (individually shown as conductive traces 248a and 248b). For example, such as Figure 2B As illustrated in the embodiments, the upper capacitor plate 142 can be electrically coupled to a first upper metallization feature 132a via conductive trace 248a and to a second upper metallization feature 132b via conductive trace 248b. The first upper metallization feature 132a and the second upper metallization feature 132b can be electrically coupled to ground or to a power supply. In some embodiments, the conductive trace 248 is formed as part of the same metallization process as the upper metallization feature 132 and the upper capacitor plate 142.

[0033] In some embodiments, capacitor plates 142, 144 may be electrically coupled to the same vias in the semiconductor die 110. Figure 1 Therefore, capacitor plates 142, 144 can be electrically coupled to both ground and power supply. In these embodiments, each alternating semiconductor die 110 in stack 105 may have the same configuration of capacitor plates 142, 144 such that there is a voltage difference between opposing capacitor plates 142, 144 between adjacent pairs of semiconductor dies 110 formed in stack 105. However, in other embodiments, capacitor plates 142, 144 on semiconductor dies 110 may be electrically coupled to different (e.g., individual) vias 112 such that one of capacitor plates 142, 144 is electrically coupled to ground and the other is electrically coupled to power supply. For example, in these embodiments, each upper capacitor plate 142 in stack 105 may be electrically coupled to power supply and each lower capacitor plate 144 may be electrically coupled to ground.

[0034] Let's refer to each other. Figure 2A and 2BBoth capacitor plates 142 and 144 can be formed to fill relatively large areas of surfaces 113b and 113a, respectively, areas not otherwise occupied by metallization features 132 and 134. For example, such as Figure 2A and 2B As illustrated in both diagrams, the semiconductor die 110 may have metallization features 132, 134 arranged in rows at the peripheral regions 216, 226 of surfaces 113a, 113b. By forming capacitor plates 142, 144 on the central regions 218, 228 and shaping them with rectangular cross-sections (e.g., rectangular planar shapes), the capacitor plates 142, 144 may occupy a considerable area of ​​surfaces 113a, 113b not occupied by the metallization features 132, 134 (their location may be limited to the location of via 112). For example, in some embodiments, the capacitor plates 142, 144 may each cover an area greater than approximately 25% of the surface area of ​​surfaces 113a, 113b of the semiconductor die 110. In some embodiments, the capacitor plates 142, 144 may cover an area greater than approximately 50% of the surface area of ​​surfaces 113a, 113b. In some other embodiments, capacitor plates 142, 144 may cover an area greater than approximately 75% of the surface area of ​​surfaces 113a, 113b. However, the coverage of capacitor plates 142, 144 is not limited, and capacitor plates 142, 144 may cover any suitable portion of surfaces 113a, 113b. Furthermore, in some embodiments, metallization features 132, 134 may be formed on different regions of the semiconductor die 110 and may have different arrangements. In these embodiments, the size, shape, and positioning of the capacitor plates may be selected to match the layout of the metallization features 132, 134.

[0035] For example, Figure 3A and 3B These are, respectively, top and bottom plan views of one of the semiconductor dies 110 of the assembly 100 according to another embodiment of the present invention, wherein the semiconductor dies 110 have metallization features and different arrangements of capacitor plates on surfaces 113a and 113b. (See also: Top plan view and Bottom plan view of one of the semiconductor dies 110 according to another embodiment of the present invention, wherein the semiconductor dies 110 have different metallization features and capacitor plates on surfaces 113a and 113b.) Figure 3A and 3B Both, metallization features 132 and 134 are arranged in rows that are uniformly spaced along surfaces 113b and 113a, respectively. Metallization features 132 and 134 can be arranged in this manner (for example) to match the arrangement of vias (e.g., via 112) on the semiconductor die 110. Figure 3A As shown, the lower capacitor plate 344 is electrically coupled to one or more of the lower metallization features 134 on the upper surface 113a forming the semiconductor die 110 and via conductive traces 338 (e.g., corresponding to power or ground). Similarly, as Figure 3BAs shown, the upper capacitor plate 342 is formed on the lower surface 113b of the semiconductor die 110 and is electrically coupled to one or more of the upper metallization features 132 via conductive traces 348 (e.g., corresponding to power or ground). In some embodiments, both the upper capacitor plate 342 and the lower capacitor plate 344 are electrically coupled to the same via 112 of the semiconductor die 110. Figure 1 (For example, both plates are grounded or both are connected to a power supply), while in other embodiments, the upper capacitor plate 342 and the lower capacitor plate 344 are electrically coupled to different ones in the via 112 (e.g., one of the plates is grounded and the other is connected to a power supply). Furthermore, both the upper capacitor plate 342 and the lower capacitor plate 344 have a generally linear shape and are formed over a considerable portion of the open surface area surrounding the metallization features 132, 134. Given the layout of the metallization features 132, 134, this arrangement typically allows the upper capacitor plate 342 and the lower capacitor plate 344 to have the largest possible area.

[0036] Generally speaking, the size, shape, and positioning of the capacitor plates described herein can be selected to maximize or nearly maximize the area of ​​the capacitor plates in order to increase the capacitance of the stacked capacitors formed in the die stack. More specifically, each capacitor plate can be formed on an open surface area of ​​a semiconductor die that will not otherwise be occupied by metallization features. Therefore, the capacitor plates described herein can be adapted to specific configurations of the semiconductor dies on which they are formed (e.g., for arrangements of vias, metallization features, and / or other features) while adding little or no additional overhead to the die assembly (e.g., without increasing the planar size or thickness of the die assembly).

[0037] Furthermore, each semiconductor die may include a single capacitor plate (as described in conjunction with the several embodiments above) or more than one capacitor plate on its surface. For example, given existing metallization structures, a semiconductor die as described herein may include multiple discrete capacitor plates to match the available space on the surface of the semiconductor die. The discrete capacitor plates may be electrically coupled (e.g., via conductive traces) or electrically isolated. In some embodiments, adjacent semiconductor dies may each have multiple discrete capacitor plates on their facing surfaces to form multiple discrete parallel-plate capacitors between adjacent semiconductor dies. The multiple parallel-plate capacitors may operate independently of each other, or may be connected in parallel, in series, etc.

[0038] Figures 4A to 4C This is a cross-sectional view illustrating various stages in a method for manufacturing a semiconductor wafer with metallized features and a capacitor plate formed thereon, according to embodiments of the present invention. Figures 4A to 4CIn the illustrated embodiment, a plurality of semiconductor dies 110 may be formed at discrete regions of a substrate assembly 400 (e.g., a semiconductor wafer or panel). The substrate assembly 400 includes a semiconductor material 460 and a dielectric material 462 on the upper side of the semiconductor material 460. Although Figures 4A to 4C The illustration only depicts a single semiconductor die 110, but in practice, the substrate assembly 400 typically has hundreds or even more than 1,000 individual semiconductor dies.

[0039] refer to Figure 4A At this processing stage, a via 112 has been formed in the semiconductor material 460. As will be readily understood by those skilled in the art, the via 112 can be formed by etching a high aspect ratio hole into the semiconductor material 460 and filling the high aspect ratio hole with one or more materials in one or more deposition and / or plating steps. For example, in Figure 4A In the embodiment shown, the through-hole 112 includes a dielectric liner 464 and a conductive plug 466 within the dielectric liner 464. For example... Figure 4A As further shown, the upper portion of the via 112 is exposed at the upper surface 113a of the semiconductor die 110.

[0040] Figure 4B The illustration depicts a substrate assembly 400 after forming a lower metallization feature 134 over the upper portion of via 112 and after forming a lower capacitor plate 144 on the upper surface 113a of the semiconductor die 110. Notably, the lower capacitor plate 144 can be formed as an extension of the metallization process used to form the lower metallization feature 134. The metallization process can be any suitable metallization process known in the art (e.g., front-side metallization or under-bump metallization). In some embodiments, for example, the lower metallization feature 134 is formed by: depositing a copper seed structure onto the dielectric material 462 and the upper portion of via 112; forming a mask on the copper seed structure with an opening aligned with the upper portion of via 112; electroplating copper onto the seed structure; and then plating one or more other materials over the copper to form the lower metallization feature 134. The lower capacitor plate 144 can be configured by adjusting the mask pattern to include one or more openings corresponding to the desired shape, position, and size of the lower capacitor plate 144 and any traces connecting the lower capacitor plate 144 to one or more of the lower metallization features 134 (e.g., Figure 2A The trace 238 in the middle is formed as part of this process. In some embodiments, after forming the lower metallization feature 134 and the lower capacitor plate 144 (and in some embodiments, the conductive element 136), a suitable wet etching removal mask is used to remove the exposed portion of the seed structure to isolate the lower metallization feature 134 from the lower capacitor plate 144.

[0041] Figure 4C The diagram illustrates the substrate assembly 400 after the following operations: (a) thinning semiconductor material 460 to expose the lower surface 113b of semiconductor die 110 and the lower portion of via 112 (e.g., using back-side grinding, dry etching, chemical etching, chemical mechanical polishing (CMP), etc.); (b) forming dielectric material 468 on the lower side of semiconductor material 460; (c) forming an upper metallization feature 132 above the lower portion of via 112; and (d) forming an upper capacitor plate 142 on the lower surface 113b of semiconductor die 110. The upper capacitor plate 142 may be formed as an extension of the metallization process used to form the upper metallization feature 132, which may be any suitable process known in the art (e.g., back-side metallization or under-bump metallization). In some embodiments, the metallization process for forming the lower metallization feature 134 and the lower capacitor plate 144 may be the same as the metallization process for forming the upper metallization feature 132 and the upper capacitor plate 142. In other embodiments, the process may be different. For example, it may not be necessary to perform the process for the topmost and bottommost dies in the stack. Figures 4A to 4C In at least some of the stages illustrated in the diagram, the uppermost and lowermost dies may be formed without capacitor plates and / or metallization features on at least one surface. Once the substrate assembly 400 has been processed, the semiconductor die 110 can be individualized from the substrate assembly 400 and incorporated into the die assembly (e.g., Figure 1 The assembly shown in the figure is 100.

[0042] Notably, capacitor plates 142 and 144 can be formed without adding significant additional cost or complexity to existing methods for forming metallization features 132 and 134, because capacitor plates 142 and 144 can be formed as an extension of those methods. Similarly, conductive traces (e.g., Figures 2A to 3B The traces 238 / 248 and 338 / 348 shown can also be readily formed as part of the same method to electrically couple capacitor plates 142, 144 to corresponding metallization features 132, 134 to provide a suitable voltage difference between the plates.

[0043] The above references can be used Figures 1 to 4C Any of the semiconductor devices with the described features can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is... Figure 5The system 500 is schematically shown in the diagram. System 500 may include a processor 502, a memory 504 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 505, and / or other subsystems or components 508. (See above reference) Figures 1 to 4C The described semiconductor die assembly 100 and semiconductor die 110 may be included in Figure 5 The resulting system 500 can be configured to perform a wide variety of computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 500 include (but are not limited to) computers and / or other data processors, such as desktop computers, laptop computers, internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 500 include lights, cameras, vehicles, etc. Regarding these and other examples, system 500 can be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Therefore, components of system 500 can include local and / or remote memory storage devices and a wide variety of computer-readable media.

[0044] Based on the foregoing, it will be understood that although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the invention. Therefore, the invention is not limited to anything other than the appended claims. Furthermore, specific aspects of the new technology described in the context of particular embodiments may be combined or eliminated in other embodiments. Moreover, although advantages associated with particular embodiments have been described in the context of those embodiments, other embodiments may also exhibit these advantages, and not all embodiments must exhibit these advantages to fall within the scope of the invention. Therefore, the invention and related technologies may encompass other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor device comprising: A first semiconductor die has a lower surface and an upper surface opposite to the lower surface; A second semiconductor die has a lower surface and an upper surface opposite to the lower surface, wherein the second semiconductor die is stacked on top of a first semiconductor die such that the lower surface of the second semiconductor die faces the upper surface of the first semiconductor die; A stacked capacitor having a first capacitor plate located on the upper surface of the first semiconductor die, a second capacitor plate located on the lower surface of the second semiconductor die, and a dielectric material located between the first capacitor plate and the second capacitor plate; A plurality of first metallization features are arranged in a plurality of rows on the upper surface of the first semiconductor die, wherein the plurality of first metallization features and the first capacitor plate are formed by the same process, wherein the plurality of first metallization features have the same thickness as the first capacitor plate, wherein the first capacitor plate is electrically coupled to the first metallization features in the plurality of first metallization features via conductive traces, and wherein the material portion of the first capacitor plate is interleaved with the plurality of rows on the upper surface of the first semiconductor die. as well as A second plurality of metallization features are arranged in a second plurality of rows on the lower surface of the second semiconductor die, wherein the second plurality of metallization features and the second capacitor plate are formed by the same process, wherein the second plurality of metallization features have the same thickness as the second capacitor plate, wherein the second capacitor plate is electrically coupled to the second metallization features in the second plurality of metallization features via conductive traces, and wherein the material portion of the second capacitor plate is interleaved with the second plurality of rows on the lower surface of the second semiconductor die.

2. The semiconductor device of claim 1, wherein the first capacitor plate is electrically coupled to the first metallization feature via a first conductive trace, and wherein the second capacitor plate is electrically coupled to the second metallization feature via a second conductive trace.

3. The semiconductor device of claim 1, wherein the capacitor in the stack is a parallel-plate capacitor.

4. The semiconductor device of claim 3, wherein the parallel plate capacitor has a capacitance greater than 100 pF.

5. The semiconductor device of claim 1, further comprising a first through-silicon via extending through the first semiconductor die, wherein: The first metallization feature is electrically coupled to the first through-silicon via; The second metallization feature is electrically coupled to the first metallization feature; The first metallization feature is made of the same metallic material as the first capacitor plate; and The second metallization feature is made of the same metallic material as the second capacitor plate.

6. The semiconductor device according to claim 1, further comprising: A first through-silicon via extending through the first semiconductor die, wherein the first metallization feature is electrically coupled to the first through-silicon via; and At least one second through-silicon via extends through the second semiconductor die, wherein the second metallization feature is electrically coupled to the second through-silicon via.

7. The semiconductor device of claim 6, wherein the first through-silicon via, the second through-silicon via, the first metallization feature, and the second metallization feature are axially aligned.

8. The semiconductor device of claim 1, wherein the first capacitor plate and the second capacitor plate have a rectangular planar shape that is reflectively symmetrical about a plane extending therebetween.

9. The semiconductor device of claim 1, wherein the first capacitor plate has a surface area greater than 25% of the area of ​​the upper surface of the first semiconductor die.

10. The semiconductor device of claim 1, further comprising: A third semiconductor die has a lower surface and an upper surface opposite to the lower surface, wherein the third semiconductor die is stacked on top of a second semiconductor die such that the upper surface of the second semiconductor die faces the lower surface of the third semiconductor die. and Another capacitor in the stack has a third capacitor plate located on the upper surface of the second semiconductor die, a fourth capacitor plate located on the lower surface of the third semiconductor die, and a dielectric material located between the third capacitor plate and the fourth capacitor plate.

11. The semiconductor device of claim 1, wherein the thickness of the first plurality of metallization features and the first capacitor plate is the same as the thickness of the second plurality of metallization features and the second capacitor plate.

12. The semiconductor device of claim 1, further comprising a conductive element coupled to the first plurality of metallization features and the second plurality of metallization features.

13. A semiconductor device comprising: Semiconductor die stacking; and Between each adjacent pair of semiconductor dies in the semiconductor die stack: Multiple interconnects electrically coupled to at least the adjacent pairs of semiconductor dies, A parallel-plate capacitor includes: an upper plate formed on a lower surface of an upper portion of an adjacent pair of semiconductor dies; a lower plate formed on an upper surface of a lower portion of an adjacent pair of semiconductor dies; and a dielectric material located between the upper plate and the lower plate. Each interconnect includes an upper metallization feature and a lower metallization feature, the upper metallization feature being formed on the lower surface of the upper part of the adjacent pair of semiconductor dies, and the lower metallization feature being formed on the upper surface of the lower part of the adjacent pair of semiconductor dies. The upper metallized feature and the upper plate are formed by the same process, and the upper metallized feature has the same thickness as the upper plate. The lower metallized feature and the lower plate are formed by the same process, and the lower metallized feature has the same thickness as the lower plate. The material portion of the upper plate intersects with the corresponding upper metallization features of the plurality of interconnects on the lower surface of the upper portion of the adjacent pair of semiconductor dies; and The material portion of the lower plate intersects with the corresponding lower metallization features of the plurality of interconnects on the upper surface of the lower portion of the adjacent pair of semiconductor dies.

14. The semiconductor device of claim 13, wherein the upper plate is electrically coupled to the upper metallization feature via a first conductive trace, and wherein the lower plate is electrically coupled to the lower metallization feature via a second conductive trace.

15. The semiconductor device of claim 13, wherein the upper plate is electrically coupled to a power supply, and wherein the lower plate is electrically coupled to ground.

16. The semiconductor device of claim 13, wherein each upper plate is electrically coupled to at least a first of the interconnects, and wherein each lower plate is electrically coupled to at least a second of the interconnects.

17. The semiconductor device of claim 13, wherein the upper metallization feature is made of the same material as the upper plate, and wherein the lower metallization feature is made of the same material as the lower plate.

18. The semiconductor device of claim 13, wherein the upper metallization feature of each interconnect is aligned with the lower metallization feature of the interconnect, and wherein each interconnect further includes a solder ball or solder bump coupling the upper metallization feature to the lower metallization feature.

19. The semiconductor device of claim 13, wherein each individual semiconductor die is electrically coupled to at least one of the parallel plate capacitor and the power supply via the interconnect, and wherein the at least one parallel plate capacitor provides a power source closer to the individual semiconductor die than the power supply.

20. The semiconductor device of claim 13, wherein each interconnect further includes a conductive element coupling the upper metallization feature and the lower metallization feature.

21. A method of manufacturing a semiconductor device, the method comprising: Forming a first plurality of metallization features such that the first plurality of metallization features are arranged in a first plurality of rows on the surface of a first semiconductor die, the first plurality of metallization features being electrically coupled to through-silicon vias extending through the first semiconductor die; While forming the first plurality of metallization features, a first capacitor plate is formed on the surface of the first semiconductor die, wherein the first capacitor plate is electrically coupled to at least one of the first plurality of metallization features, wherein the first plurality of metallization features have the same thickness as the first capacitor plate, and wherein the material portion of the first capacitor plate is staggered with the first plurality of rows on the surface of the first semiconductor die. Form a second plurality of metallization features such that the second plurality of metallization features are arranged in a second plurality of rows on the surface of the second semiconductor die; While forming the second plurality of metallization features, a second capacitor plate is formed on the surface of the second semiconductor die, wherein the second capacitor plate is electrically coupled to at least one of the second plurality of metallization features, wherein the second plurality of metallization features have the same thickness as the second capacitor plate, and wherein the material portion of the second capacitor plate is interleaved with the second plurality of rows on the surface of the second semiconductor die. The second semiconductor die is stacked on top of the first semiconductor such that at least a portion of the second capacitor plate is located on top of the first capacitor plate; and A dielectric material is formed at least partially between the first capacitor plate and the second capacitor plate.

22. The method of claim 21, wherein the first capacitor plate is electrically coupled to at least one of the first plurality of metallization features via a first conductive trace, and wherein the second capacitor plate is electrically coupled to at least one of the second plurality of metallization features via a second conductive trace.

23. The method of claim 21, wherein the method further comprises electrically coupling the first plurality of metallized features to the second plurality of metallized features via a plurality of electrical connectors disposed between the first plurality of metallized features and the second plurality of metallized features.

24. The method of claim 21, wherein the method further comprises forming a plurality of conductive elements, wherein each conductive element is coupled to one of the first plurality of metallization features and a corresponding one of the second plurality of metallization features.

25. A method of manufacturing a semiconductor device, the method comprising: A first semiconductor die is provided, the first semiconductor die having a first metal structure formed on the surface of the first semiconductor die; A second semiconductor die is stacked on top of the first semiconductor die such that a second metal structure formed on the surface of the second semiconductor die is at least partially aligned with the first metal structure; A dielectric material is formed at least partially between the first metal structure and the second metal structure, wherein the first metal structure, the second metal structure, and the dielectric material together form a parallel plate capacitor; and A plurality of interconnects are formed between the first semiconductor die and the second semiconductor die, wherein each interconnect includes a first metallization feature formed on the surface of the first semiconductor die and a second metallization feature formed on the surface of the second semiconductor die; The first metallization feature and the first metal structure are formed by the same process, and the first metallization feature has the same thickness as the first metal structure. The second metallization feature and the second metal structure are formed by the same process, and the second metallization feature has the same thickness as the second metal structure. The material portions of the first metal structure and the corresponding first metallization features of the plurality of interconnects are interleaved on the surface of the first semiconductor die; and The material portions of the second metal structure and the corresponding second metallization features of the plurality of interconnects are interleaved on the surface of the second semiconductor die.

26. The method of claim 25, wherein the first metal structure is electrically coupled to the first metallization feature via a first conductive trace, and wherein the second metal structure is electrically coupled to the second metallization feature via a second conductive trace.

27. The method of claim 25, wherein the first metallization feature and the second metallization feature are axially aligned and electrically coupled via an electrical connector disposed therebetween, wherein the first metallization feature and the first metal structure are made of the same material, and wherein the second metallization feature and the second metal structure are made of the same material.

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