Common anode data communication VCSEL chip based on p substrate and preparation method thereof

Abstract

The present invention relates to the field of laser technology and provides a p-substrate-based common anode data communication VCSEL chip, comprising a p-substrate and an epitaxial layer fabricated on the p-substrate, wherein an n-electrode and a first p-electrode are fabricated on a surface of the epitaxial layer away from the p-substrate, the n-electrode and the first p-electrode being separated by an electrode isolation region, a second p-electrode is fabricated on a surface of the p-substrate away from the epitaxial layer, and the first p-electrode and the second p-electrode are conductively connected. A method for preparing a p-substrate-based common anode data communication VCSEL chip is also provided. The present invention fabricates an epitaxial layer on the p-substrate and then forms contact layers of p-type and n-type metals. Compared to a traditional common cathode structure, this common anode structure converts the main carriers of signal modulation from holes to electrons, thereby reducing the overall effective carrier mass and facilitating higher modulation bandwidth and modulation rate.

Description

Technical Field

[0001] The present invention relates to the field of laser technology, in particular to a p-substrate-based common anode data communication VCSEL chip and a preparation method thereof. Background Art

[0002] The structure of a vertical-cavity surface-emitting laser (VCSEL) consists of a p-DBR, an n-DBR, and an active region. The quantum wells in the active region perform photoelectric conversion, forming a laser resonant cavity between the p-DBR and n-DBR. VCSELs require spatial confinement of both the electric and optical fields to create a laser light source with low threshold current, high photoelectric conversion efficiency, and high modulation frequency. Furthermore, due to their circular light-emitting aperture and vertical light-emitting structure, they are easily coupled to optical fibers. Therefore, high-speed VCSELs can be used in data centers as the transmitter for short-distance fiber-optic data communications, enabling optical interconnection.

[0003] Existing VCSELs for high-speed data communications are based on an n-type doped gallium arsenide (n-GaAs) substrate. The n-DBR region, active region, and p-DBR region are grown on the n-GaAs substrate. The conductive channel is then defined through a wafer fabrication process, and p-type and n-type metal contact layers are formed. Due to physical limitations, this traditional common cathode design makes it difficult to further increase the device's bandwidth and modulation rate. Summary of the Invention

[0004] The object of the present invention is to provide a common anode data communication VCSEL chip based on a p-substrate and a preparation method thereof, which can at least solve some of the defects in the prior art.

[0005] To achieve the above objectives, an embodiment of the present invention provides the following technical solution: a common anode data communication VCSEL chip based on a p-substrate, comprising a p-substrate and an epitaxial layer fabricated on the p-substrate, an n-electrode and a first p-electrode fabricated on a surface of the epitaxial layer away from the p-substrate, the n-electrode and the first p-electrode being separated by an electrode isolation region, a second p-electrode being fabricated on a surface of the p-substrate away from the epitaxial layer, and the first p-electrode and the second p-electrode being conductive.

[0006] Furthermore, the epitaxial layer includes a p-DBR region, an active region and an n-DBR region grown sequentially on the p substrate.

[0007] Furthermore, the epitaxial layer has a light exit hole that sequentially passes through the p-DBR region, the active region and the n-DBR region. The light exit surface of the light exit hole is opened on the n-DBR region, and the light exit surface is provided in the n-electrode.

[0008] Furthermore, the active layer and the n-DBR region are separated by an oxide layer, the oxide layer has an opening in the middle, and the position of the opening is the position of the light output hole.

[0009] Furthermore, an insulating layer is provided on the n-DBR region.

[0010] Furthermore, the insulating layer is a silicon nitride insulating layer.

[0011] Furthermore, the p-substrate is a p-type doped gallium arsenide substrate.

[0012] The embodiment of the present invention provides another technical solution: a method for preparing a common anode data communication VCSEL chip based on a p-substrate, comprising the following steps:

[0013] S1, forming an epitaxial layer on a p-substrate;

[0014] S2, fabricating a ring-shaped connecting n-metal on the surface of the epitaxial layer, and etching a groove outside the n-metal using a dry method;

[0015] S3, performing oxidation after etching to form a light-emitting hole in the epitaxial layer;

[0016] S4, electroplating the front n-metal layer to form an n-electrode;

[0017] S5, etching the cutting lanes at the edge of the chip;

[0018] S6, isolating the electrodes on the front side and fabricating a p-pole metal layer to obtain a first p-electrode;

[0019] S7, then forming a second p-electrode on the back side of the p-substrate, and performing high-temperature alloying to make the first p-electrode and the second p-electrode conductive.

[0020] Furthermore, in the step S3, after the light exit hole is formed, an insulating layer is plated.

[0021] Furthermore, after the photolithography and etching are completed, ion implantation is performed to assist in defining the current limiting region, and then the step S4 is performed.

[0022] Compared with the existing technology, the beneficial effect of the present invention is: by making an epitaxial layer on a p-substrate and then making contact layers of p-type and n-type metals, compared with the traditional common cathode structure, this common anode structure converts the main carriers of signal modulation from holes to electrons, thereby reducing the overall effective carrier mass, which is conducive to achieving higher modulation bandwidth and modulation rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A schematic diagram of a partial structure of the front side of a p-substrate-based common anode data communication VCSEL chip provided by an embodiment of the present invention;

[0024] Figure 2 A schematic vertical cross-sectional view of a p-substrate-based common anode data communication VCSEL chip provided in an embodiment of the present invention;

[0025] In the figure numerals: 1-n electrode; 2-first p electrode; 3-electrode isolation region; 5-p substrate; 6-p-DBR region; 7-active region; 8-n-DBR region; 9-light output hole; 10-insulating layer; 11-oxide layer. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] See also Figure 1 and Figure 2 An embodiment of the present invention provides a common anode data communication VCSEL chip based on a p-substrate 5, comprising a p-substrate 5 and an epitaxial layer formed on the p-substrate 5. An n-electrode 1 and a first p-electrode 2 are formed on the surface of the epitaxial layer away from the p-substrate 5. The n-electrode 1 and the first p-electrode 2 are separated by an electrode isolation region 3. A second p-electrode is formed on the surface of the p-substrate 5 away from the epitaxial layer. The first p-electrode 2 and the second p-electrode are electrically conductive. In this embodiment, by forming an epitaxial layer on the p-substrate 5 and then forming contact layers of p-type and n-type metals, this common anode structure converts the main carriers of signal modulation from holes to electrons compared to the traditional common cathode structure, thereby reducing the overall effective carrier mass and facilitating higher modulation bandwidth and modulation rate. Preferably, the epitaxial layer includes a p-DBR region 6, an active region 7, and an n-DBR region 8, which are sequentially grown on the p-substrate 5. Specifically, this chip focuses on changing the epitaxial wafer structure, namely, first growing the p-DBR region 6 on a p-type doped gallium arsenide (p-GaAs) substrate, and then growing the active region 7 and n-DBR region 8. The subsequent wafer process limits the conductive channel and forms the contact layer of the p-type and n-type metals. In traditional technology, if you want to achieve the effect of this application, you need to optimize the epitaxial structure based on the traditional common cathode, such as increasing the differential gain and photon concentration of the active region 7. However, the space for further optimization is limited, and it is impossible to achieve higher modulation bandwidth and modulation rate.

[0028] As an optimization solution of the embodiment of the present invention, please refer to Figure 1 The epitaxial layer has a light exit hole 9 that sequentially penetrates the p-DBR region 6, the active region 7, and the n-DBR region 8. The light exit surface of the light exit hole 9 is opened on the n-DBR region 8, and the light exit surface is set in the n-electrode 1. The light exit hole 9 is designed to emit light. Figure 2 As shown, the active layer and the n-DBR region 8 are separated by an oxide layer 11. The oxide layer 11 has an opening in the middle, which is located at the position of the light exit hole 9. After oxidation in a wet water oxygen furnace, the oxide layer 11 defines the position of the light exit hole 9. Preferably, an insulating layer 10 is provided on the n-DBR region 8. The insulating layer 10 is a silicon nitride insulating layer 10. After the light exit hole 9 is formed, the silicon nitride insulating layer 10 is first plated.

[0029] See also Figure 1 and Figure 2An embodiment of the present invention provides a method for preparing a common anode data communication VCSEL chip based on a p-substrate 5, comprising the following steps: S1, forming an epitaxial layer on the p-substrate 5; S2, forming a ring-shaped connecting n-metal on the surface of the epitaxial layer, and etching a groove on the outside of the n-metal using a dry method; S3, oxidizing after etching to form a light output hole 9 in the epitaxial layer; S4, electroplating the front n-metal layer to form an n-electrode 1; S5, etching a cutting path at the edge of the chip; S6, isolating the electrode on the front (i.e., the electrode isolation area 3), and forming a p-pole metal layer to obtain a first p-electrode 2; S7, then forming a second p-electrode on the back of the p-substrate 5, and performing high-temperature alloying to make the first p-electrode 2 and the second p-electrode conductive. In this embodiment, by forming an epitaxial layer on a p-type substrate 5 and then forming contact layers of p-type and n-type metals, this common anode structure converts the main carriers of the signal modulation from holes to electrons compared to the traditional common cathode structure, thereby reducing the overall effective carrier mass and facilitating the realization of higher modulation bandwidth and modulation rate. Preferably, the epitaxial layer includes a p-DBR region 6, an active region 7, and an n-DBR region 8, which are sequentially grown on the p-type substrate 5. Specifically, this chip focuses on changing the epitaxial wafer structure, namely, first growing the p-DBR region 6 on a p-type doped gallium arsenide (p-GaAs) substrate, and then growing the active region 7 and n-DBR region 8. The subsequent wafer fabrication process limits the conductive channel and forms contact layers of p-type and n-type metals. In conventional technology, if one wants to achieve the effects of this application, it is necessary to optimize the epitaxial structure based on the traditional common cathode, such as increasing the differential gain and photon concentration of the active region 7. However, the room for further optimization is limited, and it is impossible to achieve higher modulation bandwidth and modulation rate. Preferably, the p-DBR region 6, active region 7, and n-DBR region 8 are sequentially grown on a p-type doped gallium arsenide (p-GaAs) substrate using MOCVD or MBE. Preferably, in step S3, after forming the light exit hole 9, an insulating layer 10 is plated. After photolithography and etching are completed, ion implantation is performed to assist in defining the current confinement region, and then step S4 is performed. In this embodiment, after all steps are completed, the chip is cut to complete the preparation.

[0030] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A common anode data communication VCSEL chip based on a p-substrate, characterized by: The invention comprises a p-substrate and an epitaxial layer formed on the p-substrate, wherein an n-electrode and a first p-electrode are formed on a surface of the epitaxial layer away from the p-substrate, the n-electrode and the first p-electrode are separated by an electrode isolation region, a second p-electrode is formed on a surface of the p-substrate away from the epitaxial layer, the first p-electrode and the second p-electrode are conductive, the epitaxial layer comprises a p-DBR region, an active region and an n-DBR region grown sequentially on the p-substrate, the epitaxial layer comprises a light exit hole that sequentially penetrates the p-DBR region, the active region and the n-DBR region, the light exit surface of the light exit hole is opened on the n-DBR region, and the light exit surface is arranged in the n-electrode.

2. The p-substrate-based common anode data communication VCSEL chip according to claim 1, characterized in that: The active layer and the n-DBR region are separated by an oxide layer. An opening is provided in the middle of the oxide layer, and the position of the opening is the position of the light exit hole.

3. The p-substrate-based common anode data communication VCSEL chip according to claim 1, characterized in that: An insulating layer is provided on the n-DBR region.

4. The p-substrate-based common anode data communication VCSEL chip according to claim 3, characterized in that: The insulating layer is a silicon nitride insulating layer.

5. The p-substrate-based common anode data communication VCSEL chip according to claim 1, characterized in that: The p-substrate is a p-type doped gallium arsenide substrate.

6. A method for preparing a common anode data communication VCSEL chip based on a p-substrate, characterized in that: The method for preparing a chip according to any one of claims 1 to 5 comprises the following steps: S1, forming an epitaxial layer on a p-substrate; S2, fabricating a ring-shaped connecting n-metal on the surface of the epitaxial layer, and etching a groove outside the n-metal using a dry method; S3, performing oxidation after etching to form a light-emitting hole in the epitaxial layer; S4, electroplating the front n-metal layer to form an n-electrode; S5, etching the cutting lanes at the edge of the chip; S6, isolating the electrodes on the front side and fabricating a p-pole metal layer to obtain a first p-electrode; S7, then forming a second p-electrode on the back side of the p-substrate, and performing high-temperature alloying to make the first p-electrode and the second p-electrode conductive.

7. The method for preparing a p-substrate-based common-anode data communication VCSEL chip according to claim 6, wherein: In the step S3, after the light exit hole is formed, an insulating layer is plated.

8. The method for preparing a p-substrate-based common anode data communication VCSEL chip according to claim 7, wherein: After the photolithography and etching are completed, ion implantation is performed to assist in defining the current limiting region, and then the step S4 is performed.

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