Controller design method for interleaved parallel converters in DC microgrid based on differential flatness

Abstract

The present invention discloses a controller design method for a DC microgrid interleaved parallel converter based on differential flatness. Aiming at the problems of reduced stability of a boost system with a constant power load and deterioration of transient performance when disturbed, an interleaved parallel Boost converter is selected as a power converter connecting an input source and a load. The current inner loop design adopts differential flatness control, and a switch control law is obtained according to a state equation of the system, and a reasonable selection basis is provided for the adjustment parameters of the current error. The voltage outer loop design adopts global fast terminal sliding mode control, and a reference value of the inductor current of each phase is determined according to a sliding mode. The sliding mode control law does not contain a switching function, which reduces the difficulty of parameter adjustment. The control strategy of the controller designed by the present invention not only ensures the steady-state operation of the constant power system, but also enhances the robustness while meeting the rapidity requirement.

Description

Technical Field

[0001] The invention belongs to the technical field of converters, and in particular relates to a controller design method for a DC microgrid interleaved parallel converter based on differential flatness. Background Art

[0002] As the greenhouse effect and energy consumption become increasingly serious, measures are taken to transition from fossil energy such as coal to primary energy such as solar energy, wind energy, and fuel cells to gradually achieve low carbon. Among them, primary energy has the advantages of being clean and renewable, but its output voltage is low and easy to fluctuate. In order to match the stable operation of the load and input source, it needs to be connected to the DC bus through a boost converter. Power converters such as high-gain Boost converters, interleaved Boost Converters (IBC), and dual-input Boost converters have the advantages of reducing output ripple and improving converter efficiency and are widely used. Among them, interleaved parallel converter control is suitable for power supply occasions with high power, high precision, and low output ripple. The parallel technology divides the total power supply into several power modules, reducing the switching loss of the power device. The interleaved technology delays the N switch modules by 1 / N cycles respectively, which can reduce the output ripple.

[0003] like Figure 1 The figure shows the structure of a DC microgrid, which consists of an input source, a power converter, and a load. The load includes a constant power load (CPL) connected to the DC bus through a converter and a constant resistance load (CRL) directly connected to the bus voltage. The constant power load exhibits a negative impedance characteristic (i.e., Δv dc / Δi o <0), which will reduce the stability of system operation. In addition, the right half plane zero point in the transient mathematical model of the boost DC-DC converter causes the negative regulation of the output voltage, which will reduce the transient performance of the system. Therefore, it is particularly important to study the control method that can improve the stability and transient performance of the boost system with constant power load.

[0004] Scholars at home and abroad have conducted extensive research on bus voltage control of constant power systems. The literature Jusoh A, Saiful M, Sutikno T. DC bus stabilization using passive damping network indistributed power system with constant power load [J]. 2019 adopts a passive damping control method to add additional damping in the circuit to reduce the negative impedance effect of CPL, but this method brings power loss, which is not conducive to practical industrial applications. In order to improve system stability without affecting efficiency, nonlinear controls such as differential flatness based control (DFBC), sliding mode control, and adaptive control are widely used. The literature Thounthong P, Mungporn P, Guilbert D, et al. Design and control of multiphase interleaved boost converters-based on differential flatness theory for PEM fuel cell multi-stack applications [J]. International Journal of Electrical Power & Energy Systems, 2021, 124: 106346 adopts differential flatness control to design the voltage outer loop and the inductor current inner loop respectively, which improves the transient performance of the system. Moreover, differential flat control does not require solving differential equations when obtaining feedforward control through inverse dynamics equations, so it is easy to implement, but its modeling depends on the accurate model of the system; the literature Martinez-Trevino, Blan CA, Aroudi E, et al. Sliding-mode control of a boost converter under constant power loading conditions [J]. IET Power Electronics, 2019 introduces sliding mode control into the boost system with CPL to improve robustness. The integral term contained in the sliding surface of the global fast terminal sliding mode control (GFTSM) avoids the output steady-state error existing in traditional sliding mode control, ensures that the system converges within a finite time, and the sliding mode design is independent of the object parameters, but the sliding mode control has limited ability to suppress the system from a wide range of load disturbances. Summary of the invention

[0005] The purpose of the present invention is to provide a controller design method for a DC microgrid interleaved parallel converter based on differential flatness, which not only ensures the steady-state operation of the constant power system, but also enhances the robustness while meeting the rapidity requirements.

[0006] The technical solution adopted by the present invention is a controller design method for a DC microgrid interleaved parallel converter based on differential flatness, which specifically includes the following steps:

[0007] Step 1: Modeling Interleaved Parallel Boost Converters

[0008] The staggered parallel Boost converter model includes a capacitor C, a resistive load R and a constant power load are respectively connected in parallel to the capacitor C, and branches a and b are also respectively connected in parallel to the capacitor C. Branch a includes a power switch tube S1 and a diode D1 connected in sequence. The power switch tube S1 and the diode D1 are respectively connected at both ends of the capacitor C. An input voltage is connected in series between the power switch tube S1 and the diode D1. The connection end of the power switch tube S1 and the capacitor C is also connected to the input voltage. Branch b includes a power switch tube S2 and a diode D2 connected in sequence. The power switch tube S2 and the diode D2 are respectively connected at both ends of the capacitor C. An input voltage is connected in series between the power switch tube S2 and the diode D2. The connection end of the power switch tube S2 and the capacitor C is also connected to the input voltage. S1 and S2 are power switch tubes, and the two are turned on with a phase difference of 180°.

[0009] Step 2: Voltage outer loop controller design

[0010] The voltage outer loop is designed by using global fast terminal sliding mode with capacitor energy function, which not only ensures that the system converges to the equilibrium state quickly within a limited time, but also does not contain switching items, reducing the complexity of sliding mode parameter adjustment.

[0011] Step 3: Design of current inner loop controller.

[0012] The differential flatness theory is used to design the current inner loop based on the inductor current error to ensure that the inductor current follows the reference trajectory quickly and accurately, and the current error parameters are designed.

[0013] The present invention is also characterized in that:

[0014] In step 1, the mathematical model of the interleaved parallel Boost converter system is obtained based on the state space averaging method:

[0015]

[0016] In formula (1): v in is the input voltage signal, v o is the voltage signal across the capacitor, i ois the load side current, P CPL is the power value of the constant power load, i L1 、i L2 are the current signals of the inductors L1 and L2 respectively, u1 and u2 are the on-duty ratios of the switch elements S1 and S2 respectively, and u1=u2.

[0017] Step 2 is as follows:

[0018] The capacitance energy is used to construct the sliding surface, and the capacitance energy function is assumed to be:

[0019]

[0020] When the voltage outer loop system stably follows the energy function reference value y vref When the bus voltage tracks the reference voltage v oref , the relationship between the parameters in the steady state is:

[0021]

[0022] Combining equations (1) to (3), we get:

[0023]

[0024] Let e ​​= y vref -y v , x2=e, the voltage outer loop system model is expressed as

[0025]

[0026] In formula (5): f(x) = i o v o , g(x)=-2v in ,u v is the voltage loop control variable and u v =i Lref ;

[0027] The global fast terminal sliding surface s of the voltage outer loop system is designed as

[0028]

[0029] In formula (6), s0 is the sliding surface independent variable and s0=x1, α and β are positive numbers, and c satisfies 0 <c<1;

[0030] Derivation of equation (6) yields the approach motion expression:

[0031]

[0032] Considering the voltage outer loop model established by equation (7), in the approaching stage The outer loop control law obtained by equivalent control is:

[0033]

[0034] When the system reaches and maintains on the sliding surface s, s = 0 is satisfied. At this time, equation (6) gives

[0035]

[0036] From equation (9) in step 2, it can be seen that when the voltage outer loop system is far away from the equilibrium point, that is, |s0|≥1, the system convergence speed is adjusted by the adjustment equation plays a major role; when the voltage outer loop system approaches the equilibrium point, that is, |s0|<1, the system convergence speed is controlled by the adjustment formula Therefore, by adjusting the control parameters α, β, and c, the system state can quickly converge to the equilibrium state within a globally limited time.

[0037] Step 3 is as follows:

[0038] The current inner loop adopts differential flat control to ensure that the inductor current is flat and quickly follows the reference value of the current. When the two-phase interleaved Boost converter is in steady-state current sharing, the inductor current of each phase has the following relationship:

[0039]

[0040] In formula (12): i Lref1 、i Lref2 i L1 、i L2 Reference value of

[0041] According to the design requirement of the inner loop inductor current flat output, the inductor current is selected as the flat output yc and the state variable x c ,Right now

[0042] x c =y c =[i L1 i L2 ] T =ψ x (y c ) (13)

[0043] In formula (13): x (y c ) is x c About y c The mapping function of

[0044] According to equations (1) and (13), the flat output yc and its derivative constitute the input variable u c The expression is

[0045]

[0046] In formula (14): for u c About y c The mapping function of .

[0047] Equations (13) and (14) meet the flatness requirements of the system, and the flat output y c It is easy to get the reference trajectory y of the flat output cd =[i L1ref i L2ref ] T ,,when Precisely follow its reference trajectory When c and The deviation between and the derivative and integral of the deviation have the following relationship:

[0048]

[0049] In formula (15): K1, K2 are feedback gain matrices;

[0050] The control object is equivalent to a second-order system to eliminate the steady-state error, and the closed-loop transfer function of the current inner loop system is:

[0051]

[0052] In formula (16), ξ c is the damping ratio of the second-order system, ω nc is the natural frequency;

[0053] Combining equation (15) and equation (16), we get

[0054]

[0055] In formula (17): e c =y c -y cd ;

[0056] Therefore, from formula (17) we get

[0057]

[0058] Combining equations (15) and (18), the differential term of the flat output variable is

[0059]

[0060] In step 3, it can be seen from equation (19) that when K1 and K2 are positive definite matrices, the inner loop system is stable and the controller parameter ξc and ω nc The selection of determines the transient characteristics of the inner loop controller system. When ξ is fixed, ω nc The larger the value, the faster the system responds, but nc It cannot be increased infinitely. The system stability also requires the bandwidth of the current loop system, that is, the oscillation frequency ω nc Much smaller than the system switching frequency f s , that is, the following relationship is satisfied

[0061] ω nc <<2πf s (20).

[0062] The beneficial effects of the present invention are:

[0063] The present invention is based on a controller design method for a DC microgrid interleaved parallel converter with differential flatness. Aiming at the problems of reduced stability of a boost system with a constant power load and deterioration of transient performance when disturbed, an interleaved parallel Boost converter is selected as a power converter connecting an input source and a load. The current inner loop design adopts differential flatness control, and a switching control law is obtained based on the state equation of the system, and a reasonable selection basis is provided for the adjustment parameters of the current error. The voltage outer loop design adopts global fast terminal sliding mode control, and a reference value of the inductor current of each phase is determined according to the sliding mode. The sliding mode control law does not contain a switching function, which reduces the difficulty of parameter adjustment. The control strategy of the controller designed by the present invention not only ensures the steady-state operation of the constant power system, but also enhances the robustness while meeting the rapidity requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 It is the DC microgrid structure diagram;

[0065] Figure 2 It is the topological structure diagram of the interleaved parallel Boost converter circuit;

[0066] Figure 3 It is a structural block diagram of the outer loop terminal sliding mode and inner loop differential flat control of the present invention;

[0067] Figure 4 It is the overall control block diagram built in the PSIM simulation software;

[0068] Figure 5 It is the response curve of output error when sliding mode coefficients α and β change;

[0069] Figure 6 It is the response curve of the output error when the sliding mode index c changes;

[0070] FIG. 7 is a bus voltage waveform diagram of circuit parameter perturbation, wherein FIG. 7( a ) is a bus voltage simulation waveform diagram of the output response of the inductance parameter perturbation, and FIG. 7( b ) is a bus voltage simulation waveform diagram of the output response of the capacitance parameter perturbation;

[0071] FIG8 is a bus voltage waveform diagram for load disturbance resistance, wherein FIG8(a) is a bus voltage variation waveform diagram, FIG8(b) is an output current variation waveform diagram, FIG8(c) is a local enlarged diagram of the bus voltage when the resistive load is reduced, and FIG8(d) is a local enlarged diagram of the bus voltage when the resistive load is increased;

[0072] FIG9 is a bus voltage waveform diagram of the constant power load disturbance resistance, wherein FIG9(a) is a constant power load P CPL The output power waveform under disturbance, Figure 9(b) is P CPL Figure 9(c) shows the bus voltage waveform of the CPI control strategy during the sudden change. CPL Figure 9(d) shows the bus voltage waveform of CDFBC control strategy during sudden change. CPL Bus voltage waveform of TSMFC control strategy during mutation. DETAILED DESCRIPTION

[0073] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] The controller design method of the differentially flat DC microgrid interleaved parallel converter of the present invention specifically includes the following steps:

[0075] Step 1: Modeling Interleaved Parallel Boost Converters

[0076] like Figure 2 As shown, the staggered parallel Boost converter model includes a capacitor C, a resistive load R and a constant power load are respectively connected in parallel to the capacitor C, and branches a and b are also respectively connected in parallel to the capacitor C. Branch a includes a power switch tube S1 and a diode D1 connected in sequence. The power switch tube S1 and the diode D1 are respectively connected at both ends of the capacitor C. An input voltage is connected in series between the power switch tube S1 and the diode D1. The connection end of the power switch tube S1 and the capacitor C is also connected to the input voltage. Branch b includes a power switch tube S2 and a diode D2 connected in sequence. The power switch tube S2 and the diode D2 are respectively connected at both ends of the capacitor C. An input voltage is connected in series between the power switch tube S2 and the diode D2. The connection end of the power switch tube S2 and the capacitor C is also connected to the input voltage. S1 and S2 are power switch tubes, and the two are turned on with a phase difference of 180°.

[0077] The mathematical model of the interleaved parallel Boost converter system based on the state space averaging method is:

[0078]

[0079] In formula (1): v in is the input voltage signal, v o is the voltage signal across the capacitor, i o is the load side current, P CPL is the power value of the constant power load, i L1 、i L2 are the current signals of the inductors L1 and L2 respectively, u1 and u2 are the on-duty ratios of the switch elements S1 and S2 respectively, and u1=u2.

[0080] The design of the controller of the present invention is as follows Figure 3 As shown in the figure, it consists of two parts: the terminal sliding mode voltage outer loop and the differential flat current inner loop.

[0081] Step 2: Voltage outer loop controller design

[0082] The voltage outer loop is designed by using global fast terminal sliding mode with capacitor energy function, which not only ensures that the system converges to the equilibrium state quickly within a limited time, but also does not contain switching items, reducing the complexity of sliding mode parameter adjustment.

[0083] Step 2 is as follows:

[0084] The capacitance energy is used to construct the sliding surface, and the capacitance energy function is assumed to be:

[0085]

[0086] When the voltage outer loop system stably follows the energy function reference value y vref When the bus voltage tracks the reference voltage v oref , the relationship between the parameters in the steady state is:

[0087]

[0088] Combining equations (1) to (3), we get:

[0089]

[0090] Let e ​​= y vref -y v , x2=e, the voltage outer loop system model is expressed as

[0091]

[0092] In formula (5): f(x) = i o v o , g(x)=-2v in ,u v is the voltage loop control variable and uv =i Lref ;

[0093] The global fast terminal sliding surface s of the voltage outer loop system is designed as

[0094]

[0095] In formula (6), s0 is the sliding surface independent variable and s0=x1, α and β are positive numbers, and c satisfies 0 <c<1;

[0096] Derivation of equation (6) yields the approach motion expression:

[0097]

[0098] Considering the voltage outer loop model established by equation (7), in the approaching stage The outer loop control law obtained by equivalent control is:

[0099]

[0100] When the system reaches and maintains on the sliding surface s, s = 0 is satisfied. At this time, equation (6) gives

[0101]

[0102] From formula (9), we can see that when the voltage outer loop system is far away from the equilibrium point, that is, |s0|≥1, the system convergence speed is adjusted by the formula plays a major role; when the voltage outer loop system approaches the equilibrium point, that is, |s0|<1, the system convergence speed is controlled by the adjustment formula Therefore, by adjusting the control parameters α, β, and c, the system state can quickly converge to the equilibrium state within a globally limited time.

[0103] Step 3: Design of current inner loop controller.

[0104] The differential flatness theory is used to design the current inner loop based on the inductor current error to ensure that the inductor current follows the reference trajectory quickly and accurately, and the current error parameters are designed.

[0105] Differential flat control is achieved by selecting a flat output and its derivatives y, y (1) , …, y (n) To linearly represent the original state variable x and input variable u, assuming that there is a nonlinear system, its model can be expressed as

[0106]

[0107] And the flat output y can be found, and the state variable x and input u can be expressed as

[0108]

[0109] Then the system is said to be flat. In formula (11), a and b are the derivative orders of the flat output y, and x∈R m , u∈R n , y∈R n , m, n are positive integers, ψ x (·),ψ u (·) is the mapping function;

[0110] Step 3 is as follows:

[0111] The current inner loop adopts differential flat control to ensure that the inductor current is flat and quickly follows the reference value of the current. When the two-phase interleaved Boost converter is in steady-state current sharing, the inductor current of each phase has the following relationship

[0112]

[0113] In formula (12): i Lref1 、i Lref2 i L1 、i L2 Reference value of

[0114] According to the design requirement of flat output of inner loop inductor current, the inductor current is selected as the flat output quantity y c and the state variable x c ,Right now

[0115] x c =y c =[i L1 i L2 ] T =ψ x (y c ) (13)

[0116] In formula (13): x (y c ) is x c About y c The mapping function of .

[0117] According to equations (1) and (13), the flat output y c The input variable u is composed of its derivative c The expression of (feedforward control) is

[0118]

[0119] Where: for u c About y c The mapping function of .

[0120] From the analysis of formula (11), we can see that formula (13) and formula (14) meet the flatness requirements of the system, and the flat output y c It is easy to get the reference trajectory y of the flat output cd =[i L1ref i L2ref ] T ,,when Precisely follow its reference trajectory When c and The deviation between and the derivative and integral of the deviation have the following relationship:

[0121]

[0122] In formula (15): K1, K2 are feedback gain matrices;

[0123] The control object is equivalent to a second-order system to eliminate the steady-state error, and the closed-loop transfer function of the current inner loop system is:

[0124]

[0125] In formula (16), ξ c is the damping ratio of the second-order system, ω nc is the natural frequency;

[0126] Combining equation (15) and equation (16), we get

[0127]

[0128] In formula (17): e c =y c -y cd ;

[0129] Therefore, from formula (17) we get

[0130]

[0131] Combining equations (15) and (18), the differential term of the flat output variable is

[0132]

[0133] From equation (19), we can see that when K1 and K2 are positive definite matrices, the inner loop system is stable and the controller parameter ξ c and ω nc The selection of determines the transient characteristics of the inner loop controller system. When ξ is fixed, ω nc The larger the value, the faster the system responds, but nc It cannot be increased infinitely. The system stability also requires the bandwidth of the current loop system, that is, the oscillation frequency ωnc Much smaller than the system switching frequency f s , that is, the following relationship is satisfied

[0134] ω nc <<2πf s (20).

[0135] Simulation Verification

[0136] In order to verify the effectiveness and superiority of the controller control strategy designed by the controller design method of the DC microgrid interleaved parallel converter based on differential flatness in the present invention, a PSIM simulation model was established. The control strategy adopted terminal sliding mode-flat control (TSMFC) and was compared with traditional cascade proportional-integral (CPI) control and cascade differential flat control (Cascade DFBC, CDFBC).

[0137] (I) Simulation experiment construction

[0138] In the PSIM simulation software, Figure 4 The overall structure block diagram is shown in the figure. According to the application of IBC running in low ripple and high current, the circuit parameter design is shown in Table 1; the equivalent constant power load connected to the DC bus is composed of a closed-loop DC / DC converter cascaded with the bus voltage, and the parameter design is shown in Table 2.

[0139] Table 1 Parameters of two-phase IBC circuit

[0140]

[0141] Table 2 Parameters of cascade converter parameters

[0142]

[0143] To ensure the fairness of the simulation experiment, each controller is selected to have the same damping ratio and bandwidth as much as possible. The controller parameters are shown in Table 3.

[0144] Table 3 Controller parameters

[0145]

[0146]

[0147] Controller 2: In order to reflect the rapidity of the nonlinear control strategy, traditional CPI control is used as controller 2.

[0148] Current reference value i in CPI control Lref The inner loop expression of CPI control is indirectly determined by the expected value of the output energy function of the voltage loop:

[0149]

[0150] In formula (21): k pi , k ii are the proportional and integral coefficients of the current loop respectively; i Lref is the reference value of the inner current loop and P ref is the input power reference value, and its expression is

[0151] P ref =k pv (y vref -y v )+k iv ∫(y vref -y v )dt (22)

[0152] In formula (22): k pv , k iv They are the proportional and integral coefficients of the voltage loop respectively.

[0153] Select the current loop PI parameter as k pi =0.1, k ii =12.5; Based on the requirements of the closed-loop system for steady-state performance, the voltage loop PI parameter is selected as k pv =0.2, k iv =100.

[0154] Controller 3: In order to reflect the suppression of the terminal sliding mode on the sensitivity of system parameters, a CDFBC controller based on IBC is designed.

[0155] The inner loop control law of the controller is the same as that of the TSMFC controller, and the outer loop control law is

[0156]

[0157] In formula (23), the voltage outer loop output variable and the control variable are defined as u v =i Lref .

[0158] State variable x v Select bus voltage v o , then the state variable can be expressed by the output variable as

[0159]

[0160] In order to ensure that the output energy function can accurately follow its reference value y vref , replace the formula (23) Designed by the linear feedback law, it can be expressed as

[0161]

[0162] In formula (25), K3 and K4 are controller parameters.

[0163] It can be seen from formula (25) that when K3>0, K4>0, the error between the output energy function and its reference value converges to zero asymptotically. K3 and K4 can be combined with closed-loop dynamic performance parameters to determine the transient performance, which can be expressed as

[0164]

[0165] In formula (26): v and ω nv are the voltage loop damping ratio and natural frequency respectively.

[0166] Considering the stability and dynamic response comprehensively, we select ξ v =1,ω nv =628.32, at this time K3=1256.64, K4=394784.18.

[0167] (II) Sliding mode parameter selection

[0168] In traditional sliding mode control, in order to suppress the chattering phenomenon of sliding mode control, switching functions are usually added to the control law, but the number of sliding mode parameters is increased, which increases the complexity of parameter adjustment. The outer loop sliding mode in the controller proposed in this paper only contains three sliding mode parameters in the sliding surface, which improves the convergence characteristics of the traditional sliding mode and can achieve the system reaching the equilibrium point within a limited time. Next, the influence of selecting different sliding mode parameters on the arrival time and convergence speed of the system is verified.

[0169] Figure 5 The response curve of the output error when the sliding mode index c=9 / 11 is fixed and the sliding mode coefficients α and β change.

[0170] analyze Figure 5 It can be seen that there is no steady-state error in the system output, that is, the system converges within a finite time. As α and β continue to increase, the convergence speed of the system also increases and the arrival time is shortened. However, α and β cannot increase indefinitely. From the error curve when α=1000, β=2000, it can be seen that the system overshoots, which will cause fluctuations in the system output. Therefore, this paper selects the sliding mode coefficients α=500, β=600.

[0171] Figure 6 The response curve of the output error when the sliding mode coefficient α=500, β=600 is fixed and the sliding mode index c changes. Figure 6It can be seen that as c increases, the convergence speed of the system decreases and the arrival time increases. Considering the transient performance and chattering influence of the system, the sliding mode index c = 9 / 11 is selected.

[0172] (III) Ability to resist circuit parameter perturbations

[0173] The converter is easily affected by factors such as temperature and component aging in actual working conditions, which will cause deviations between the actual values ​​of the capacitors and inductors in the circuit and the nominal values. Adding GFTSM to the controller involved in the present invention reduces the sensitivity of the controller to circuit parameter perturbations.

[0174] The inductor and capacitor parameters are designed to be within the perturbation range of ±15% of their rated values ​​to verify the sensitivity of the TSMFC controller to the circuit parameters. First, except for the capacitor, all other parameters are fixed, and the capacitor parameters are taken as 153μH, 180μH, and 207μH respectively. The bus voltage simulation waveform of the bus voltage is reduced from 110V to 90V in 0.1s as shown in Figure 7(a). Secondly, except for the inductor, all other parameters are fixed, and the inductor parameters are taken as 323μF, 380μF, and 437μF respectively. The bus voltage simulation waveform of the bus voltage is increased from 110V to 130V in 0.1s as shown in Figure 7(b).

[0175] From the analysis of Figure 7, it can be seen that the controller returns to the new steady-state value within 0.4ms under the inductance parameter perturbation, and returns to the new steady-state value within 0.2ms under the capacitance parameter perturbation with basically no overshoot. Therefore, the control strategy of the controller designed in the present invention reduces the sensitivity of the system to the circuit parameters, so that the circuit parameter perturbation has basically no effect on the system.

[0176] (IV) Anti-disturbance verification

[0177] 1) Sudden change of resistive load

[0178] The expected bus voltage in IBC is set to 110V, the constant power load is set to 360W, the resistive load is suddenly reduced from 20W to 10W in 0.2s, and suddenly increased from 10W to 20W in 0.3s. The system simulation of CPI, CDFBC and TSMFC control strategies under load disturbance is shown in Figure 8. Figure 8(a) is the bus voltage waveform during load disturbance, Figure 8(b) is the output current waveform corresponding to the disturbance, and Figures 8(c) and (d) are partial enlarged views of the bus voltage during sudden load reduction and sudden load increase, respectively.

[0179] Analysis of Figure 8 shows that when the load suddenly decreases, the overshoot of the bus voltage transition to the expected value of 6.5V is smaller than that of CPI control, which produces an overshoot of 13.2V, but the output regulation time under the TSMFC control strategy is shorter; when the load suddenly increases, the overshoot of the bus voltage transition to the expected value of 4.7V is smaller than that of CPI control, which produces an overshoot of 14.6V, but the output regulation time under the TSMFC control strategy is shorter. Therefore, the TSMFC strategy has better transient performance when subjected to resistive load disturbances.

[0180] 2) Constant power load sudden change

[0181] The expected bus voltage in IBC is set to 110V, the resistive load is fixed to 10W, the constant power load is suddenly reduced from 40W to 120W at 0.5s, suddenly increased from 120W to 320W at 0.6s, and suddenly reduced from 320W to 40W at 0.7s. The system output simulation of CPI, CDFBC and TSMFC control strategies under constant power load disturbance is shown in Figure 9. Among them, Figure 9 (a) is the total output power waveform under constant power load disturbance, and Figures 9 (b), (c) and (d) are the disturbed bus voltage waveforms under CPI, CDFBC and TSMFC control strategies. Table 4 compares the output performance of three different control strategies under constant power load disturbance.

[0182] From the analysis of Figure 9 and Table 4, it can be seen that the disturbance at 0.5s causes the system DC bus fluctuation. The bus voltage fluctuation under the control strategy proposed in this paper is 0.98V, with the smallest overshoot and the shortest adjustment time.

[0183] Table 4 Output performance against constant power load disturbance

[0184]

[0185]

[0186] The equivalent constant power sudden increase disturbance at 0.6s causes the system DC bus fluctuation. The bus voltage fluctuation under the control strategy proposed in this paper is 2.30V, with the smallest overshoot and the shortest adjustment time. The equivalent constant power sudden increase disturbance at 0.7s causes the system DC bus fluctuation. The bus voltage fluctuation under the control strategy proposed in this paper is 3.04V, with the shortest adjustment time.

[0187] During the disturbance process of 0.4 to 0.8 s, we can see that P CPLBefore and after the disturbance, the bus voltage under the CPI control strategy showed low-frequency oscillation; the CDFBC control strategy also showed low-frequency oscillation after the disturbance; while the bus voltage under the control strategy proposed in this paper was basically stable. Therefore, the TSMFC control strategy controlled by the present invention enhances the robustness on the basis of CDFBC, making the bus voltage run smoothly and stably.

[0188] Aiming at the problems of reduced stability of the boost system with constant power load and deterioration of transient performance when disturbed, the controller designed in this invention adopts a cascade nonlinear control strategy consisting of GFTSM and DFBC. The simulation results show that:

[0189] (1) The system under the control strategy of the controller designed by the present invention has no steady-state error, and the increase of α and β in the sliding mode parameters is conducive to improving the transient performance of the system, and the decrease of parameter c is conducive to improving the transient performance of the system;

[0190] (2) The addition of global fast terminal sliding mode reduces the sensitivity of circuit parameter perturbations to the system, making the system output smoother;

[0191] (3) Compared with the CPI and CDFBC control strategies, the control strategy adopted by the present invention can optimize the dynamic performance of the system in resisting load disturbances and enhance the robustness of the system.

Claims

1. A controller design method for DC microgrid interleaved parallel converters based on differential flatness, characterized in that: The specific steps include: Step 1: Modeling Interleaved Parallel Boost Converters Step 2: Voltage outer loop controller design The voltage outer loop is designed by using global fast terminal sliding mode with capacitor energy function, which not only ensures that the system converges to the equilibrium state quickly within a limited time, but also does not contain switching items, reducing the complexity of sliding mode parameter adjustment. Step 2 is as follows: The capacitance energy is used to construct the sliding surface, and the capacitance energy function is assumed to be: (2) In formula (2), is the voltage signal across the capacitor, C is the capacitor C of the interleaved parallel Boost converter; When the voltage outer loop system stably follows the energy function reference value When the bus voltage tracks the reference voltage , the relationship between the parameters in the steady state is: (3) In formula (3), , Inductance , The current signal, , Switching elements , The on-duty ratio of Combining equations (1) to (3), we get: (4) In formula (4), is the input voltage signal, is the voltage signal across the capacitor, is the load side current; make , , , the voltage outer loop system model is expressed as: (5) In formula (5): , , is the voltage loop control variable and ; Global fast terminal sliding surface of voltage outer loop system s Designed for (6) In formula (6): is the sliding surface independent variable and , α and β are positive numbers, c Satisfy 0< c <1; Derivation of equation (6) yields the approach motion expression: (7) Considering the voltage outer loop model established by equation (7), in the approaching stage The outer loop control law obtained by equivalent control is: (8) When the system reaches and maintains the sliding surface s Time Satisfaction s =0, then from formula (6) we get (9)； Step 3: Design of current inner loop controller; The differential flatness theory is used to design the current inner loop based on the inductor current error to ensure that the inductor current follows the reference trajectory quickly and accurately, and the current error parameters are reasonably designed. Step 3 is as follows: The current inner loop adopts differential flat control to ensure that the inductor current is flat and quickly follows the reference value of the current. When the two-phase interleaved Boost converter is in steady-state current sharing, the inductor current of each phase has the following relationship: (12) In formula (12): They are Reference value of According to the design requirement of flat output of inner loop inductor current, the inductor current is selected as the flat output quantity. and state variables x c ,Right now (13) In formula (13): for about The mapping function of According to equations (1) and (13), the flat output The input variables are composed of The expression is (14) In formula (14): for about The mapping function of Equations (13) and (14) meet the flatness requirements of the system, and the flat output Easy to get a reference trajectory for flat output ,when Precisely follow its reference trajectory hour, and The deviation between and the derivative and integral of the deviation have the following relationship: (15) In formula (15): , is the feedback gain matrix; The control object is equivalent to a second-order system to eliminate the steady-state error, and the closed-loop transfer function of the current inner loop system is: (16) In formula (16), is the damping ratio of the second-order system, is the natural frequency; Combining equation (15) and equation (16), we get (17) In formula (17): ; Therefore, from formula (17) we get (18) Combining equations (15) and (18), the differential term of the flat output variable is (19)。 2. The controller design method for a DC microgrid interleaved parallel converter based on differential flatness according to claim 1 is characterized in that: Step 1 is specifically, the staggered parallel Boost converter model includes a capacitor C, a resistive load R and a constant power load are connected in parallel to the capacitor C, and a branch a and a branch b are connected in parallel to the capacitor C, and the branch a includes power switch tubes connected in sequence. and diode , power switch tube and diode Connected to both ends of capacitor C, power switch tube and diode The connection point is connected to the positive input terminal, the power switch tube The connection end with capacitor C is also connected to the negative input terminal. Branch b includes power switch tubes connected in sequence. and diode , power switch tube and diode Connected to both ends of capacitor C, power switch tube and diode The connection point is connected to the positive input terminal, the power switch tube The connection end with capacitor C is also connected to the negative input terminal. , The two are power switch tubes, and the phase difference between them is 180°. In step 1, the mathematical model of the interleaved parallel Boost converter system is obtained based on the state space averaging method: (1) In formula (1): is the input voltage signal, is the voltage signal across the capacitor, is the load side current, , is the power value of the constant power load, , Inductance , The current signal, , Switching elements , The on-duty ratio of .

3. The controller design method for a DC microgrid interleaved parallel converter based on differential flatness according to claim 1, characterized in that: From equation (9) in step 2, we can see that when the voltage outer loop system is far away from the equilibrium point, that is, , the system convergence speed is regulated by plays a major role; when the voltage outer loop system approaches the equilibrium point, that is, , the system convergence speed is regulated by plays a major role, therefore, by adjusting the control parameters α , β , Make the system state converge quickly to the equilibrium state within a globally limited time.

4. The controller design method for a DC microgrid interleaved parallel converter based on differential flatness according to claim 1, characterized in that: In step 3, it can be seen from formula (19) that: K 1. K 2 is a positive definite matrix, and the inner loop system is stable and the controller parameters and The selection of determines the transient characteristics of the inner loop controller system. ξ When fixed, The larger the value, the faster the system responds, but It cannot be increased infinitely. The system stability also requires the bandwidth of the current loop system, that is, the oscillation frequency. Much smaller than the system switching frequency f s , that is, the following relationship is satisfied (20)。

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