A common-mode current control method for a HERIC type non-isolated photovoltaic inverter

Abstract

The application discloses a common-mode current control method of a HERIC type non-isolated photovoltaic inverter, which comprises the following steps: detecting a switching tube S1 and a switching tube S3, and allowing the photovoltaic inverter to be grid-connected after detecting that the switching tube S1 and the switching tube S3 are normal. The common-mode current control method reduces the common-mode current of the non-isolated photovoltaic inverter caused by the parasitic capacitance of a photovoltaic module to the ground.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic grid-connected inverters and relates to a common-mode current control method for HERIC-type non-isolated photovoltaic inverters. Background Technology

[0002] Currently, low-power single-phase inverters typically employ non-isolated grid-connected photovoltaic (PV) inverters, which offer advantages such as high conversion efficiency, high power density, and low cost. Furthermore, non-isolated PV grid-connected inverters often utilize the HERIC topology, which offers good performance in terms of device cost, conversion efficiency, and leakage current. (Refer to...) Figure 1 As shown, in a transformerless, non-isolated HERIC topology photovoltaic grid-connected inverter system, a common-mode resonant circuit is formed due to the direct electrical connection between the grid (Vg) and the photovoltaic array 1, and the parasitic capacitance (Cm) between the photovoltaic array 1 and the ground (PE). This circuit consists of the parasitic capacitance, filter elements, and grid impedance. The varying common-mode voltage (Vcm) across the parasitic capacitance can excite this resonant circuit, generating a corresponding common-mode current. The presence of this common-mode current causes grid current distortion, electromagnetic interference, additional system losses, and safety hazards. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a common-mode current control method for HERIC-type non-isolated photovoltaic inverters, thereby reducing the common-mode current caused by the parasitic capacitance of photovoltaic modules to the ground in non-isolated photovoltaic inverters.

[0004] A common-mode current control method for a HERIC-type non-isolated photovoltaic inverter, the photovoltaic inverter including a HERIC inverter circuit, the HERIC inverter circuit including switches S1, S2, S3, S4, S5 and S6, wherein switches S1 and S2 are connected to form a first inverter bridge arm, and switches S3 and S4 are connected to form a second inverter bridge arm; the photovoltaic inverter also includes a first detection branch and a second detection branch, the first detection branch being connected between the midpoint of switches S1 and S2 and the negative DC bus, the second detection branch being connected between the midpoint of switches S3 and S4 and the negative DC bus, the first detection branch and the second detection branch each including multiple voltage divider resistors connected in series; the common-mode current control method includes: detecting switches S1 and S3, and allowing the photovoltaic inverter to connect to the grid after detecting that switches S1 and S3 are normal;

[0005] The specific steps for detecting the switching transistor S1 include:

[0006] (A1) Under the bus voltage, the switch S1 is not driven and the voltage between the voltage divider resistors of the first detection branch is sampled to obtain the first sample voltage. The first sample voltage is compared with the first threshold. If the first sample voltage is less than the first threshold, it is determined that the switch S1 has no short circuit fault.

[0007] The specific steps for detecting the switching transistor S3 include:

[0008] (B1) Under the bus voltage, the switch S3 is not driven and the voltage between the voltage divider resistors of the second detection branch is sampled to obtain a third sample voltage. The third sample voltage is compared with a third threshold. If the third sample voltage is less than the third threshold, it is determined that the switch S3 has no short circuit fault.

[0009] In some preferred embodiments, the step of detecting the switching transistor S1 further includes:

[0010] (A2) Under the bus voltage, the switch S1 is driven to sample the voltage between the voltage divider resistors of the first detection branch to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that the switch S1 is normally turned on.

[0011] The step of detecting the switching transistor S3 further includes:

[0012] (B2) Under the bus voltage, the switch S3 is driven to sample the voltage between the voltage divider resistors of the second detection branch to obtain a fourth sampling voltage. The fourth sampling voltage is compared with a fourth threshold. If the fourth sampling voltage is greater than the fourth threshold, it is determined that the switch S3 is normally turned on.

[0013] The photovoltaic inverter is allowed to connect to the grid after it is detected that there is no short circuit fault in the switching transistors S1 and S3 and they are conducting normally.

[0014] In a preferred embodiment, the second threshold is greater than the first threshold, and the fourth threshold is greater than the third threshold.

[0015] In a preferred embodiment, the first detection branch includes a first resistor, a second resistor, and a third resistor connected in series. One end of the first resistor is electrically connected to the midpoint between the switching transistors S1 and S2. The first sampling voltage and the second sampling voltage are obtained through the first resistor voltage divider sampling terminal connected to the midpoint between the second resistor and the third resistor.

[0016] In a preferred embodiment, the second detection branch includes a fourth resistor, a fifth resistor, and a sixth resistor connected in series. One end of the fourth resistor is electrically connected to the midpoint between the switching transistors S3 and S4. The third sampling voltage and the fourth sampling voltage are obtained through a second resistor voltage divider sampling terminal connected to the midpoint between the fifth resistor and the sixth resistor.

[0017] In some preferred embodiments, the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0018] In a preferred embodiment, the emitter of the switch S1 and the collector of the switch S2 are electrically connected, and the emitter of the switch S3 and the collector of the switch S4 are electrically connected.

[0019] In a preferred embodiment, the emitter of the switching transistor S5 is electrically connected to the midpoint of the first inverter bridge arm, the collector of the switching transistor S5 is electrically connected to the collector of the switching transistor S6, the emitter of the switching transistor S6 is electrically connected to the midpoint of the second inverter bridge arm, and diodes are connected in reverse parallel between the switching transistors S5 and S6.

[0020] A common-mode current control method for a HERIC-type non-isolated photovoltaic inverter, the photovoltaic inverter including a HERIC inverter circuit, the HERIC inverter circuit including switches S1, S2, S3, S4, S5 and S6, wherein switches S1 and S2 are connected to form a first inverter bridge arm, and switches S3 and S4 are connected to form a second inverter bridge arm; the photovoltaic inverter also includes a first detection branch, the first detection branch being connected between the midpoint of switches S1 and S2 and the negative DC bus, the first detection branch including multiple voltage divider resistors connected in series; the common-mode current control method includes: detecting switches S1, and connecting the photovoltaic inverter to the grid after detecting that switches S1 are normal;

[0021] The specific steps for detecting the switching transistor S1 include:

[0022] (A1) Under the bus voltage, the switch S1 is not driven and the voltage between the voltage divider resistors of the first detection branch is sampled to obtain the first sample voltage. The first sample voltage is compared with the first threshold. If the first sample voltage is less than the first threshold, it is determined that the switch S1 has no short circuit fault.

[0023] (A2) Under the bus voltage, the switch S1 is driven to sample the voltage between the voltage divider resistors of the first detection branch to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that the switch S1 is normally turned on.

[0024] In a preferred embodiment, the second threshold is greater than the first threshold, and the first detection branch includes a first resistor, a second resistor and a third resistor connected in series. One end of the first resistor is electrically connected to the midpoint of the switching transistors S1 and S2. The first sampling voltage and the second sampling voltage are obtained through the first resistor voltage divider sampling terminal connected to the midpoint of the second resistor and the third resistor.

[0025] A common-mode current control method for a HERIC-type non-isolated photovoltaic inverter, the photovoltaic inverter including a HERIC inverter circuit, the HERIC inverter circuit including switches S1, S2, S3, S4, S5 and S6, wherein switches S1 and S2 are connected to form a first inverter bridge arm, and switches S3 and S4 are connected to form a second inverter bridge arm; the photovoltaic inverter also includes a second detection branch, the second detection branch being connected between the midpoint of switches S3 and S4 and the negative DC bus, the second detection branch including multiple voltage divider resistors connected in series; the common-mode current control method includes: detecting switch S3, and connecting the photovoltaic inverter to the grid after detecting that switch S3 is normal;

[0026] The specific steps for detecting the switching transistor S3 include:

[0027] (B1) Under the bus voltage, the switch S3 is not driven and the voltage between the voltage divider resistors of the second detection branch is sampled to obtain a third sample voltage. The third sample voltage is compared with a third threshold. If the third sample voltage is less than the third threshold, it is determined that the switch S3 has no short circuit fault.

[0028] (B2) Under the bus voltage, the switch S3 is driven to sample the voltage between the voltage divider resistors of the second detection branch to obtain a fourth sampling voltage. The fourth sampling voltage is compared with a fourth threshold. If the fourth sampling voltage is greater than the fourth threshold, it is determined that the switch S3 is normally turned on.

[0029] In a preferred embodiment, the fourth threshold is greater than the third threshold, and the second detection branch includes a fourth resistor, a fifth resistor and a sixth resistor connected in series. One end of the fourth resistor is electrically connected to the midpoint of the switching transistors S3 and S4. The third sampling voltage and the fourth sampling voltage are obtained through the second resistor voltage divider sampling terminal connected to the midpoint of the fifth resistor and the sixth resistor.

[0030] The present invention adopts the above solution, which has the following advantages compared with the prior art:

[0031] The method of this invention detects the state of the switching transistors S1 and S3 of the HERIC topology before the inverter is connected to the grid to determine whether there is a short circuit fault. This can effectively avoid the common-mode current problem caused by the parasitic capacitance of the photovoltaic modules to the ground in non-isolated photovoltaic inverters due to short circuits in the switching transistors S1 and S3, reduce the common-mode current caused by the parasitic capacitance of the photovoltaic modules to the ground in non-isolated photovoltaic inverters, and also achieve the function of early detection, prevention and alarm. Attached Figure Description

[0032] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a topology diagram of a HERIC-type non-isolated photovoltaic inverter system.

[0034] Figure 2 This is a schematic diagram of the voltage divider resistors R1, R2, and R3.

[0035] Figure 3 The waveform diagram is shown when the S1 transistor is not driven.

[0036] Figure 4 The test waveform diagram when driving the S1 transistor.

[0037] Figure 5 This is a schematic diagram of the voltage divider resistors R4, R5, and R6.

[0038] Figure 6 The waveform diagram is shown when the S3 transistor is not driven.

[0039] Figure 7 The test waveform diagram when driving the S3 transistor. Detailed Implementation

[0040] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art. It should be noted that the description of these embodiments is for the purpose of aiding understanding the present invention, but does not constitute a limitation thereof. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0041] Figure 1The diagram shows a transformerless, non-isolated HERIC topology photovoltaic grid-connected inverter system. Because there is a direct electrical connection between the grid Vg and the photovoltaic array 1, and because there is a parasitic capacitance Cm between the photovoltaic array 1 and the ground PE, a common-mode resonant circuit is formed, consisting of the parasitic capacitance Cm, filter elements, and grid impedance. The changing common-mode voltage Vcm on the parasitic capacitance Cm can excite this resonant circuit to generate a corresponding common-mode current Icm.

[0042] Reference Figure 1 As shown, the photovoltaic inverter includes a HERIC inverter circuit, which includes switching transistors S1, S2, S3, S4, S5, and S6. Switches S1 and S2 are connected to form the first inverter arm, and switches S3 and S4 are connected to form the second inverter arm. The first and second inverter arms are connected in parallel between the positive DC bus 201 and the negative DC bus 202. The midpoints of the first and second inverter arms serve as AC output terminals, connected to the grid Vg. The emitter of switch S1 is electrically connected to the collector of switch S2, and the emitter of switch S3 is electrically connected to the collector of switch S4. Switches S5 and S6 form a freewheeling arm between the two inverter bridge arms. Specifically, the emitter of switch S5 is electrically connected to the midpoint between switches S1 and S2, the collector of switch S5 is electrically connected to the collector of switch S6, and the emitter of switch S6 is electrically connected to the midpoint between switches S3 and S4. The bases of switches S1, S2, S3, S4, S5, and S6 are electrically connected to MCU chip 203, and each is connected in reverse parallel with a diode.

[0043] A first detection branch 21 is connected between the midpoint of switching transistors S1 and S2 and the negative DC bus 202. A second detection branch 22 is connected between the midpoint of switching transistors S3 and S4 and the negative DC bus 202. The first detection branch 21 and the second detection branch 22 each include multiple voltage divider resistors connected in series. Specifically, the first detection branch 21 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series. One end of the first resistor R1 is electrically connected to the midpoint of switching transistors S1 and S2. One end of the third resistor R3 is connected to the negative DC bus 202 and grounded. The midpoint between the second resistor R2 and the third resistor R3 is connected to the first resistor voltage divider sampling terminal 211. The second detection branch includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 connected in series. One end of the fourth resistor R4 is electrically connected to the midpoint between the switching transistors S3 and S4. One end of the sixth resistor R6 is connected to the negative DC bus 202 and grounded. The second resistor voltage divider sampling terminal 221 is located at the midpoint between the fifth resistor R5 and the sixth resistor R6.

[0044] The principle of reducing common-mode current in this embodiment is explained as follows. In the formulas below, Cbus represents the bus capacitance, Vc is the voltage value of the resistor divider network, Vd is the voltage value of the resistor divider network; Va is the voltage between point a of the inverter bridge and point 0 of the DC negative bus; Vb is the voltage between point b of the inverter bridge and point 0 of the DC negative bus; VL1 is the inductor voltage drop across L1; VL2 is the inductor voltage drop across L2; ​​Vg is the grid voltage; Icm is the resonant current in the common-mode resonant circuit; L1 is the inverter inductance on line L; L2 is the inverter inductance on line N; PE represents the ground; Cm is the parasitic capacitance of the photovoltaic array to the ground; Vcm is the common-mode voltage generated across the parasitic capacitance; Vbus is the BUS voltage.

[0045] According to Kirchhoff's voltage law, the voltage equation for the common-mode circuit can be written as follows:

[0046] -Va+VL1+Vg+Vcm=0 (1)

[0047] -Vb-VL2+Vcm=0 (2)

[0048] Adding equations (1) and (2) yields the common-mode voltage Vcm. Since VL1 = VL2,

[0049] Get Vcm=0.5*(Va+Vb-Vg)=0.5*(Va+Vb)-0.5*Vg(3)

[0050] The common-mode current Icm flowing through the parasitic capacitance is:

[0051] Icm=Cm*dCm / dt (4)

[0052] As shown in equation (4), the common-mode current is proportional to the rate of change of the common-mode voltage. Since Vg is the mains frequency voltage, the common-mode current generated by Vg on the parasitic capacitance can generally be ignored. Va and Vb are PWM high-frequency pulse voltages, and the common-mode current is mainly generated by these excitations. Therefore, the common-mode voltage of the grid-connected inverter in engineering can be approximately expressed as:

[0053] Vcm=0.5*(Va+Vb) (5)

[0054] From the above analysis, it can be seen that if Vcm can be made to a constant value, the common-mode current can be basically eliminated. That is, the PWM switching sequence used by the inverter bridge should ensure that the sum of the voltages at points Va and Vb relative to zero satisfies the following:

[0055] Va + Vb = constant (6)

[0056] 1) When the HERIC topology is intact:

[0057] During the positive half-cycle of the grid current, when S1, S4, and S5 are turned on, the common-mode voltage is:

[0058] Vcm=0.5*(Va+Vb)=0.5*(Vpv+0)=0.5*Vpv (7)

[0059] When S5 is on and S1 and S4 are off, the common-mode voltage is:

[0060] Vcm=0.5*(Va+Vb)=0.5*(0.5*Vpv+0.5*Vpv)=0.5*Vpv (8)

[0061] From equations (7) and (8), we can see that the common-mode voltage Vcm = 0.5 * Vpv. When the PV voltage is constant, the common-mode voltage is a constant value, so the common-mode current will not be generated by the PWM high-frequency pulse voltage.

[0062] 2) When the S1 transistor (CE terminal) of the HERIC topology is short-circuited (the HERIC topology cannot work properly when the S1 transistor is open);

[0063] During the positive half-cycle of the grid current, when transistor S1 is short-circuited and transistors S4 and S5 are conducting, the common-mode voltage is:

[0064] Vcm=0.5*(Va+Vb)=0.5*(Vpv+0)=0.5*Vpv (9)

[0065] When S1 is short-circuited, S5 is on, and S4 is off, the common-mode voltage is:

[0066] Vcm=0.5*(Va+Vb)=0.5*(Vpv+0.5*Vpv)=0.75*Vpv (10)

[0067] As can be seen from equations (9) and (10), if their common-mode voltages are not equal, then the common-mode current will be generated by the PWM high-frequency pulse voltage.

[0068] It can be seen that if the collector and emitter of transistor S1 cannot conduct, that is, if there is a conduction failure, the HERIC topology cannot work properly; if the collector and emitter of transistor S1 are short-circuited, the HERIC topology can still work properly, but a large common-mode current will be generated.

[0069] 3) Similarly, when the S3 transistor (CE terminal) of the HERIC topology is short-circuited (the HERIC topology cannot work properly when the S3 transistor is open);

[0070] During the negative half-cycle of the grid current, when transistor S3 is short-circuited and transistors S2 and S6 are conducting, the common-mode voltage is:

[0071] Vcm=0.5*(Va+Vb)=0.5*(0+Vpv)=0.5*Vpv (12)

[0072] When S3 is short-circuited, S6 is on, and S2 is off, the common-mode voltage is:

[0073] Vcm=0.5*(Va+Vb)=0.5*(0.5*Vpv+Vpv)=0.75*Vpv (13)

[0074] As can be seen from equations (12) and (13), their common-mode voltages are not equal, so a common-mode current will be generated by the PWM high-frequency pulse voltage.

[0075] It can be seen that when the collector and emitter of the S3 transistor cannot conduct, i.e., there is a conduction failure, the HERIC topology cannot work properly; when the collector and emitter of the S3 transistor are short-circuited, the HERIC topology can work properly, but a large common-mode current will be generated.

[0076] Therefore, the common-mode current control method in this embodiment includes detecting the switching transistors S1 and S3 before grid connection, and allowing the photovoltaic inverter to connect to the grid after detecting that the switching transistors S1 and S3 are normal.

[0077] The steps for detecting the switching transistor S1 provided in this embodiment include:

[0078] Under the bus voltage, the switch S1 is not driven. The first resistor voltage divider sampling terminal 211 samples the voltage between the voltage divider resistors of the first detection branch 21 to obtain the first sampling voltage. The first sampling voltage is compared with the first threshold. If the first sampling voltage is less than the first threshold, it is determined that the switch S1 has no short circuit fault.

[0079] Under the bus voltage, the switch S1 is driven, and the first resistor voltage divider sampling terminal 211 samples the voltage between the voltage divider resistors of the first detection branch 21 to obtain the second sampling voltage. The second sampling voltage is compared with the second threshold. If the second sampling voltage is greater than the second threshold, it is determined that the switch S1 is normally turned on.

[0080] The steps for detecting the switching transistor S3 provided in this embodiment include:

[0081] Under the bus voltage, the switch S3 is not driven. The second resistor voltage divider sampling terminal 221 samples the voltage between the voltage divider resistors of the second detection branch 22 to obtain the third sampling voltage. The third sampling voltage is compared with the third threshold. If the third sampling voltage is less than the third threshold, it is determined that the switch S3 has no short circuit fault.

[0082] Under the bus voltage, the switch S3 is driven, and the second resistor voltage divider sampling terminal 221 samples the voltage between the voltage divider resistors of the second detection branch 22 to obtain the fourth sampling voltage. The fourth sampling voltage is compared with the fourth threshold. If the fourth sampling voltage is greater than the fourth threshold, it is determined that the switch S3 is normally turned on.

[0083] Specific examples are as follows:

[0084] (a) Check if the S1 transistor in the HERIC topology is short-circuited or not conducting.

[0085] 1. Under a certain bus voltage, the sampling voltage Vc can be obtained through the voltage divider network of resistors R1, R2, and R3; the sampling voltage Vc is then sent to the MCU.

[0086] Vc=Vbus*R3 / (R1+R2+R3) (11)

[0087] 2. Under a certain bus voltage, the ratio of resistors R1, R2, and R3 is pre-designed. Before the open-loop voltage of the inverter bridge is turned on, the S1 transistor is checked. If the S1 transistor is not driven and the drive balance is low (S2, S3, S4, S5, and S6 drive balance is low), the MCU reads the Vc voltage value. If Vc < 0.5V, the S1 transistor is determined to be normal and there is no short circuit.

[0088] 3. Under a certain bus voltage, the ratio of resistors R1, R2, and R3 is pre-designed. Before the open-loop voltage of the inverter bridge is turned on, the S1 transistor is detected. When the S1 transistor is driven, the drive balance is high; (the drive balance of S2, S3, S4, S5, and S6 is low). The MCU reads the Vc voltage value. If Vc > 1V, it is determined that the S1 transistor is conducting normally.

[0089] (ii) Check whether the S3 transistor in the HERIC topology is short-circuited or unable to conduct.

[0090] ① Under a certain bus voltage, the sampling voltage Vd can be obtained through the voltage divider network of resistors R4, R5, and R6; the sampling voltage Vd is then sent to the MCU.

[0091] Vd=Vbus*R6 / (R4+R5+R6) (14)

[0092] ② Under a certain bus voltage, the ratio of resistors R4, R5, and R6 is pre-designed. Before the open-loop voltage of the inverter bridge is tested, transistor S3 is checked. Transistor S3 is not driven, and the drive balance is low. (S1, S2, S4, S5, and S6 have low drive balance). The MCU reads the Vd voltage value. If Vd < 0.5V, transistor S3 is determined to be normal and there is no short circuit.

[0093] ③ Under a certain bus voltage, the ratio of resistors R4, R5, and R6 is pre-designed. Before the inverter bridge opens the loop voltage, the S3 transistor is tested. When the S3 transistor is driven, the drive balance is high; (S1, S2, S4, S5, and S6 drive balance is low). The MCU reads the Vd voltage value. If Vd > 1V, it is determined that the S3 transistor is conducting normally.

[0094] (iii) Allow photovoltaic inverters to be connected to the grid.

[0095] If the judgment results of any of steps 2, 3, ② and ③ are opposite, then the photovoltaic inverter is not allowed to be connected to the grid, or the photovoltaic inverter cannot work normally.

[0096] By following the steps above, it is possible to detect whether the S1 and S3 transistors of the HERIC topology are short-circuited or unable to conduct. This effectively avoids common-mode current problems caused by parasitic capacitance between the photovoltaic modules and the ground in non-isolated photovoltaic inverters due to short circuits in the S1 and S3 transistors. By proactively detecting key components of the inverter bridge and testing their basic functions before power generation, fault codes are uploaded and alarms are issued in advance when abnormalities are detected, preventing serious malfunctions such as machine failure or short circuits.

[0097] Simulation Example

[0098] I. The values ​​of the voltage divider resistors R1, R2, and R3 are selected according to... Figure 2 As shown, R1 and R2 are composed of resistors Ra, Rb, Rc, Rd and Re (5 PCS 220kΩ) connected in series, and R3 is composed of resistor Rf (1 PCS 4.99kΩ), forming a resistor voltage divider network; the voltage value Va is sent to the MCU for sampling.

[0099] The preset PV voltage is 350Vdc. Before the inverter bridge open-loop voltage is tested, transistor S1 is checked. S1 is not driven, and the drive balance is low (S1 / S2 / S3 / S4 / S5 / S6 drive balance is low). S1 is not conducting. At this time, the MCU reads the voltage value of the resistor divider network, Vc = 34.00mV < 0.5V (indicating that S5 is normal and there is no short circuit); the test waveform is as follows. Figure 3 As shown.

[0100] The preset PV voltage is 350Vdc. Before the inverter bridge open-loop voltage is tested, transistor S1 is checked. When transistor S1 is driven, the drive balance is high (while the drive balance of S2 / S3 / S4 / S5 / S6 is low), and transistor S1 is turned on. At this time, the MCU reads the voltage value of the resistor divider network, Vc = 1.60V > 1V (indicating that transistor S1 is conducting normally); the test waveform is as follows. Figure 4 As shown.

[0101] II. The values ​​of the voltage divider resistors R4, R5, and R6 are selected according to... Figure 5 As shown, R4 and R5 are composed of resistors Ra, Rb, Rc, Rd and Re (5 PCS 220kΩ) connected in series, and R6 is composed of resistor Rf (1 PCS 4.99kΩ), forming a resistor voltage divider network; the voltage value Vb is sent to the MCU for sampling.

[0102] The preset PV voltage is 350Vdc. Before the inverter bridge open-loop voltage is tested, the S3 transistor is checked. The S3 transistor is not driven, and the drive balance is low (S1 / S2 / S3 / S4 / S5 / S6 drive balance is low). The S3 transistor is not conducting. At this time, the MCU reads the voltage value of the resistor divider network, Vd = 34.83mV < 0.5V (indicating that the S3 transistor is normal and there is no short circuit); the test waveform is as follows. Figure 6 As shown.

[0103] The preset PV voltage is 350Vdc. Before the inverter bridge open-loop voltage is tested, transistor S3 is checked. When transistor S3 is driven, the drive balance is high (while the drive balance of S1 / S2 / S4 / S5 / S6 is low), and transistor S3 is turned on. At this time, the MCU reads the voltage value of the resistor divider network, Vd = 1.61V > 1V (indicating that transistor S3 is conducting normally); the test waveform is as follows. Figure 7 As shown.

[0104] Figures 3 to 4 In the diagram, CH1 represents the PV voltage, and CH2 represents the Vd voltage sampled by the resistor divider network. Figures 6 to 7 In the diagram, CH1 represents the PV voltage, and CH2 represents the Vd voltage sampled by the resistor divider network.

[0105] Through the above theoretical analysis and test verification, it is possible to effectively detect whether the S1 and S3 transistors in the HERIC topology are short-circuited or unable to conduct. This can avoid common-mode current problems caused by the parasitic capacitance of photovoltaic modules to the ground in non-isolated photovoltaic inverters due to short circuits in the S1 and S3 transistors. It can also proactively detect whether the key components and their functions in the inverter bridge are abnormal, thus achieving the function of early detection, prevention, and alarm.

[0106] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are preferred embodiments. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and they should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A common-mode current control method for a HERIC-type non-isolated photovoltaic inverter, the photovoltaic inverter comprising a HERIC inverter circuit, the HERIC inverter circuit comprising switching transistors S1, S2, S3, S4, S5, and S6, wherein switching transistors S1 and S2 are connected to form a first inverter bridge arm, and switching transistors S3 and S4 are connected to form a second inverter bridge arm; characterized in that, The photovoltaic inverter further includes a first detection branch and a second detection branch. The first detection branch is connected between the midpoint of the switching transistors S1 and S2 and the negative DC bus. The second detection branch is connected between the midpoint of the switching transistors S3 and S4 and the negative DC bus. The first detection branch and the second detection branch each include multiple voltage divider resistors connected in series. The common-mode current control method includes: detecting the switching transistors S1 and S3, and allowing the photovoltaic inverter to connect to the grid after detecting that there is no short-circuit fault in the switching transistors S1 and S3; The specific steps for detecting the switching transistor S1 include: (A1) Under the bus voltage, the switch S1 is not driven and the voltage between the voltage divider resistors of the first detection branch is sampled to obtain the first sample voltage. The first sample voltage is compared with the first threshold. If the first sample voltage is less than the first threshold, it is determined that the switch S1 has no short circuit fault. The specific steps for detecting the switching transistor S3 include: (B1) Under the bus voltage, the switch S3 is not driven and the voltage between the voltage divider resistors of the second detection branch is sampled to obtain a third sample voltage. The third sample voltage is compared with a third threshold. If the third sample voltage is less than the third threshold, it is determined that the switch S3 has no short circuit fault.

2. The common-mode current control method according to claim 1, characterized in that, The step of detecting the switching transistor S1 further includes: (A2) Under the bus voltage, the switch S1 is driven to sample the voltage between the voltage divider resistors of the first detection branch to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that the switch S1 is normally turned on. The step of detecting the switching transistor S3 further includes: (B2) Under the bus voltage, the switch S3 is driven to sample the voltage between the voltage divider resistors of the second detection branch to obtain a fourth sampling voltage. The fourth sampling voltage is compared with a fourth threshold. If the fourth sampling voltage is greater than the fourth threshold, it is determined that the switch S3 is normally turned on. The photovoltaic inverter is allowed to connect to the grid after it is detected that there is no short circuit fault in the switching transistors S1 and S3 and they are conducting normally.

3. The common-mode current control method according to claim 2, characterized in that, The second threshold is greater than the first threshold, and the fourth threshold is greater than the third threshold.

4. The common-mode current control method according to claim 1, characterized in that, The first detection branch includes a first resistor, a second resistor, and a third resistor connected in series. One end of the first resistor is electrically connected to the midpoint between the switching transistors S1 and S2. The first sampling voltage is obtained through the voltage divider sampling terminal of the first resistor connected to the midpoint between the second resistor and the third resistor.

5. The common-mode current control method according to claim 1, characterized in that, The second detection branch includes a fourth resistor, a fifth resistor, and a sixth resistor connected in series. One end of the fourth resistor is electrically connected to the midpoint between the switching transistors S3 and S4. The third sampling voltage is obtained through the second resistor voltage divider sampling terminal connected to the midpoint between the fifth resistor and the sixth resistor.

6. The common-mode current control method according to claim 4, characterized in that, The resistance of the first resistor is greater than the resistance of the second resistor.

7. The common-mode current control method according to claim 1, characterized in that, The emitter of the switching transistor S1 is electrically connected to the collector of the switching transistor S2, and the emitter of the switching transistor S3 is electrically connected to the collector of the switching transistor S4.

8. The common-mode current control method according to claim 7, characterized in that, The emitter of the switching transistor S5 is electrically connected to the midpoint of the first inverter bridge arm, the collector of the switching transistor S5 is electrically connected to the collector of the switching transistor S6, the emitter of the switching transistor S6 is electrically connected to the midpoint of the second inverter bridge arm, and diodes are connected in reverse parallel between the switching transistors S5 and S6.

9. A common-mode current control method for a HERIC-type non-isolated photovoltaic inverter, the photovoltaic inverter comprising a HERIC inverter circuit, the HERIC inverter circuit comprising switching transistors S1, S2, S3, S4, S5, and S6, wherein switching transistors S1 and S2 are connected to form a first inverter bridge arm, and switching transistors S3 and S4 are connected to form a second inverter bridge arm; characterized in that, The photovoltaic inverter further includes a first detection branch, which is connected between the midpoint of the switching transistors S1 and S2 and the negative DC bus. The first detection branch includes multiple voltage divider resistors connected in series. The common-mode current control method includes: detecting the switching transistor S1, and connecting the photovoltaic inverter to the grid after detecting that the switching transistor S1 is normal. The specific steps for detecting the switching transistor S1 include: (A1) Under the bus voltage, the switch S1 is not driven and the voltage between the voltage divider resistors of the first detection branch is sampled to obtain the first sample voltage. The first sample voltage is compared with the first threshold. If the first sample voltage is less than the first threshold, it is determined that the switch S1 has no short circuit fault. (A2) Under the bus voltage, the switch S1 is driven to sample the voltage between the voltage divider resistors of the first detection branch to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that the switch S1 is normally turned on.

10. A common-mode current control method for a HERIC-type non-isolated photovoltaic inverter, the photovoltaic inverter comprising a HERIC inverter circuit, the HERIC inverter circuit comprising switching transistors S1, S2, S3, S4, S5, and S6, wherein switching transistors S1 and S2 are connected to form a first inverter bridge arm, and switching transistors S3 and S4 are connected to form a second inverter bridge arm; characterized in that, The photovoltaic inverter also includes a second detection branch, which is connected between the midpoint of the switching transistors S3 and S4 and the negative DC bus. The second detection branch includes multiple voltage divider resistors connected in series. The common-mode current control method includes: detecting the switching transistor S3, and connecting the photovoltaic inverter to the grid after detecting that the switching transistor S3 is normal; The specific steps for detecting the switching transistor S3 include: (B1) Under the bus voltage, the switch S3 is not driven and the voltage between the voltage divider resistors of the second detection branch is sampled to obtain a third sample voltage. The third sample voltage is compared with a third threshold. If the third sample voltage is less than the third threshold, it is determined that the switch S3 has no short circuit fault. (B2) Under the bus voltage, the switch S3 is driven to sample the voltage between the voltage divider resistors of the second detection branch to obtain a fourth sampling voltage. The fourth sampling voltage is compared with a fourth threshold. If the fourth sampling voltage is greater than the fourth threshold, it is determined that the switch S3 is normally turned on.

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