Supply voltage detection circuit and circuit system using the same

Abstract

The present invention provides a supply voltage detection circuit and a circuit system using the same, wherein the supply voltage detection circuit has a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives a supply voltage and is used to detect the supply voltage to generate a low voltage detection signal. When the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and the transistor current flowing through the voltage detection circuit is proportional to the supply voltage; when the supply voltage is greater than or equal to the set level, the low voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a fixed current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the fixed current. The supply voltage detection circuit provided by the present invention has the characteristics of high accuracy, low temperature drift and low power consumption.

Description

Technical Field

[0001] The present invention relates to a supply voltage detection circuit, and more particularly to a supply voltage detector with a stable temperature coefficient, low power consumption and fast response, and a circuit system using the same. Background Art

[0002] The supply voltage detection circuit is also known as a brownout detector (BOD) or low voltage detector (LVD). After the circuit system is powered on, the microcontroller activates the supply voltage detection mechanism to determine the low-voltage operating mode and even serve as a basis for switching between different power sources. Therefore, the accuracy and temperature characteristics of the voltage detection are very important, and the power consumption and response speed of the voltage detection are also discussed in the specifications. Since the supply voltage detection circuit needs to detect the supply voltage (e.g., VDD), one common approach is to use a voltage divider resistor string to divide the supply voltage to generate a sense voltage. This sense voltage is then compared with a reference voltage generated by a bandgap voltage generator to determine whether the circuit system should operate in the low-voltage operating mode or start up in the normal operating mode. Generally speaking, the response speed and power consumption of the supply voltage detection circuit are usually in a trade-off relationship with the circuit area.

[0003] Please refer to Figure 1 , Figure 1 This is a circuit diagram of a conventional supply voltage detection circuit. In the supply voltage detection circuit 1, MOS transistor MN1, PMOS transistor MP1, and resistor R3 form a latch circuit, and resistors R1 and R2 serve as a voltage divider resistor string. The low-voltage detection signal BODOUT output by the supply voltage detection circuit 1 is related to the threshold voltage (VTH) of the MOS transistor MN1 and the PMOS transistor MP1. In integrated circuit manufacturing processes, threshold voltage variations can be as high as ±20%, and even reach 40% when the threshold voltage is in the slow-fast (SF) or fast-slow (FS) corner. This can cause the supply voltage detection circuit 1 to output an erroneous low-voltage detection signal BODOUT. For example, the expected startup voltage is 1.7 volts (i.e., when the supply voltage VDD is greater than or equal to 1.7 volts, the output low-voltage detection signal BODOUT is a logic low, allowing the circuit system to start and operate in normal mode). However, the actual startup voltage ranges from 1.36 to 2.04 volts.

[0004] Please refer to Figure 2 , Figure 2This is a circuit diagram of another conventional supply voltage detection circuit. Supply voltage detection circuit 2 includes a bandgap voltage generator 21 (formed by a comparator CMP2, PMOS transistors MP1-MP3, resistors R3-R6, and BJT transistors Q1-Q3), a voltage divider resistor string (formed by resistors R1 and R2 connected in series), and comparator CMP1. Initially, supply voltage detection circuit 2 operates bandgap voltage generator 21. It then compares the sense voltage VSEN generated by the resistor divider resistor string with the reference voltage VBG generated by bandgap voltage generator 21 via comparator CMP1 to detect the supply voltage. This approach of supply voltage detection circuit 2 achieves a more accurate startup voltage, but this sacrifices power consumption.

[0005] Please refer to Figure 3A , Figure 3A This is a circuit diagram of another conventional supply voltage detection circuit. The supply voltage detection circuit 3 includes multiple BJT transistors Q1 and Q2, resistors R1-R4, a comparator CMP1, a PMOS transistor MP1, an AND logic gate AND1, and an inverter module 301 (composed of multiple inverters connected in series). The BJT transistor Q2 and resistor R4 form a circuit similar to a bandgap voltage generator. The PMOS transistor MP1 is controlled by the enable signal EN output by the AND logic gate AND1 to turn on or off, enabling the bandgap voltage generator-like circuit to generate a reference voltage VBE2 and the BJT transistor Q1 and resistors R1-R3 to generate a sense voltage VBER, where the sense voltage VBE2 is equal to the base-emitter voltage of the BJT transistor Q2. The comparator CMP1 is enabled by the enable signal EN and is used to compare the sense voltage VBER with the reference voltage VBE2 to output a low-voltage detection signal. The inverter module 301 is used to generate a reverse low-voltage detection signal BODOUT_B. The AND logic gate AND1 receives the reverse low voltage detection signal BODOUT_B and the external signal STB, and thereby resets or activates the supply voltage detection circuit 3 through the generated enable signal EN.

[0006] Please also refer to Figure 3A and Figure 3B , Figure 3B yes Figure 3A The waveform of the supply voltage detection circuit. When the supply voltage VDD rises, the sensing voltage VBER will also rise. LWhen the external signal STB is at a logic high level ("1"), the sense voltage VBER is greater than the reference voltage VBE2, causing the reverse low-voltage detection signal BODOUT_B to be at a logic high level. The supply voltage detection circuit 3 can achieve higher accuracy when the supply voltage VDD is at a low input voltage, but the detection level is difficult to adjust and requires the external signal STB to activate and reset. After the circuit system is activated (the reverse low-voltage detection signal BODOUT_B is at a logic high level), the supply voltage detection circuit 3 enters a state of death lock and cannot be used any further, requiring an external signal STB to reset it. Summary of the Invention

[0007] An embodiment of the present invention provides a supply voltage detection circuit, and the supply voltage detection circuit includes: a voltage detection circuit that receives a supply voltage and is used to detect the supply voltage to generate a low-voltage detection signal; and a current clamping circuit electrically connected to the voltage detection circuit; wherein when the supply voltage is lower than a set level, the low-voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and a transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is greater than or equal to the set level, the low-voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a fixed current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the fixed current.

[0008] In one embodiment, the voltage detection circuit includes a switching PMOS transistor, first to third resistors, a comparator, and first and second diode circuits. The source of the switching PMOS transistor receives the supply voltage, the gate of the switching PMOS transistor is electrically connected to the output of the comparator, the drain of the switching PMOS transistor is electrically connected to the first ends of the second and third resistors, the second ends of the second and third resistors are electrically connected to the negative and positive inputs of the comparator, respectively. The output of the comparator outputs the low voltage detection signal and is electrically connected to the current clamp circuit to control the turning on and off of the current clamp circuit. The first diode circuit is electrically connected to the second end of the second resistor, the first end of the first resistor is electrically connected to the second end of the third resistor, and the second end of the first resistor is electrically connected to the second diode circuit. The drain of the switching PMOS transistor is also electrically connected to one end of the current clamp circuit to receive a current proportional to the fixed current when the current clamp circuit is turned on.

[0009] In one embodiment, the current clamping circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a current source. The sources of the first PMOS transistor and the second PMOS transistor receive the supply voltage. The gate of the first PMOS transistor is electrically connected to the gate and drain of the second PMOS transistor. The drain of the first PMOS transistor is electrically connected to the voltage detection circuit to provide a current proportional to the fixed current when the current clamping circuit is turned on. The gate of the first NMOS transistor is electrically connected to the voltage detection circuit to receive the low voltage detection signal. The drain of the first NMOS transistor is electrically connected to the drains of the first PMOS transistor and the second PMOS transistor. The source of the first NMOS transistor is electrically connected to the current source to receive the fixed current provided by the current source.

[0010] In one embodiment, each of the first diode circuit and the second diode circuit is composed of one or more BJT transistors.

[0011] In one embodiment, the voltage detection circuit further includes a fourth resistor and a trimming resistor, wherein a first end of the trimming resistor is electrically connected to the drain of the switch PMOS transistor, a second end of the trimming resistor is electrically connected to a first end of the fourth resistor, and a second end of the fourth resistor is electrically connected to the first ends of the second resistor and the third resistor.

[0012] In one embodiment, the fourth resistor and the trimming resistor are variable resistors, and their resistance values ​​are changed according to two control signals respectively.

[0013] An embodiment of the present invention further provides a supply voltage detection circuit, comprising: a voltage detection circuit; an adjustable voltage generating circuit, electrically connected to the voltage detection circuit, receiving a supply voltage, and generating a bias voltage for biasing the voltage detection circuit; wherein the voltage detection circuit receives the bias voltage, and when the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit is a logic low level; and when the supply voltage is greater than or equal to the set level, the low voltage detection signal output by the voltage detection circuit is a logic high level.

[0014] In one embodiment, the voltage detection circuit includes a first resistor to a fourth resistor, a first comparator, and a first diode circuit and a second diode circuit. The first end of the fourth resistor is electrically connected to the adjustable voltage generating circuit to receive the bias voltage. The second end of the fourth resistor is electrically connected to the first end of the second resistor and the third resistor. The second ends of the second resistor and the third resistor are electrically connected to the negative input terminal and the positive input terminal of the first comparator, respectively. The output terminal of the first comparator outputs the low voltage detection signal. The first diode circuit is electrically connected to the second end of the second resistor. The first end of the first resistor is electrically connected to the second end of the third resistor, and the second end of the first resistor is electrically connected to the second diode circuit. The fourth resistor is a variable resistor and receives a first control signal to change its resistance value.

[0015] In one embodiment, the adjustable voltage generating circuit includes a trimming resistor, a fifth resistor, and a voltage follower. A first end of the trimming resistor receives the supply voltage, a second end of the trimming resistor is electrically connected to the first end of the fifth resistor and the positive input end of the voltage follower, and an output end of the voltage follower is electrically connected to the negative input end of the voltage follower and is used to output the bias voltage. The trimming resistor is a variable resistor and receives a second control signal to change its resistance value.

[0016] An embodiment of the present invention further provides a circuit system, comprising: a load; and any one of the aforementioned supply voltage detection circuits, electrically connected to the load.

[0017] In summary, compared to the prior art, the embodiments of the present invention provide a supply voltage detection circuit with high accuracy, low temperature drift, and low power consumption, and a circuit system using the same.

[0018] To further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, which may provide a thorough and specific understanding of the purposes, features and concepts of the present invention. However, the following detailed description and accompanying drawings are intended only to provide a reference and illustration of the implementation of the present invention and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention may be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 This is a circuit diagram of a conventional supply voltage detection circuit;

[0021] Figure 2 This is another circuit diagram of a conventional supply voltage detection circuit;

[0022] Figure 3A This is another circuit diagram of a traditional supply voltage detection circuit;

[0023] Figure 3B yes Figure 3A The waveform diagram of the supply voltage detection circuit;

[0024] Figure 4 is a block diagram of a supply voltage detection circuit according to a first embodiment of the present invention;

[0025] Figure 5A is a circuit diagram of a supply voltage detection circuit according to a second embodiment of the present invention;

[0026] Figure 5B yes Figure 5A a graph of a reference voltage and a sense voltage of a supply voltage detection circuit relative to the supply voltage;

[0027] Figure 5C yes Figure 5A a graph of transistor current versus supply voltage when the supply voltage detection circuit operates in a first mode and a second mode;

[0028] Figure 6 is a circuit diagram of a supply voltage detection circuit according to a third embodiment of the present invention;

[0029] Figure 7 is a circuit diagram of a supply voltage detection circuit according to a fourth embodiment of the present invention; and

[0030] Figure 8 FIG. 5 is a circuit diagram of a supply voltage detection circuit according to a fifth embodiment of the present invention.

[0031] The symbols in the diagram are explained as follows: 1 to 8 supply voltage detection circuit; R1 to R6, R TRIM Resistors; VDD, AVDD supply voltages; BODOUT low-voltage detection signal; BODOUT_B reverse low-voltage detection signal; MP1 to MP3, MSW PMOS transistors; MN1 NMOS transistor; CMP1, CMP2 comparators; VBG, VBE2, VBE1 reference voltages; VSEN, VBER sense voltages; Q1 to Q3, Q 24 BJT transistor; 21 bandgap voltage generator; 301 inverter module; AND1 AND logic gate; STB external signal; BOD LSet level; 42, 51, 61, 71, 82 voltage detection circuit; 41, 52, 62, 72 current clamp circuit; BODSEL[2:0], VBGTRIM[3:0] control signals; VBOD, VBP, VBGR, VX, VBE24, VBE voltage; VSS low voltage; CS current source; IHOLD fixed current; 511, 512, 611, 612, 711, 712 diode circuit; IBJT transistor current; mode1 first mode; mode2 second mode; 81 adjustable voltage generation circuit; and VF voltage follower. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or similar parts. The exemplary embodiments are merely one way to implement the design concepts of the present invention, and the following examples are not intended to limit the present invention.

[0033] The present invention provides a high-precision, low temperature drift and low power supply voltage detection circuit and a circuit system using the same. The circuit uses the base-emitter voltage difference (ΔVBE) to generate a bias voltage to detect whether the supply voltage is greater than a set level BOD. L , and the supply voltage is greater than the set level BOD L When the supply voltage detection circuit is turned on, the overall current of the supply voltage detection circuit will be clamped, thereby reducing power consumption. Furthermore, the supply voltage detection circuit can continue to be used after being activated without the need for an external signal to reset or activate it.

[0034] First, please refer to 4. Figure 4 is a block diagram of a supply voltage detection circuit according to an embodiment of the present invention. The supply voltage detection circuit 4 includes a current clamp circuit 41 and a voltage detection circuit 42, wherein the current clamp circuit 41 and the voltage detection circuit 42 are electrically connected to each other and receive the supply voltage VDD, and the voltage detection circuit 42 outputs a low voltage detection signal BODOUT to the current clamp circuit 41 and a load electrically connected to the supply voltage detection circuit 4 (not shown). Figure 4 , for example, a circuit or chip with a specific function).

[0035] The voltage detection circuit 42 is used to detect the supply voltage VDD and output a low voltage detection signal BODOUT to control whether the current clamp circuit 41 is activated (turned off or on). LWhen the voltage detection circuit 42 outputs the low voltage detection signal BODOUT, the current clamp circuit 41 is turned off, and the currents flowing through the voltage detection circuit 42 (for example, in the following Figure 5A 、 Figure 6 、 Figure 7 In the embodiment, there are two currents) that increase with the supply voltage VDD. However, when the supply voltage VDD is greater than or equal to the set level BOD L When the voltage detection circuit 42 outputs the low voltage detection signal BODOUT, the current clamp circuit 41 is turned on, and the current clamp circuit 41 provides a fixed current (for example, in the following Figure 5A 、 Figure 6 、 Figure 7 The constant current IHOLD in the embodiment is used to maintain the continuous operation of the voltage detection circuit 42. In this way, the overall power consumption of the supply voltage detection circuit 4 is limited by the constant current provided by the current clamp circuit 41. On the other hand, the voltage detection circuit 42 uses at least two BJT transistors to generate a base-emitter voltage difference (delta VBE) to generate a voltage (e.g., Figure 5A 、 Figure 6 and Figure 7 voltage VBOD) to detect whether the supply voltage is greater than the set level BOD L Therefore, the supply voltage detection circuit 4 is less susceptible to temperature drift, and thus can achieve high-precision detection.

[0036] Please refer to Figure 5A , Figure 5A FIG is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. Figure 5A In the embodiment, the current clamp circuit 52 of the supply voltage detection circuit 5 is composed of two PMOS transistors MP1 and MP2, an NMOS transistor MN1 and a current source CS, and the voltage detection circuit 51 of the supply voltage detection circuit 5 is composed of a PMOS transistor MSW, a plurality of resistors R TRIM , R1~R4, comparator CMP1 and diode circuits 511, 512 (respectively composed of two BJT transistors Q1, Q 24 implementation).

[0037] The source of the PMOS transistor MSW receives the supply voltage VDD, the gate of the PMOS transistor MSW is electrically connected to the output terminal of the comparator CMP1 to receive the low-voltage detection signal BODOUT outputted from the output terminal of the comparator CMP1, and the drain of the PMOS transistor MSW is electrically connected to the drain of the PMOS transistor MP2 in the current clamp circuit 52. In the second mode, the bias voltage level of VBOD is maintained by the fixed current IHOLD provided by the current clamp circuit 52 and a bias current corresponding to the fixed current IHOLD (which is proportional to the fixed current IHOLD and has a fixed current value) is received. TRIM The two ends of the resistor R3 are electrically connected to the drain of the PMOS transistor MSW and one end of the resistor R4, respectively, and the other end of the resistor R4 is electrically connected to one end of the resistor R2 and one end of the resistor R3. The other end of the resistor R2 is electrically connected to the emitter of the BJT transistor Q1 and the negative input terminal of the comparator CMP1, and the other end of the resistor R3 is electrically connected to one end of the resistor R1 and the positive input terminal of the comparator CMP1. The other end of the resistor R1 is electrically connected to the BJT transistor Q1. 24 The emitter of BJT transistors Q1, Q 24 The base and collector of the resistor R are electrically connected to a low voltage VSS, for example, a ground voltage. TRIM , R4 is a non-essential component and can be removed in other embodiments.

[0038] The sources of the PMOS transistors MP1 and MP2 receive a supply voltage VDD. The gates of the PMOS transistors MP1 and MP2 are electrically connected to each other, and the gate of the PMOS transistor MP2 is electrically connected to the drain of the PMOS transistor MP2. The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor MP2. The gate of the NMOS transistor N1 is electrically connected to the output terminal of the comparator CMP1 to receive the low-voltage detection signal BODOUT output by the output terminal of the comparator CMP1. The source of the NMOS transistor N1 is connected to one terminal of the current source CS. The other terminal of the current source CS is electrically connected to the low voltage VSS.

[0039] When the supply voltage detection circuit 5 is connected to the supply voltage VDD, one of the currents in the supply voltage detection circuit 5 flows through the resistor R2 and the transistor Q1 (which is connected in such a way that it functions as a diode) and thereby generates a reference voltage VBE1, wherein the reference voltage VBE1 is the base-emitter voltage of the transistor Q1 and is received by the negative input terminal of the comparator CMP1. Another current in the supply voltage detection circuit 5 flows through the resistors R1, R3 and the transistor Q1. 24 , and generates a sensing voltage VBER to the positive input terminal of the comparator CMP1, wherein the sensing voltage VBER is the 24The base-emitter voltage VBE24 plus the voltage across resistor R1. TRIM The resistor R4 can be a variable resistor and receive control signals BODSEL[2:0] and VBGTRIM[3:0] to adjust its resistance value respectively, so that the level of the voltage VBGR can be adjusted. TRIM The resistor R4 can make the circuit layout easier to match and reduce the manufacturing process variation, but as mentioned above, the resistor R TRIM , R4 are non-essential components and can be removed or replaced by a low dropout regulator (LDO) buffer (i.e., the resistor R TRIM , R4 are removed, and a low voltage linear regulator buffer is used to provide voltage VBGR).

[0040] When the supply voltage VDD is lower than the set level BOD L When (operating in the first mode), because the size of the BJT transistor Q1 is designed to be small, the BJT transistor Q1 has a larger internal resistance, so that the reference voltage VBE1 is higher than the sensing voltage VBER. The low voltage detection signal BODOUT output by the comparator CMP1 is a logic low level ("0"), so the PMOS transistor MSW is turned on (conducted), so that the voltage VBOD on the drain of the PMOS transistor MSW is substantially equal to the supply voltage, thereby reducing the detection error. At this time, the two PMOS transistors MP1, MP2 and the NMOS transistor MN1 of the current clamp circuit 52 are turned off, and the voltage VBP on the drain of the PMOS transistors MP1 and MP2 is a high voltage, so that the current consumed by the current clamp circuit 52 is substantially zero (the current of the PMOS transistors MP1 and MP2 is 0), and no power is consumed. In addition, the current flowing through the BJT transistors Q1, Q 24 The two currents I_Q1 and I_Q24 are proportional to the magnitude of the supply voltage VDD.

[0041] When the supply voltage VDD gradually rises and is greater than or equal to the set level BOD LWhen (operating in the second mode), the voltage VX at one end of the resistors R2 and R3 gradually rises, so that the sensing voltage VBER is greater than or equal to the reference voltage VBE1, so the low voltage detection signal BODOUT output by the comparator CMP1 is a logic high level ("1"). At this time, the PMOS transistor MSW is turned off (non-conducting), the NMOS transistor MN1 is turned on (conducting), and the PMOS transistors MP1 and MP2 are turned on (conducting) to provide a fixed current IHOLD to the drain of the PMOS transistor MP2 to generate a voltage VBOD to provide a bias and maintain the operation of the voltage detection circuit 51. At this time, even if the supply voltage VDD continues to rise, the voltage detection circuit 51 is clamped by the current clamp circuit 52 and still maintains the same operating current, so that power consumption can be reduced. At this time, the current I_MP2 of the PMOS transistor MP2 is set to be greater than the current flowing through the BJT transistors Q1 and Q 24 As mentioned above, the current flowing through BJT transistors Q1 and Q 24 The two currents are substantially proportional to the size of the fixed current IHOLD.

[0042] In this embodiment, the convergence point is set when the current IQ1 is equal to the current IQ24, and the level BOD is set L It can be calculated from the current IQ1 and IQ24 at the convergence point. At this time, IQ1=ΔVBE / R1=VTln(n) / R1, and the voltage VBOD=2*IQ1*[(R2 / / R3)+R4+R TRIM ]+VBE1, where ΔVBE is the base-emitter voltage difference (ΔVBE). Since the current IQ1 has a temperature coefficient proportional to the absolute temperature, it will affect the voltage VBOD. Therefore, the resistors R2, R3, R4 and R TRIM , so that the supply voltage detection circuit 5 is not easily affected by temperature drift. In one embodiment, the reference voltage VBE1 can be set to 1.25, 2.5 or 3.75 volts.

[0043] Figure 5B yes Figure 5A The reference voltage and sense voltage of the supply voltage detection circuit are plotted against the supply voltage. As previously mentioned, the relationship between the reference voltage VBE1 and the sense voltage VBER of the two input voltages (referred to as voltage VBE) of the comparator CMP1 and the supply voltage VDD is shown in the figure below. Figure 5B When the supply voltage VDD is greater than or equal to the set level BOD L , the sensing voltage VBER is greater than or equal to the reference voltage VBE1, and maintains a fixed voltage value at the reference voltage VBE1 (due to being clamped by the current clamping circuit 52); when the supply voltage VDD is less than the set level BODL , the sensing voltage VBER is less than the reference voltage VBE1.

[0044] Figure 5C yes Figure 5A The supply voltage detection circuit of FIG. 1 is operated in the first mode and the second mode. As described above, the transistor current flowing through the BJT transistors Q1 and Q 24 The sum of the two currents is represented by the transistor current IBJT. The transistor current IBJT is in the first mode mode1 (the supply voltage VDD is less than the set level BOD L ), which is proportional to the size of the supply voltage VDD; and the transistor current IBJT in the second mode mode2 (supply voltage VDD is greater than or equal to the set level BOD L ), which is a fixed current proportional to the fixed current IHOLD.

[0045] Next, please refer to Figure 6 , Figure 6 FIG is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. The supply voltage detection circuit 6 includes a current clamping circuit 62 and a voltage detection circuit 61. The current clamping circuit 62 and the voltage detection circuit 61 are connected. Figure 5A The current clamp circuit 52 is the same as that of the current clamp circuit 52, and the diode circuits 611 and 612 of the voltage detection circuit 61 are the same as those of the current clamp circuit 52. Figure 5A The diode circuits 511 and 512 of the voltage detection circuit 51 are slightly different. Each of the diode circuits 611 and 612 is implemented by two BJT transistors (in a diode connection mode) to provide twice the bias voltage of the diode circuits 511 and 512. For example, Figure 5A The voltage VBE1 and VBE24 are 1.25 volts, and Figure 6 The voltage VBE1 and VBE24 are 2.5 volts.

[0046] Next, please refer to Figure 7 , Figure 7 FIG is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. The supply voltage detection circuit 7 includes a current clamping circuit 72 and a voltage detection circuit 71. The current clamping circuit 72 and the voltage detection circuit 71 are connected. Figure 5A The current clamp circuit 52 is the same as that of the current clamp circuit 52, and the diode circuits 711 and 712 of the voltage detection circuit 71 are the same as those of the current clamp circuit 52. Figure 5A The diode circuits 511 and 512 of the voltage detection circuit 51 are slightly different. Each of the diode circuits 711 and 712 is implemented by three BJT transistors (in a diode connection mode) to provide a triple bias voltage of the diode circuits 511 and 512. For example, Figure 5A The voltage VBE1 and VBE24 are 1.25 volts, and Figure 7 The voltage VBE1 and VBE24 are 3.75 volts.

[0047] Next, please refer to Figure 8 , Figure 8 FIG. 8 is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. The supply voltage detection circuit 8 does not have a current clamp circuit, but includes an adjustable voltage generating circuit 81 and a voltage detection circuit 82, wherein the voltage detection circuit 82 is substantially the same as Figure 5A The voltage detection circuit 51 is approximately Figure 5A The resistor R in the voltage detection circuit 51 TRIM The PMOS transistor MSW is replaced by an adjustable voltage generating circuit 81 to form the supply voltage detection circuit 8 .

[0048] The adjustable voltage generating circuit 81 includes a resistor R TRIM , R5 and voltage follower VF. Resistor R TRIM The two ends of the voltage follower VF are electrically connected to the supply voltage AVDD and one end of the resistor R5, respectively. The other end of the resistor R5 is electrically connected to the low voltage VSS. The voltage follower VF is implemented by a comparator, for example, but the present invention is not limited thereto. The output end of the voltage follower VF is electrically connected to the negative input end of the voltage follower VF, and the positive input end of the voltage follower VF is electrically connected to one end of the resistor R5 and the resistor R TRIM The other end (resistor R5 and R TRIM ) to receive the voltage VBOD used to bias the voltage detection circuit 82. The voltage follower VF is connected in such a way that it acts as a buffer, so that the voltage VBGR is substantially equal to the voltage VBOD. The level of the voltage VBOD can be adjusted by the control signal BODSEL[2:0] to adjust the resistor R TRIM The operation principle of the supply voltage detection circuit 8 is similar to that of the supply voltage detection circuits 4 to 7. When the supply voltage AVDD is lower than the set level BOD L When the supply voltage detection circuit 8 outputs a low voltage detection signal BODOUT, which is a logic low level ("0"); and when the supply voltage AVDD is greater than or equal to the set level BODOUT, ... L When the supply voltage detection circuit 8 outputs a low voltage detection signal BODOUT, which is a logic high level ("1"). In this embodiment, regardless of whether the supply voltage detection circuit 8 operates in the first or second mode, the current flowing through the BJT transistors Q1 and Q 24 The two currents I_Q1 and I_Q24 are both proportional to the magnitude of the supply voltage AVDD.

[0049] In addition, an embodiment of the present invention further provides a circuit system, which includes a load and any one of the above-mentioned supply voltage detection circuits 4 to 8, wherein the load can be electrically connected to the supply voltage detection circuit, and the load can be any functional chip or functional circuit that needs to use the supply voltage detection result.

[0050] In summary, compared to the prior art, the present invention provides a supply voltage detection circuit and a circuit system using the same with high accuracy, low temperature drift, and low power consumption. Furthermore, when the supply voltage is greater than a set level, the voltage detection circuit in the supply voltage detection circuit is clamped to a fixed current, thereby effectively reducing power consumption. Furthermore, because the base-emitter voltage difference (ΔVBE) is used to generate a bias voltage, it is possible to detect whether the supply voltage is greater than the set level BOD. L Therefore, the influence of temperature drift is small and the accuracy can be improved. Furthermore, the supply voltage detection circuit can continue to be used after being activated without the need for resetting or starting through an external signal.

[0051] It will be understood that the above embodiments are cited only as examples, and the present invention is not limited to what has been specifically shown and described above. Instead, the scope of the present invention includes combinations and subcombinations of the various features described above, variations and modifications thereof that would occur to a person skilled in the art after reading the foregoing description, and those not disclosed in the prior art. Documents incorporated by reference into this patent application should be considered an integral part of this application, except that the scope of any term defined in such incorporated documents in a manner that conflicts with the explicit or implicit definition in this specification should be considered in the present specification.

Claims

1. A supply voltage detection circuit, characterized in that: The supply voltage detection circuit includes: Voltage detection circuit; an adjustable voltage generating circuit, electrically connected to the voltage detecting circuit, receiving a supply voltage and generating a bias voltage for biasing the voltage detecting circuit; The voltage detection circuit receives the bias voltage, and when the supply voltage is lower than a set level, the voltage detection circuit outputs a low voltage detection signal at a logic low level; and when the supply voltage is greater than or equal to the set level, the voltage detection circuit outputs the low voltage detection signal at a logic high level; The voltage detection circuit includes a first resistor to a fourth resistor, a first comparator, and a first diode circuit and a second diode circuit. The first end of the fourth resistor is electrically connected to an adjustable voltage generating circuit to receive the bias voltage. The second end of the fourth resistor is electrically connected to the first ends of the second resistor and the third resistor. The second ends of the second resistor and the third resistor are electrically connected to the negative input terminal and the positive input terminal of the first comparator, respectively. The output terminal of the first comparator outputs the low voltage detection signal. The first diode circuit is electrically connected to the second end of the second resistor, the first end of the first resistor is electrically connected to the second end of the third resistor, and the second end of the first resistor is electrically connected to the second diode circuit. The fourth resistor is a variable resistor and receives a first control signal to change its resistance value.

2. The supply voltage detection circuit according to claim 1, wherein: The adjustable voltage generating circuit includes a trimming resistor, a fifth resistor, and a voltage follower. A first end of the trimming resistor receives the supply voltage, a second end of the trimming resistor is electrically connected to the first end of the fifth resistor and the positive input end of the voltage follower, and an output end of the voltage follower is electrically connected to the negative input end of the voltage follower and is used to output the bias voltage. The trimming resistor is a variable resistor and receives a second control signal to change its resistance value.

3. A circuit system, characterized in that: The circuit system comprises: load; and The supply voltage detection circuit according to any one of claims 1 to 2, which is electrically connected to the load.

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