Processor, chip, electronic device and data processing method

Abstract

Embodiments of the present disclosure provide a processor, chip, electronic device, and data processing method. The processor includes: a first register file, the first register file including at least one first register group and at least one second register group, each of the first register group and the second register group including at least one register, each first register group being allocated to one thread, and each second register group being allocated to at least two threads; and a processing unit configured to schedule each of a plurality of threads and, in response to a data access request from a target thread in the plurality of threads, access a target register in the register group allocated to the target thread. Embodiments of the present disclosure implement data reuse between threads.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to processors, chips, electronic devices, and data processing methods. Background Art

[0002] To improve scheduling efficiency, many processors introduce hardware multi-threading technology. For example, a graphics processing unit (GPU) schedules the execution of multiple threads at the same time. Threads can form thread blocks and collaborate to complete an overall computing task. During collaborative computing, a large amount of data interaction is required between different threads. In order to increase the data transmission bandwidth, a register stack can be used for data reuse. For example, when performing a convolution operation, a feature map can be stored in a register stack first for multiple use by the operation unit. However, in conventional processor designs, register stacks are generally private to each thread, and different threads cannot reuse the data on the register stack. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides a processor, comprising: a first register stack, the first register stack comprising at least one first register group and at least one second register group, the first register group and the second register group each comprising at least one register, each first register group being used to be allocated to one thread, and each second register group being used to be allocated to at least two threads; and a processing unit, configured to schedule each thread among a plurality of threads, and access a target register in the register group allocated to the target thread in response to a data access request of a target thread among the plurality of threads.

[0004] In some embodiments, the data access request of the target thread carries the logical address of the target register; the processing unit is used to: map the logical address to the physical address of the target register; and access the target register based on the physical address.

[0005] In some embodiments, the processing unit is configured to: determine the physical address based on the total number of registers allocated to each preceding thread and the logical address when the target register is a register in the first register group; the preceding threads include threads having a thread number smaller than that of the target thread; and / or determine the physical address based on the total number of registers allocated to each thread and the logical address when the target register is a register in the second register group.

[0006] In some embodiments, the first register file is divided into at least one storage unit, each storage unit includes at least one first register group and at least one second register group; different storage units are physically isolated and correspond to different threads, the first register group included in one storage unit is used to be allocated to one thread corresponding to the storage unit, and the second register group included in one storage unit is used to be allocated to at least two threads corresponding to the storage unit; the processing unit is used to: when the target register is a register in the first register group, determine the storage unit where the target register is located based on the thread number of the target thread and the number of storage units, and determine the physical address based on the total number of register groups allocated to each previous thread, the number of storage units, and the logical address; the previous thread includes each thread with a thread number smaller than the target thread; and / or when the register accessed by the data access request is a register in the second register group, determine the storage unit where the target register is located based on the logical address and the number of storage units, and determine the physical address based on the total number of register groups allocated to each thread, the number of storage units, and the logical address.

[0007] In some embodiments, the target register is a register in the first register group; the processing unit is configured to: use data read from the target register as index information, and access the register in the second register group based on the index information.

[0008] In some embodiments, the processing unit is configured to: obtain index information read from the second register file; and access the target register based on the index information read from the second register file.

[0009] In some embodiments, the data access request includes an indication bit, and the indication bit is used to indicate whether to use the data read from the second register file as index information for accessing the target register.

[0010] In some embodiments, the processor further includes: an instruction path for sending a data access request to the target register; and an execution path for acquiring data transmitted by the target register in response to the data access request, and performing operations on the acquired data.

[0011] In some embodiments, the instruction path includes: an instruction reading unit for reading the data access request sent by the target thread; an instruction decoding unit for decoding the data access request read by the instruction reading unit; an instruction issuing unit for sending the decoded data access request to the target register; and / or the execution path includes: an operation unit for performing operation processing on the acquired data; and a memory access unit for outputting the operation result to the memory, and / or outputting the data stored in the memory to the operation unit for operation processing.

[0012] In some embodiments, each first register group includes the same number of registers.

[0013] In a second aspect, an embodiment of the present disclosure provides a chip, which includes the processor described in any embodiment of the present disclosure.

[0014] In a third aspect, an embodiment of the present disclosure provides an electronic device, which includes the chip described in any embodiment of the present disclosure.

[0015] In a fourth aspect, an embodiment of the present disclosure provides a data processing method, which is applied to a processing unit in a processor described in any embodiment of the present disclosure, and the method includes: scheduling each thread among multiple threads; and accessing a target register in a register group allocated to the target thread in response to a data access request of a target thread among the multiple threads.

[0016] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, which implements the method described in any embodiment when the program is executed by a processor.

[0017] The disclosed embodiment divides the register file into a first register group and at least one second register group, wherein the second register group can be assigned to at least two threads, that is, the second register group can be accessed by two or more threads together, thereby achieving data multiplexing between threads; in addition, since each first register group is assigned to only one thread, that is, the first register group can only be accessed by one thread alone, data between different threads still has a certain degree of data isolation.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0020] Figure 1This is a schematic diagram of how threads access register files in a multi-threaded environment in the related art.

[0021] Figure 2 Schematic diagram of the structure of the processor according to an embodiment of the present disclosure.

[0022] Figure 3 It is a schematic diagram of the mapping relationship between physical addresses and logical addresses in an embodiment of the present disclosure.

[0023] Figure 4A and Figure 4B They are schematic diagrams of the address mapping method of the register file in the embodiments of the present disclosure.

[0024] Figure 5 Schematic diagram of the positional relationship between the first register group and the second register group in an embodiment of the present disclosure.

[0025] Figure 6 and Figure 7 They are respectively schematic diagrams of the data calculation process of the embodiments of the present disclosure.

[0026] Figure 8 is a schematic diagram of a chip according to an embodiment of the present disclosure.

[0027] Figure 9 It is a flowchart of the data processing method of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0029] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms "a", "the" and "the" used in this disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. In addition, the term "at least one" herein means any combination of at least two of any one or more of a plurality of.

[0030] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0031] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present disclosure and to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings.

[0032] The design of high-performance processors is crucial in fields such as artificial intelligence and scientific computing. Improving processor performance in intensive computing scenarios requires addressing the memory wall problem, reducing external bandwidth requirements through data reuse, and improving the efficiency of computing units.

[0033] Traditional processor memory structures can be broadly divided into three layers: external memory, cache, and register file. The bandwidth structure follows the following pattern: external memory < cache < register file. Cache can be further divided into multiple layers, such as the L1 / L2 cache of the central processing unit (CPU). Data reuse is typically achieved through cache. Once data is stored in cache, two types of reuse can occur: 1) different computing units access the same data; 2) a single computing unit accesses the same cached data multiple times. This type of reuse effectively reduces data access to external memory.

[0034] To improve scheduling efficiency, many processors incorporate hardware multithreading. For example, GPUs can schedule the execution of multiple threads simultaneously. Threads can form thread groups and collaborate to complete a single computing task. During collaborative computing, threads exchange a large amount of data. Traditional processor designs typically utilize on-chip storage, such as CPU cache or GPU shared memory, to efficiently facilitate this inter-thread data exchange.

[0035] However, in intensive computing scenarios, sometimes the bandwidth of the on-chip storage unit still cannot meet the needs of the operation. In this case, the register stack can be further used for data reuse. For example, when performing a convolution operation, a feature map can be stored in the register stack first for multiple use by the operation unit. In conventional processor designs, the register stack is generally thread-private. Therefore, only the same thread can reuse the data on the register stack, and different threads cannot reuse the data on the register stack. For example, in Figure 1 In the example, thread 1 can only access registers 1, 2, and 3 in the register file; thread 2 can only access registers 4 and 5 in the register file; and thread 3 can only access registers 6, 7, and 8 in the register file. In this way, the data in the same register cannot be reused by multiple threads.

[0036] Based on this, the present disclosure provides a processor, see Figure 2 , the processor includes:

[0037] A first register file 201, the first register file 201 includes at least one first register group 2011 and at least one second register group 2012, each of the first register group 2011 and the second register group 2012 includes at least one register R, each first register group 2011 is allocated to one thread, and each second register group 2012 is allocated to at least two threads; and

[0038] The processing unit 202 is configured to schedule each thread among the multiple threads, and access a target register in a register group allocated to the target thread in response to a data access request of the target thread among the multiple threads.

[0039] The processor in the embodiments of the present disclosure may be a multi-threaded processor of various types, such as a CPU, a GPU, or a Neural Network Processing Unit (NPU). The present disclosure does not limit the type of processor. The processor may schedule multiple threads to process data in parallel so that the target register can be accessed by the threads.

[0040] In the embodiment of the present disclosure, the first register file 201 may include at least two register groups. The first register file 201 may be divided into a first register group 2011 and a second register group 2012. The number of first register groups 2011 and the number of second register groups 2012 are both greater than or equal to one, and the number of first register groups 2011 and the number of second register groups 2012 may be equal or unequal. The first register group 2011 may include at least one register, and the second register group 2012 may also include at least one register. The number of registers included in the first register group 2011 and the number of registers included in the second register group 2012 may be equal or unequal, and different first register groups 2011 may include the same or unequal number of registers.

[0041] In some embodiments, the number of first register groups 2011 may be determined based on the number of threads. For example, the number of first register groups 2011 may be equal to the number of threads, so that each thread may be allocated one first register group 2011. Alternatively, the number of first register groups 2011 may be an integer multiple of the number of threads, so that each thread may be allocated one or more first register groups 2011. For simplicity, Figure 2 In the example, the number of first register groups 2011 is 2, the number of second register groups 2012 is 1, the number of threads is 2, and each thread is assigned a first register group, where R represents a register. Those skilled in the art will appreciate that the above is merely an example. In actual applications, the number of first register groups 2011, the number of second register groups 2012, the number of threads, and / or the number of first register groups assigned to each thread may also take other values, which are not further described here. For ease of explanation, the following describes the solution of the embodiments of the present disclosure using the example of each thread being assigned a first register group, and each first register group having an equal number of registers.

[0042] The number of first register groups 2011, the number of second register groups 2012, the number of registers in the first register group 2011, and the number of registers in the second register group 2012 can be configured separately through configuration information. In some embodiments, the configuration information only needs to specify the number of first register groups 2011 and the number of second register groups 2012, without specifying which registers comprise the first register group 2011 and the second register group 2012. This provides greater configuration flexibility. The configuration information can be generated by a controller, and the processor can automatically specify a corresponding number of registers to comprise the first register group 2011 and the second register group 2012 based on the configuration information. When at least one of the number of first register groups 2011, the number of second register groups 2012, the number of registers in the first register group 2011, and the number of registers in the second register group 2012 needs to be changed, only the corresponding configuration information needs to be changed.

[0043] For ease of description, the first register group 2011 and the second register group 2012 are collectively referred to as register groups below. The register group mentioned below may be either the first register group 2011 or the second register group 2012 .

[0044] A first register group 2011 can only be assigned to one thread. After the assignment, the first register group 2011 is not visible to other threads. In this way, data isolation between different threads can be achieved. Each second register group 2012 can be assigned to at least two threads, so that the at least two threads can achieve data multiplexing. For example, in Figure 2 In the embodiment, one of the first register groups 2011 may be allocated to thread 0, another first register group 2011 may be allocated to thread 1, and the second register group 2012 may be allocated to both thread 0 and thread 1.

[0045] Each thread can access a target register in the register group assigned to the thread to read data from or write data to the target register. The number of target registers can be greater than or equal to 1. Each thread can be scheduled by the processing unit 202. When scheduling a target thread, the processing unit 202 can access the target register in the register group assigned to the target thread in response to a data access request from the target thread.

[0046] The data access request can carry the logical address of the target register. The processing unit needs to map the logical address to the physical address of the target register, and then access the target register based on the physical address. Among them, the logical address of a register can be used to represent the identification information of the register in the register group assigned to a certain thread, and the physical address of a register can be used to represent the identification information of the register in the register stack. The physical address and logical address of each register can be sequentially numbered using integers (for example, 0, 1, 2, 3, ...). The logical addresses of registers in register groups assigned to different threads can be the same, but the physical addresses of different registers must be different. For example, in Figure 3 In the illustrated embodiment, registers with physical addresses 0, 1, and 2 are in the register group assigned to thread 0, and their logical addresses are 0, 1, and 2, respectively. Registers with physical addresses 3, 4, and 5 are in the register group assigned to thread 1, and their logical addresses are also 0, 1, and 2, respectively.

[0047] The processing unit 202 can uniquely determine the target register by mapping the logical address to the physical address so as to access the correct register. For example, for thread 1, when the logical address of the target register it accesses is 0, it is necessary to map the logical address to the physical address of the register in the first register file 201 (i.e., 3). In some embodiments, the logical addresses of the registers in the first register group and the registers in the second register group can be set independently. For example, in Figure 2 In the illustrated embodiment, the logical addresses of the registers in the first register group assigned to thread 0 may be integers starting from 0 (e.g., 0, 1, 2, 3, ...), and the logical addresses of the registers in the second register group assigned to thread 0 may also be integers starting from 0 (e.g., 0, 1, 2, 3, ...). Since the position of the first register group in the register file is different from the position of the second register group in the register file, the processing unit 202 may determine the physical address of the target register based on the type of the register group to which the target register belongs and the position of the register group to which the target register belongs in the register file. The type of a register group is used to indicate whether the register group is the first register group or the second register group.

[0048] Specifically, when the target register is a register in the first register group, the physical address can be determined based on the total number of registers allocated to each prior thread and the logical address. The prior threads include threads whose thread numbers (i.e., thread IDs) are smaller than the target thread. For example, if the thread IDs of the threads are integers such as 0, 1, and 2, and the target thread has a thread ID of 2, then the prior threads include threads with thread ID 0 and threads with thread ID 1. The total number of registers allocated to each prior thread can be obtained by summing the number of registers allocated to each prior thread. When the number of registers allocated to each thread is equal, the total number of registers allocated to each prior thread can be obtained by multiplying the number of registers allocated to the prior thread by the number of registers allocated to the single thread. When k (k is a positive integer) first register groups are allocated to each thread, the number of registers allocated to the single thread is the total number of registers included in these k register groups.

[0049] like Figure 4A As shown, assuming that the total number of threads is N, k=1, that is, the total number of first register groups is also N, and assuming that the number of registers included in each first register group is M, the number of registers included in the second register group is P, and the second register group is shared by all N threads, the storage space formed by the second register group is also called shared space. In the case where the target register is a register in the first register group, the physical address physical_addr of the target register can be recorded as:

[0050] physical_addr=reg_id+thread_id*M;

[0051] Wherein, reg_id is the logical address of the target register, thread_id is the thread ID, and M is the number of registers in the first register group. An adder and a multiplier can be used to implement the addition and multiplication operations in the above formula respectively to obtain the physical address.

[0052] In the case where the target register is a register in the second register group, the physical address may be determined based on the total number of registers allocated to each thread and the logical address. Figure 4A Taking the case shown as an example, when the target register is a register in the second register group, the physical address physical_addr of the target register can be recorded as:

[0053] physical_addr = reg_id + N*M;

[0054] Where N is the total number of threads.

[0055] In the above embodiment, the physical addresses of the registers in the second register group are greater than the physical addresses of the registers in the first register group. That is, the registers in the second register group are the last registers in the register stack, and the registers in the first register group are the first registers in the register stack (case 1). In actual applications, the physical addresses of the registers in the second register group may also be smaller than the physical addresses of the registers in the first register group. That is, the registers in the second register group are the first registers in the register stack, and the registers in the first register group are the last registers in the register stack (case 2). Alternatively, several registers in the middle of the register stack may be used as registers in the second register group, and the registers at the front and back of the register stack may be used as registers in the first register group (case 3).

[0056] There are three distribution situations of the position relationship between the first register group and the second register group in the register stack: Figure 5 As shown. The gray squares represent registers in the second register group, the white squares represent registers in the first register group, and the numbers in the squares represent the physical addresses of each register. Under different positional relationships, the physical address is calculated differently. For example, it is still assumed that the total number of threads is N, k=1, that is, the total number of first register groups is also N, and it is assumed that the number of registers included in each first register group is M, the number of registers included in the second register group is P, and the second register group is shared by all N threads. In the above case 2, when the target register is a register in the first register group, the physical address physical_addr of the target register can be recorded as:

[0057] physical_addr=P+reg_id+thread_id*M;

[0058] In a case where the target register is a register in the second register group, the physical address of the target register is equal to the logical address of the target register.

[0059] In the third case above, when the target register is a register in the first register group, assuming that the number of first register groups located before the second register group in the register file is X, the physical address physical_addr of the target register can be recorded as:

[0060] physical_addr=reg_id+thread_id*M,0<thread_id<X;

[0061] physical_addr=P+reg_id+thread_id*M, thread_id≥X;

[0062] In the case where the target register is a register in the second register group, the physical address physical_addr of the target register can be recorded as:

[0063] physical_addr=reg_id+X*M.

[0064] In some embodiments, the first register file is divided into at least one storage unit (Bank), each storage unit including at least one first register group and at least one second register group; different storage units are physically isolated from each other, and different storage units correspond to different threads. The first register group included in a storage unit is used to allocate to one thread corresponding to the storage unit, and the second register group included in a storage unit is used to allocate to at least two threads corresponding to the storage unit. This approach is called interleaving. For register files with multiple banks, to ensure uniform access, the shared space will be evenly distributed on each bank through interleaving.

[0065] by Figure 4B For example, there are K banks, and a shared space of P registers is reserved in each bank. The total shared space capacity is K*P. The shared storage space on each storage unit can be allocated to any thread. The logical addresses of the shared space are 0 to K*P-1. The logical addresses of the registers in the shared space (i.e., the second register group) can be interleaved in each bank. As shown in the figure, the logical addresses of the registers in the second register group on Bank_0 are K*(0 to P-1), that is, the register numbers are 0, K, 2K, ..., (P-1)*K respectively; the logical addresses of the registers in the second register group on Bank_1 are 1+K*(0 to P-1), that is, the register numbers are 1, K+1, 2K+1, ..., (P-1)*K+1, and so on. For example, assuming K=3 and P=5, the registers in the second register group on Bank_0 are numbered 0 / 3 / 6 / 9 / 12, the registers in the second register group on Bank_1 are numbered 1 / 4 / 7 / 10 / 13, and the registers in the second register group on Bank_2 are numbered 2 / 5 / 8 / 11 / 14. Of course, those skilled in the art will appreciate that the interleaving method is not limited to this.

[0066] Each Bank also reserves dedicated storage space for each thread (i.e., the first register group). For example, Bank_0 reserves dedicated storage space for thread 0, thread K, ..., thread NK, and Bank_1 reserves dedicated storage space for thread 1, thread K+1, ..., thread N-K+1. For ease of explanation, it is assumed here that the size of the dedicated storage space reserved for each thread on a Bank is M, that is, the logical address of each thread on a Bank is 0 to M-1. The registers with addresses 0 to M-1 reserved for a thread constitute a first register group, that is, the first register group allocated to a thread includes M registers.

[0067] Among them, different storage units correspond to different threads. Taking the case where the number of threads is 9 and the number of storage units is 3 as an example, storage unit Bank_0 corresponds to thread 0, thread 3 and thread 6, and the first register group included in storage unit Bank_0 can be respectively allocated to thread 0, thread 3 and thread 6. Storage unit Bank_1 corresponds to thread 1, thread 4 and thread 7, and the first register group included in storage unit Bank_1 can be respectively allocated to thread 1, thread 4 and thread 7. Storage unit Bank_2 corresponds to thread 2, thread 5 and thread 8, and the first register group included in storage unit Bank_2 can be respectively allocated to thread 2, thread 5 and thread 8. Of course, in addition to the interleaving method described in the above embodiment, other interleaving methods can also be used, and they will not be given as examples here.

[0068] In the case of multiple banks, if the target register is a register in the first register bank, the bank in which the target register is located can be determined based on the target thread number and the number of banks, and the physical address can be determined based on the total number of register banks, the number of banks, and the logical address allocated to each preceding thread; the preceding threads include threads with thread numbers lower than the target thread. For example, the bank number physical_bank in which the target register is located can be expressed as:

[0069] physical_bank=thread_id%K;

[0070] The physical address physical_addr of the target register in the corresponding storage unit can be recorded as:

[0071] physical_addr=reg_id+thread_id / K*M;

[0072] Wherein, % represents the remainder operator, and the physical meanings of the other symbols in the formula are the same as those in the aforementioned embodiment. Still taking the example of the number of threads N being 9 and the number of storage units K being 3, and assuming that M=3, the threads are numbered 0 to 8, and the physical addresses of the registers in the first register group assigned to each thread are 0 to 2. In the case where the target register is the register with a physical address of 1 in the first register group assigned to thread 0, the number of the storage unit where the target register is located is 0%3, i.e., Bank_0, and the physical address of the target register on Bank_0 can be recorded as 1+0 / 3*9=1. In the case where the target register is the register with a physical address of 2 in the first register group assigned to thread 1, the number of the storage unit where the target register is located is 1%3, i.e., Bank_1, and the physical address of the target register on Bank_1 can be recorded as 2+1 / 3*9=5.

[0073] If the register accessed by the data access request is a register in the second register bank, the storage unit where the target register is located can be determined based on the logical address and the number of storage units, and the physical address can be determined based on the total number of register banks allocated to each thread, the number of storage units, and the logical address. For example, the physical_bank number of the storage unit where the target register is located can be recorded as:

[0074] physical_bank=reg_id%K;

[0075] The physical address physical_addr of the target register in the corresponding storage unit can be recorded as:

[0076] physical_addr=reg_id / K+N / K*M.

[0077] Assume that the number of threads N is 9, the number of storage units K is 3, and M = 3, and assume that P = 5. If the target register is register numbered 6 in the second register group, the number of the storage unit where the target register is located is 6%3=0, that is, the target register is in Bank_0, and the physical address of the target register is 6 / 3+9 / 3*3=11.

[0078] In some embodiments, K may be set to a power of 2, and K may be set to an integer multiple of N. If the value of reg_id is not an integer, it may be rounded down so that the obtained physical address is an integer.

[0079] After the target register is determined based on the above method, the target register can be accessed, for example, data can be read from the target register. In some embodiments, the data read from the target register can be used as the access address of another register to access the data in another register. For example, the target register can be a register in the first register group. The processing unit 202 can first obtain the physical address of the target register (i.e., the index register number), and use the data read from the target register as index information (i.e., address information, i.e., the index register value in the figure) based on the index register number, and access the register in the second register group based on the index information. For example, assuming that the logical address of the target register in the first register group is A1, the physical address of the target register can be calculated by the above method, assuming it is A2, and access the register with the physical address A2 to obtain the data A3 therein, and use A3 as the logical address of a register in the second register group, and calculate the physical address of the register based on A3, assuming it is address A4, and then the register with address A4 can be accessed. The above process can be found in Figure 6 The instruction path can read instructions (i.e., the aforementioned data access requests) sent by multiple threads based on multi-threaded context information, decode the data access requests, and send them to the execution path. The data access requests can be used to access a target register in the first register group. After obtaining the data in the target register, the data is used as index information to access registers in the second register group. This method is called indirect addressing.

[0080] The above solution can be extended to processors containing parallel computing units, such as CPUs or GPUs containing Single Instruction Multiple Data (SIMD) units. Figure 7, the processing unit 202 can first obtain the physical address of the register to be accessed in the second register file (i.e., the index register number), and obtain the index information read from the second register file based on the index register number (i.e., the index register value in the figure); and access the target register based on the index information read from the second register file. The target register here can be either a register in the first register group or a register in the second register group. The main idea of ​​the embodiment of the present disclosure is that the processor can include two independent register files, wherein the second register file can be a vector register file for storing SIMD data or single instruction multiple threads (SIMT) data for parallel computing; the first register file can be a scalar register file for storing simple scalar data or control information. The value read from the scalar register file can be used as an index to access the vector register file, and then the data obtained from the vector register file is sent to the execution path. Since the core operation occurs in the vector register file, the main purpose is to increase the support of shared space for the vector register file.

[0081] In some embodiments, in addition to indirect addressing, data read from a register can also be used directly for data operations. This approach is referred to as direct addressing. In direct addressing, data read from registers included in the second register file or from registers included in the first register group is no longer used as index information to access other registers, but is instead used directly to perform data operations (e.g., multiplication, addition, etc.). To facilitate the distinction between direct and indirect addressing, the data access request can include an indicator bit that indicates whether the data read from the target register will be used as the index information. Specifically, the indicator bit can have two indication states: when the indicator bit is in a first indication state, the data read from the target register is determined to be used as the index information; when the indicator bit is in a second indication state, the data read from the target register is determined not to be used as the index information. In some embodiments, the first indication state and the second indication state can be represented by at least one data bit. For example, the first indication state can be represented by binary data "0," and the second indication state can be represented by binary data "1." Of course, the representation of the indication state is not limited to this. Those skilled in the art may use other methods to represent different indication states based on actual circumstances, and these are not listed here.

[0082] In some embodiments, the processor further comprises an instruction path for sending a data access request to the target register; and an execution path for acquiring data transmitted by the target register in response to the data access request, and performing arithmetic processing on the acquired data. The solution of the disclosed embodiment can be applied to both the direct addressing scenario and the indirect addressing scenario.

[0083] Specifically, the instruction path may include: an instruction fetch unit for fetching a data access request sent by the target thread; an instruction decode unit for decoding the data access request read by the instruction fetch unit; and an instruction emit unit for transmitting the decoded data access request to the target register. The target register may output stored data to the execution path for computational processing, or may return the stored data as index information to the instruction emit unit, so that the instruction emit unit, based on the index information, transmits the data stored in the corresponding register to the execution path for computational processing.

[0084] In some embodiments, the execution path includes: an operation unit for performing operation processing on the acquired data; and a memory access unit for outputting the operation result to the memory, and / or outputting the data stored in the memory to the operation unit for operation processing. The operation unit may include one or more sub-operation units, such as an addition operation unit, a multiplication operation unit, a convolution operation unit, etc. The number and type of sub-operation units included in the operation unit can be set based on actual needs. The memory access unit is used to realize data transmission between the operation unit and the memory. When the data required for the operation is not included in the register file, the memory can be accessed through the memory access unit to obtain the corresponding data. Furthermore, the data obtained from the scalar register can also be output to the scalar execution unit as data that needs to be operated for processing.

[0085] See also Figure 8 The present disclosure also provides a chip, including a processor 801. The processor 801 can be any of the processors described in the above embodiments. In some embodiments, the chip can be used in an AI accelerator card. In some embodiments, the chip also includes a controller 802 for configuring at least one of the following information: a first number of registers included in the first register group, a second number of registers included in the second register group, the number of the first register group, and the number of the second register group.

[0086] The details of the embodiments of the present disclosure are detailed in the aforementioned processor embodiments and will not be repeated here.

[0087] An embodiment of the present disclosure further provides an electronic device, comprising the chip described in any of the above embodiments.

[0088] See also Figure 9 The present disclosure also provides a data processing method, which is applied to a processing unit in a processor according to any embodiment of the present disclosure. The method includes:

[0089] Step 901: Scheduling each thread among multiple threads;

[0090] Step 902: In response to a data access request of a target thread among the multiple threads, access a target register in a register group allocated to the target thread.

[0091] In some embodiments, the data access request of the target thread carries the logical address of the target register; and in response to the data access request of the target thread among the multiple threads, accessing the target register in the register group allocated to the target thread includes: mapping the logical address to the physical address of the target register; and accessing the target register based on the physical address.

[0092] In some embodiments, mapping the logical address to the physical address of the target register includes: when the target register is a register in the first register group, determining the physical address based on the total number of registers allocated to each previous thread and the logical address; the previous threads include each thread having a thread number smaller than the target thread; and / or when the target register is a register in the second register group, determining the physical address based on the total number of registers allocated to each thread and the logical address.

[0093] In some embodiments, the first register file is divided into at least one storage unit, each storage unit includes at least one first register group and at least one second register group; different storage units are physically isolated and correspond to different threads, the first register group included in one storage unit is used to be allocated to one thread corresponding to the storage unit, and the second register group included in one storage unit is used to be allocated to at least two threads corresponding to the storage unit; mapping the logical address to the physical address of the target register includes: when the target register is a register in the first register group, determining the storage unit where the target register is located based on the thread number of the target thread and the number of storage units, and determining the physical address based on the total number of register groups allocated to each previous thread, the number of storage units, and the logical address; the previous thread includes each thread with a thread number smaller than the target thread; and / or when the register accessed by the data access request is a register in the second register group, determining the storage unit where the target register is located based on the logical address and the number of storage units, and determining the physical address based on the total number of register groups allocated to each thread, the number of storage units, and the logical address.

[0094] In some embodiments, the target register is a register in the first register group; and in response to a data access request of a target thread among the multiple threads, accessing the target register in the register group assigned to the target thread includes: using data read from the target register as index information, and accessing the register in the second register group based on the index information.

[0095] In some embodiments, in response to a data access request of a target thread among the multiple threads, accessing a target register in a register group assigned to the target thread includes: obtaining index information read from a second register file; and accessing the target register based on the index information read from the second register file.

[0096] In some embodiments, the data access request includes an indication bit, and the indication bit is used to indicate whether to use the data read from the second register file as index information for accessing the target register.

[0097] In some embodiments, the method further includes: sending a data access request to the target register through an instruction path; acquiring data transmitted by the target register in response to the data access request through an execution path, and performing arithmetic processing on the acquired data.

[0098] In some embodiments, the sending of the data access request to the target register through the instruction path includes: reading the data access request sent by the target thread through the instruction reading unit in the instruction path; decoding the data access request read by the instruction reading unit through the instruction decoding unit in the instruction path; sending the decoded data access request to the target register through the instruction emission unit in the instruction path; and / or obtaining the data transmitted by the target register in response to the data access request through the execution path, and performing operation processing on the obtained data, including: performing operation processing on the obtained data through the operation unit in the execution path; and outputting the operation result to the memory through the memory access unit in the execution path, and / or outputting the data stored in the memory to the operation unit for operation processing.

[0099] In some embodiments, each first register group includes the same number of registers.

[0100] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, which implements the method described in any of the aforementioned embodiments when the program is executed by a processor.

[0101] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0102] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that the embodiments of this specification can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solutions of the embodiments of this specification, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments of this specification.

[0103] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email transceiver, game console, tablet computer, wearable device, or any combination of these devices.

[0104] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device embodiment described above is merely illustrative, wherein the modules described as separate components may or may not be physically separated, and when implementing the embodiment scheme of this specification, the functions of each module can be implemented in the same one or more software and / or hardware. It is also possible to select some or all of the modules according to actual needs to achieve the purpose of the embodiment scheme. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0105] The above is only a specific implementation of the embodiment of this specification. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the embodiment of this specification. These improvements and modifications should also be regarded as the scope of protection of the embodiment of this specification.

Claims

1. A processor, characterized in that: The processor includes: a first register file, the first register file including at least one first register group and at least one second register group, the first register group and the second register group each including at least one register, each first register group being allocated to one thread, and each second register group being allocated to at least two threads; and A processing unit is configured to schedule each of a plurality of threads and, in response to a data access request of a target thread among the plurality of threads, access a target register in a register group assigned to the target thread; the data access request of the target thread carries a logical address of the target register; the specific manner in which the processing unit accesses the target register in the register group assigned to the target thread comprises: mapping the logical address to a physical address of the target register; and accessing the target register based on the physical address; The first register file is divided into at least one storage unit, each storage unit includes at least one first register group and at least one second register group; different storage units are physically isolated from each other, and different storage units correspond to different threads. The first register group included in a storage unit is allocated to one thread corresponding to the storage unit, and the second register group included in a storage unit is allocated to at least two threads corresponding to the storage unit; the processing unit is configured to: If the target register is a register in the first register group, determining the storage unit where the target register is located based on the thread number of the target thread and the number of the storage units, and determining the physical address based on the total number of register groups allocated to each preceding thread, the number of storage units, and the logical address; the preceding threads include each thread having a thread number smaller than that of the target thread; and / or When the register accessed by the data access request is a register in the second register group, the storage unit where the target register is located is determined based on the logical address and the number of storage units, and the physical address is determined based on the total number of register groups allocated to each thread, the number of storage units, and the logical address.

2. The processor according to claim 1, wherein: The processing unit is used for: When the target register is a register in the first register group, determining the physical address based on the total number of registers allocated to each preceding thread and the logical address; the preceding threads include threads having thread numbers smaller than the target thread; and / or In a case where the target register is a register in the second register group, the physical address is determined based on the total number of registers allocated to each thread and the logical address.

3. The processor according to claim 1, wherein: The target register is a register in the first register group; the processing unit is configured to: The data read from the target register is used as index information, and the registers in the second register group are accessed based on the index information.

4. The processor according to claim 1, wherein: The processing unit is used for: Obtaining index information read from the second register file; The target register is accessed based on the index information read from the second register file.

5. The processor according to claim 4, wherein: The data access request includes an indication bit, and the indication bit is used to indicate whether to use the data read from the second register file as index information for accessing the target register. The processor according to claim 1 , wherein: The processor further includes: an instruction path for sending a data access request to the target register; and The execution path is used to obtain data transmitted by the target register in response to the data access request, and perform operation processing on the obtained data.

7. The processor according to claim 6, wherein: The instruction path includes: An instruction reading unit, configured to read a data access request sent by the target thread; an instruction decoding unit, configured to decode the data access request read by the instruction reading unit; an instruction issuing unit, configured to send the decoded data access request to the target register; and / or The execution path includes: A computing unit, configured to perform computing on the acquired data; and The memory access unit is used to output the operation result to the memory and / or output the data stored in the memory to the operation unit for operation processing.

8. The processor according to claim 1, wherein: Each first register group includes the same number of registers.

9. A chip, characterized in that: The chip includes the processor according to any one of claims 1 to 8.

10. The chip according to claim 9, characterized in that The chip further includes: A controller is used to configure at least one of the following information: first quantity information of registers included in the first register group, The second register group includes second quantity information of registers, the number of the first register group, The number of the second register group.

11. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9 or 10.

12. A data processing method, characterized in that: The processing unit applied to the processor according to any one of claims 1 to 8, the method comprising: Scheduling each of the multiple threads; In response to a data access request of a target thread among the plurality of threads, a target register in a register group allocated to the target thread is accessed.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to claim 12 is implemented.

Images