Display panel and display device

Abstract

The present application provides a display panel and a display device, wherein the display panel includes a pixel circuit and a first shift register circuit; the pixel circuit includes a driving transistor and a first transistor, and the driving current generated by the driving transistor flows through the first transistor; the output end of the first shift register circuit is connected to the first end of the first scan line, and the first scan line is connected to the control end of the first transistor in a plurality of pixel circuits; the same first scan line is electrically connected to the first pixel circuit and the second pixel circuit, the distance between the first end of the first scan line and the first pixel circuit is smaller than the distance between the first end of the first scan line and the second pixel circuit, and the channel width-to-length ratio of the first transistor in the first pixel circuit is smaller than the channel width-to-length ratio of the first transistor in the second pixel circuit. The present application makes it possible for the opening degree of the first transistor in the second pixel circuit to be the same as the opening degree of the first transistor in the first pixel circuit, which is conducive to improving the brightness uniformity of the far end and the near end of the output of the first shift register circuit.

Description

[Technical field]

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0002] Organic light-emitting diode (OLED) display panels have the advantages of simple manufacturing process, low power consumption, light weight, fast response speed, wide viewing angle, high resolution and wide temperature characteristics, and have broad market application prospects. Among them, OLED devices are current-type organic light-emitting devices, whose luminous brightness is controlled by current and are very sensitive to changes in current.

[0003] In existing OLED display panels, the OLED is usually driven by a pixel circuit to emit light, and multiple pixel circuits can be driven by the same shift register circuit. However, the output signal of the shift register circuit usually has a voltage drop, which will cause the multiple pixel circuits driven by it to transmit different light-emitting drive currents to the OLED device, resulting in different brightness between different areas in the display panel, affecting the display effect. [Summary of the invention]

[0004] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, which includes a light-emitting element, a pixel circuit and a first shift register circuit; the pixel circuit includes a driving transistor and a first transistor, the driving transistor is used to provide a driving current for the light-emitting element, and the driving current flows through the first transistor; the output end of the first shift register circuit is electrically connected to the first end of the first scan line, and the first scan line is electrically connected to the control end of the first transistor in a plurality of pixel circuits; wherein the plurality of pixel circuits electrically connected to the same first scan line include a first pixel circuit and a second pixel circuit; along the extension direction of the first scan line, the distance between the first end of the first scan line and the first pixel circuit is smaller than the distance between the first end of the first scan line and the second pixel circuit, and the channel width-to-length ratio of the first transistor in the first pixel circuit is smaller than the channel width-to-length ratio of the first transistor in the second pixel circuit.

[0006] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0007] In an embodiment of the present application, along the extension direction of the first scan line, the control voltage received by the first transistor in the second pixel circuit farther from the first end of the first scan is smaller than the control voltage received by the first transistor in the first pixel circuit closer to the first end of the first scan. By setting the channel width-to-length ratio of the first transistor in the second pixel circuit to be greater than the channel width-to-length ratio of the first transistor in the first pixel circuit, it is possible to make the opening degree of the first transistor in the second pixel circuit the same as the opening degree of the first transistor in the first pixel circuit, which is beneficial to reducing the resistance difference between the first transistor in the second pixel circuit and the first transistor in the first pixel circuit, thereby helping to reduce the brightness difference of the light-emitting elements driven respectively by the second pixel circuit and the first pixel circuit, and further helping to improve the brightness uniformity of the display panel and improve the display effect.

Brief Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0009] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0010] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0011] Figure 3 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0012] Figure 4 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0013] Figure 5 A schematic diagram of a first shift register circuit driving a pixel circuit related to the present application;

[0014] Figure 6 A comparison diagram of the channel width-to-length ratio of a first transistor in a first pixel circuit and a second pixel circuit provided in an embodiment of the present application;

[0015] Figure 7 A comparison diagram of the channel width-to-length ratio of the first transistor in another first pixel circuit and a second pixel circuit provided in an embodiment of the present application;

[0016] Figure 8 A schematic diagram of a gradual change in the channel width-to-length ratio of a first transistor provided in an embodiment of the present application;

[0017] Fig. 9 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application;

[0018] Fig.10 A schematic diagram of another display panel provided in an embodiment of the present application;

[0019] Fig.11 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application;

[0020] Fig.12 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application;

[0021] Fig.13 for Figure 4 A schematic diagram of a pixel circuit shown;

[0022] Fig.14 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0023] Fig.15 A schematic diagram of a shift register circuit driving a pixel circuit related to the present application;

[0024] Fig.16 A schematic diagram of a first shift register circuit driving a pixel circuit group related to the present application;

[0025] Fig.17 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application;

[0026] Fig.18 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application;

[0027] Fig.19 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application;

[0028] Fig. 20 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0029] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0031] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0032] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0034] It should be understood that, although the terms first, second, etc. may be used to describe transistors, pixel circuits, pixel circuit groups, shift register circuits, etc. in the embodiments of the present application, these transistors, pixel circuits, pixel circuit groups, shift register circuits, etc. should not be limited to these terms. These terms are only used to distinguish transistors, pixel circuits, pixel circuit groups, shift register circuits, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first pixel circuit may also be referred to as the second pixel circuit, and similarly, the second pixel circuit may also be referred to as the first pixel circuit.

[0035] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0036] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application, Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 3 A schematic diagram of another pixel circuit provided in an embodiment of the present application, Figure 4 A schematic diagram of another pixel circuit provided in an embodiment of the present application is shown. Figure 5 A schematic diagram of a first shift register circuit driving a pixel circuit related to the present application.

[0037] The present application embodiment provides a display panel 100, Figures 1 to 4As shown, the display panel 100 includes a light emitting element 10, a pixel circuit 20 and a first shift register circuit 30. The pixel circuit 20 includes a driving transistor Td and a first transistor T1, and the driving transistor Td is used to provide a driving current for the light emitting element 10, and the driving current flows through the first transistor T1. In other words, the driving current flowing to the light emitting element 10 passes through the first transistor T1, and the driving transistor Td, the first transistor T1 and the light emitting element 10 are located in the same current loop.

[0038] Specifically, Figure 2-Figure 4 As shown, the pixel circuit 20 includes a power supply voltage writing module 21 and a light emitting control module 22, wherein the input terminal 211 of the power supply voltage writing module 21 is electrically connected to the first power supply voltage terminal VDD. The output terminal 212 of the power supply voltage writing module 21 is electrically connected to the first electrode of the driving transistor Td. The input terminal 221 of the light emitting control module 22 is electrically connected to the second electrode of the driving transistor Td, and the output terminal 222 is electrically connected to the input terminal 11 of the light emitting element 10. Optionally, the first electrode of the driving transistor Td may be its source electrode, and the second electrode of the driving transistor Td may be its drain electrode. In other embodiments, the first electrode of the driving transistor Td may be its drain electrode, and the second electrode of the driving transistor Td may be its source electrode.

[0039] It is understandable that the driving current received by the light-emitting element 10 will flow through the power supply voltage writing module 21, the driving transistor Td and the light-emitting control module 22, and the resistance values ​​of the power supply voltage writing module 21 and the light-emitting control module 22 will affect the magnitude of the driving current received by the light-emitting element 10.

[0040] like Figure 2 As shown, the first transistor T1 may be located in the power supply voltage writing module 21, that is, the first transistor T1 is connected in series between the first power supply voltage terminal VDD and the driving transistor Td. Figure 3 As shown, the first transistor T1 is located in the light emitting control module 22 , that is, the first transistor T1 is connected in series between the driving transistor Td and the input terminal 11 of the light emitting element 10 .

[0041] In addition, if Figure 4 As shown, the pixel circuit 20 may further include two first transistors T1, one first transistor T1 is located in the power supply voltage writing module 21, and the other first transistor T1 is located in the light emitting control module 22. That is, one first transistor T1 is connected in series between the first power supply voltage terminal VDD and the driving transistor Td, and the other first transistor T1 is connected in series between the driving transistor Td and the input terminal 11 of the light emitting element 10.

[0042] Optionally, the light emitting element 10 is an organic light emitting diode, and the input terminal 11 of the light emitting element 10 is the anode thereof.

[0043] Combination Figure 1 and Figure 5 , the display panel 100 further includes a first scan line S1, which may extend along the first direction X. Optionally, the display panel 100 includes a plurality of first scan lines S1, which extend along the first direction X and are arranged along the second direction Y. A plurality of pixel circuits 20 in the display panel 100 may be arranged in an array along the first direction X and the second direction Y, and at least part of the pixel circuits 20 arranged along the first direction X may be electrically connected to the same first scan line S1. The output end 31 of the first shift register circuit 30 is electrically connected to the first end S11 of the first scan line S1, and the first scan line S1 is electrically connected to the control end of the first transistors T1 in the plurality of pixel circuits 20. That is, the signal transmitted by the same first shift register circuit 30 may be transmitted to the first transistors T1 in the plurality of pixel circuits 20 through the first scan line S1 electrically connected thereto, and control the switching states of these first transistors T1.

[0044] Among them, the multiple pixel circuits 20 electrically connected to the same first scan line S1 include a first pixel circuit 20A and a second pixel circuit 20B. Along the extension direction of the first scan line S1, that is, along the first direction X, the distance between the first end S11 of the first scan line S1 and the first pixel circuit 20A is smaller than the distance between it and the second pixel circuit 20B, and the channel width-to-length ratio of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio of the first transistor T1 in the second pixel circuit 20B.

[0045] That is, along the extension direction of the first scan line S1, the distance between the first pixel circuit 20A and the output end 31 of the first shift register circuit 30 is smaller than the distance between the second pixel circuit 20B and the output end 31 of the first shift register circuit 30. At this time, the channel width-to-length ratio of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio of the first transistor T1 in the second pixel circuit 20B.

[0046] Figure 6 A comparison diagram of the channel width-to-length ratio of a first transistor in a first pixel circuit and a second pixel circuit provided in an embodiment of the present application, Figure 7 A comparison diagram of the channel width-to-length ratio of the first transistor in another first pixel circuit and a second pixel circuit provided in an embodiment of the present application.

[0047] It can be understood that the channel width-to-length ratio of the first transistor T1 is the ratio of the channel width W of the first transistor T1 to its channel length L, that is, the channel width-to-length ratio of the first transistor T1 is W / L.

[0048] Specifically, Figure 6 and Figure 7As shown, along the thickness direction of the display panel 100, the portion where the active layer YC of the first transistor T1 overlaps with the gate of the first transistor T1 is the channel of the first transistor T1, and the portion where the first scan line S1 overlaps with the active layer YC of the first transistor T1 can be the gate of the first transistor T1, that is, the channel of the first transistor T1 can be the portion where its active layer YC overlaps with the first scan line S1.

[0049] The length of the channel of the first transistor T1 in the extension direction of the active layer YC may be the channel length L of the first transistor T1, and the width of the channel of the first transistor T1 in the extension direction of the first scan line S1 may be the channel width W of the first transistor T1. The extension direction of the active layer YC intersects with the extension direction of the first transistor T1. In some optional embodiments, the extension direction of the active layer YC is perpendicular to the extension direction of the first transistor T1.

[0050] Alternatively, if Figure 6 As shown, the channel length of the first transistor T1 in the first pixel circuit 20A is L1 and the channel width is W1, and the channel length of the first transistor T1 in the second pixel circuit 20B is L2 and the channel width is W2. The channel length L1 of the first transistor T1 in the first pixel circuit 20A is the same as the channel length L2 of the first transistor T1 in the second pixel circuit 20B, and the channel width W1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 20B, that is, L1=L2, W1<W2, so that the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B, that is, W1 / L1<W2 / L2.

[0051] Alternatively, if Figure 7 As shown, the channel length of the first transistor T1 in the first pixel circuit 20A is L1 and the channel width is W1, and the channel length of the first transistor T1 in the second pixel circuit 20B is L2 and the channel width is W2. The channel width W1 of the first transistor T1 in the first pixel circuit 20A is the same as the channel width W2 of the first transistor T1 in the second pixel circuit 20B, and the channel length L1 of the first transistor T1 in the first pixel circuit 20A is greater than the channel length L2 of the first transistor T1 in the second pixel circuit 20B, that is, W1=W2, L1>L2. As a result, the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit 20A is less than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B, that is, W1 / L1<W2 / L2.

[0052] In addition, while ensuring that the channel width-to-length ratio of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio of the first transistor T1 in the second pixel circuit 20B, the channel width W1 of the first transistor T1 in the first pixel circuit 20A can be set to be different from the channel width W2 of the first transistor T1 in the second pixel circuit 20B, and the channel length L1 of the first transistor T1 in the first pixel circuit 20A can be set to be different from the channel length L2 of the first transistor T1 in the second pixel circuit 20B.

[0053] For example, the channel width W1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 20B, and the channel length L1 of the first transistor T1 in the first pixel circuit 20A is larger than the channel length L2 of the first transistor T1 in the second pixel circuit 20B, that is, W1<W2, L1>L2. Thus, the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B, that is, W1 / L1<W2 / L2.

[0054] The inventor of the present application has found through research that, since the first scan line S1 has a resistor, the signal transmitted by the first shift register circuit 30 will generate a voltage drop on the first scan line S1, which results in different control voltages received by the first transistors T1 in different pixel circuits 20, and along the extension direction of the first scan line S1, the farther the first transistor T1 is from the output end 31 of the first shift register circuit 30, the smaller the control voltage received. If the control voltages received by multiple first transistors T1 of the same structure are different, there will be differences in the degree of their opening or closing, resulting in differences in the resistance values ​​of the first transistors T1, thereby resulting in differences in the driving current received by the light-emitting element 10, affecting the brightness uniformity of the display panel 100. The channel width-to-length ratio of the first transistor T1 can also affect the degree of its opening or closing, and when receiving the same control voltage, the larger the channel width-to-length ratio of the first transistor T1, the better the degree of its opening or closing. By setting the channel width-to-length ratios of different first transistors T1 differently, it is possible to make the first transistors T1 receiving different control voltages open or close to the same degree.

[0055] In the embodiment of the present application, along the extension direction of the first scan line S1, the control voltage received by the first transistor T1 in the second pixel circuit 20B which is farther from the first end S11 of the first scan line S1 is smaller than the control voltage received by the first transistor T1 in the first pixel circuit 20A which is closer to the first end S11 of the first scan line S1. By setting the channel width-to-length ratio of the first transistor T1 in the second pixel circuit 20B to be greater than the channel width-to-length ratio of the first transistor T1 in the first pixel circuit 20A, it is possible to make the opening degree of the first transistor T1 in the second pixel circuit 20B the same as the opening degree of the first transistor T1 in the first pixel circuit 20A, which is beneficial to reduce the resistance difference between the first transistor T1 in the second pixel circuit 20B and the first transistor T1 in the first pixel circuit 20A, thereby helping to reduce the brightness difference of the light-emitting element 10 driven respectively by the second pixel circuit 20B and the first pixel circuit 20A, and further helping to improve the brightness uniformity of the display panel 100 and improve the display effect.

[0056] In one embodiment of the present application, please continue to refer to Figure 2 , the first electrode of the first transistor T1 is electrically connected to the power supply voltage signal line DL1, and the power supply voltage signal line DL1 transmits the first power supply voltage VDD; the second electrode of the first transistor T1 is electrically connected to the first electrode of the driving transistor Td, and the first transistor T1 is used to transmit the first power supply voltage VDD to the first electrode of the driving transistor Td. Or Figure 3 As shown, the first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor Td, the second electrode of the first transistor T1 is electrically connected to the input terminal 11 of the light emitting element 10, and the first transistor T1 is used to transmit the driving current generated by the driving transistor Td to the input terminal 11 of the light emitting element 10. It is a necessary condition for the first electrode of the driving transistor Td to receive the first power supply voltage VDD to generate the driving current.

[0057] Among them, optionally, the first electrode of the first transistor T1 can be its source electrode, and the second electrode can be its drain electrode; the first electrode of the driving transistor Td can be its source electrode, and the second electrode can be its drain electrode. In other embodiments, the first electrode of the first transistor T1 can be its drain electrode, and the second electrode can be its source electrode; the first electrode of the driving transistor Td can be its drain electrode, and the second electrode can be its source electrode.

[0058] In the embodiment of the present application, the pixel circuit 20 may include only one first transistor T1, and the first transistor T1 may be connected in series between the power supply voltage signal line DL1 and the first electrode of the driving transistor Td, or connected in series between the second electrode of the driving transistor Td and the input terminal 11 of the light-emitting element 10. The position setting of the first transistor T1 ensures that the driving current received by the light-emitting element 10 will pass through the first transistor T1, and the resistance value of the first transistor T1 affects the magnitude of the driving current, thereby ensuring that the channel width-to-length ratio of the first transistor T1 in different pixel circuits 20 is set differently to achieve the brightness of different light-emitting elements 10 tending to be consistent. Moreover, the position setting of the first transistor T1 in the embodiment of the present application can make the resistance value of the first transistor T1 have a greater influence on the driving current, which is conducive to improving the operability of achieving uniform brightness of different light-emitting elements 10.

[0059] Please continue to refer to Figure 4 In one embodiment of the present application, the pixel circuit 20 may include two first transistors T1, a first electrode of one first transistor T1 is electrically connected to the power supply voltage signal line DL1, and a second electrode is electrically connected to the first electrode of the driving transistor Td, and the first transistor T1 is used to transmit the first power supply voltage VDD transmitted by the power supply voltage signal line DL1 to the first electrode of the driving transistor Td. The first electrode of the other first transistor T1 is electrically connected to the second electrode of the driving transistor Td, and the second electrode is electrically connected to the input terminal 11 of the light-emitting element 10, and the first transistor T1 is used to transmit the driving current generated by the driving transistor Td to the input terminal 11 of the light-emitting element 10.

[0060] It should be noted that the two first transistors T1 in the same pixel circuit 20 both receive signals transmitted by the same first scan line S1. Along the extension direction of the first scan line S1, the difference in distance between the two first transistors T1 and the first end S11 of the first scan line S1 can be ignored, and the channel width-to-length ratios of the two first transistors T1 can be the same.

[0061] The embodiment of the present application is conducive to further improving the influence of the resistance value of the first transistor T1 on the driving current, thereby being conducive to further improving the operability of achieving uniform brightness of different light-emitting elements 10 .

[0062] Below Figure 4 The pixel circuit shown is taken as an example to illustrate the influence of the resistance value of the first transistor T1 on the driving current.

[0063] like Figure 4As shown, the output terminal 12 of the light emitting element 10 is electrically connected to the second power supply voltage terminal VEE, that is, the output terminal 12 of the light emitting element 10 receives the second power supply voltage VEE. Assuming that the resistance of the first transistor T1 is R1, the resistance of the driving transistor Td is Rd, and the resistance of the light emitting element 10 is Roled, then in the pixel circuit 20, the driving current Id=(VDD-VEE) / (R1+Rd+R1+Roled).

[0064] It can be seen from the formula of the driving current Id that the driving current Id is related to the resistance R1 of the first transistor T1 . The larger the resistance R1 of the first transistor T1 , the smaller the driving current Id.

[0065] The resistance R1 of the first transistor T1 is determined by the degree of opening of the first transistor T1, and the degree of opening of the first transistor T1 is jointly determined by the control voltage transmitted from the first scan line S1 to the first transistor T1 and the channel width-to-length ratio of the first transistor T1. In addition, the inventors found in the research process that the smaller the voltage transmitted from the first scan line S1 to the first transistor T1, the smaller the degree of opening of the first transistor T1; the larger the channel width-to-length ratio of the first transistor T1, the larger the degree of opening of the first transistor T1. Therefore, in the case where there is a voltage drop in the control voltage transmitted by the first scan line S1, the channel width-to-length ratio of the first transistor T1 in different pixel circuits 20 is set differently (for example, the channel width-to-length ratio of the first transistor T1 with a smaller received control voltage is set larger), so that the channel width-to-length ratio of the first transistor T1 matches the control voltage received by it, so that the degree of opening of the first transistor T1 in different pixel circuits 20 can be the same, thereby effectively improving the difference in the resistance R1 of the first transistor T1 in different pixel circuits 20, and further improving the uniformity of the brightness of the display panel 100.

[0066] Figure 8 A schematic diagram of a gradual change in the channel width-to-length ratio of a first transistor provided in an embodiment of the present application, Fig. 9 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application.

[0067] In one embodiment of the present application, Figure 8 and Fig. 9 As shown, a first scan line S1 is electrically connected to a first shift register circuit 30, that is, in the first scan line S1, only the first end S11 thereof is electrically connected to the output end 31 of the first shift register circuit 30, and the other ends of the first scan line S1 are no longer electrically connected to the first shift register circuit 30. Among the plurality of pixel circuits 20 electrically connected to the same first scan line S1, along the extension direction of the first scan line S1, that is, along the first direction X, the farther away from the first end S11 of the first scan line S1, the greater the channel width-to-length ratio of the first transistor T1 in the pixel circuit 20.

[0068] For example, Figure 8 and Fig. 9 As shown, the plurality of pixel circuits 20 electrically connected to the same first scan line S1 also include a third pixel circuit 20C. Along the extension direction of the first scan line S1, that is, along the first direction X, the distances between the first pixel circuit 20A, the second pixel circuit 20B and the third pixel circuit 20C and the first end S11 of the first scan line S1 gradually increase, and the channel width-to-length ratios of the first transistors T1 in the first pixel circuit 20A, the second pixel circuit 20B and the third pixel circuit 20C gradually increase.

[0069] From the above analysis, it can be known that the channel of the first transistor T1 may be the portion where the active layer YC overlaps with the first scan line S1, the length of the channel of the first transistor T1 in the extension direction of the active layer YC may be the channel length L of the first transistor T1, and the width of the channel of the first transistor T1 in the extension direction of the first scan line S1 may be the channel width W of the first transistor T1. The extension direction of the active layer YC intersects with the extension direction of the first transistor T1. In some optional embodiments, the extension direction of the active layer YC is perpendicular to the extension direction of the first transistor T1.

[0070] Alternatively, if Figure 8 As shown, the channel length L1 of the first transistor T1 in the first pixel circuit 20A, the channel length L2 of the first transistor T1 in the second pixel circuit 20B, and the channel length L3 of the first transistor T1 in the third pixel circuit 20C are the same, the channel width W1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit 20B, and the channel width W2 of the first transistor T1 in the second pixel circuit 20B is smaller than the channel width W3 of the first transistor T1 in the third pixel circuit 20C. That is, L1=L2=L3, W1<W2<W3. Thus, the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B, and the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B is smaller than the channel width-to-length ratio W3 / L3 of the first transistor T1 in the third pixel circuit 20C. That is, W1 / L1<W2 / L2<W3 / L3.

[0071] Alternatively, if Fig. 9As shown, the channel width W1 of the first transistor T1 in the first pixel circuit 20A, the channel width W2 of the first transistor T1 in the second pixel circuit 20B, and the channel width W3 of the first transistor T1 in the third pixel circuit 20C are the same, the channel length L1 of the first transistor T1 in the first pixel circuit 20A is greater than the channel length L2 of the first transistor T1 in the second pixel circuit 20B, and the channel length L2 of the first transistor T1 in the second pixel circuit 20B is greater than the channel length L3 of the first transistor T1 in the third pixel circuit 20C. That is, W1=W2=W3, L1>L2>L3. Thus, the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit 20A is smaller than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B, and the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit 20B is smaller than the channel width-to-length ratio W3 / L3 of the first transistor T1 in the third pixel circuit 20C. That is, W1 / L1<W2 / L2<W3 / L3.

[0072] It should be noted that Figure 8 and Fig. 9 Only two modes of gradually changing the channel width-to-length ratio of the first transistor T1 are illustrated. In addition, the gradually changing channel width-to-length ratio of the first transistor T1 may also be achieved in other modes.

[0073] Since the signal transmitted by the first shift register circuit 30 will generate a voltage drop on the first scan line S1, the control voltage received by the first transistor T1 in the pixel circuit 20 that is farther away from the first end S11 of the first scan line S1 is smaller. In the embodiment of the present application, the channel width-to-length ratio of the first transistor T1 that receives the smaller control voltage is set to be larger, so that it is possible to have the same opening degree of the first transistor T1 in the pixel circuit 20 at different distances from the first end S11 of the first scan line S1, which is beneficial to reducing the difference in resistance value of the first transistor T1 in different pixel circuits 20, thereby helping to reduce the brightness difference of the light-emitting elements 10 respectively driven by different pixel circuits 20, and further helping to reduce the brightness difference at different positions of the display panel 100, improve the brightness uniformity of the display panel 100, and improve the display effect.

[0074] Fig.10 A schematic diagram of another display panel provided in an embodiment of the present application, Fig.11 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application, Fig.12 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application.

[0075] In one embodiment of the present application, Fig.10 and Fig.11 or Fig.10 and Fig.12 As shown, the first end S11 and the second end S12 of the first scan line S1 are electrically connected to the output ends 31 of different first shift register circuits 30, respectively. That is, the same first scan line S1 receives signals transmitted by two first shift registers 30, and the display panel 100 drives the multiple pixel circuits 20 electrically connected to the same first scan line S1 to work in a bilateral driving manner.

[0076] In the plurality of pixel circuits 20 electrically connected to the same first scan line S11, the channel width-to-length ratio of the first transistor T1 in the pixel circuit 20 gradually increases along the direction extending from both ends of the first scan line S1 to the middle. In other words, along the direction extending from the first end S11 of the first scan line S1 to the middle of the first scan line S1 and along the direction extending from the second end S12 of the first scan line S1 to the middle of the first scan line S1, the channel width-to-length ratio of the first transistor T1 in the plurality of pixel circuits 20 gradually increases.

[0077] For example, Fig.11 and Fig.12 As shown, the plurality of pixel circuits 20 electrically connected to the same first scan line S1 include a fourth pixel circuit 20E, a fifth pixel circuit 20F, a sixth pixel circuit 20M and a seventh pixel circuit 20N, the fourth pixel circuit 20E and the fifth pixel circuit 20F are located between the first end S11 of the first scan line S1 and the middle position S13 of the first scan line S1, and the distance between the first end S11 of the first scan line S1 and the fifth pixel circuit 20F is greater than the distance between the fifth pixel circuit 20F and the fourth pixel circuit 20E. The sixth pixel circuit 20M and the seventh pixel circuit 20N are located between the second end S12 of the first scan line S1 and the middle position S13 of the first scan line S1, and the distance between the second end S12 of the first scan line S1 and the seventh pixel circuit 20N is greater than the distance between the seventh pixel circuit 20N and the sixth pixel circuit 20M.

[0078] Among them, the channel width-to-length ratio of the first transistor T1 in the fifth pixel circuit 20F is greater than the channel width-to-length ratio of the first transistor T1 in the fourth pixel circuit 20E, and the channel width-to-length ratio of the first transistor T1 in the seventh pixel circuit 20N is greater than the channel width-to-length ratio of the first transistor T1 in the sixth pixel circuit 20M.

[0079] From the above analysis, it can be known that the channel of the first transistor T1 may be the portion where the active layer YC overlaps with the first scan line S1, the length of the channel of the first transistor T1 in the extension direction of the active layer YC may be the channel length L of the first transistor T1, and the width of the channel of the first transistor T1 in the extension direction of the first scan line S1 may be the channel width W of the first transistor T1. The extension direction of the active layer YC intersects with the extension direction of the first transistor T1. In some optional embodiments, the extension direction of the active layer YC is perpendicular to the extension direction of the first transistor T1.

[0080] Alternatively, if Fig.11 As shown, the channel length L4 of the first transistor T1 in the fourth pixel circuit 20E is the same as the channel length L5 of the first transistor T1 in the fifth pixel circuit 20F, and the channel width W4 of the first transistor T1 in the fourth pixel circuit 20E is smaller than the channel width W5 of the first transistor T1 in the fifth pixel circuit 20F; the channel length L6 of the first transistor T1 in the sixth pixel circuit 20M is the same as the channel length L7 of the first transistor T1 in the seventh pixel circuit 20N, and the channel width W6 of the first transistor T1 in the sixth pixel circuit 20M is smaller than the channel width W7 of the first transistor T1 in the seventh pixel circuit 20N. That is, L4=L5, W4<W5; L6=L7, W6<W7. Thus, the channel width-to-length ratio W4 / L4 of the first transistor T1 in the fourth pixel circuit 20E is smaller than the channel width-to-length ratio W5 / L5 of the first transistor T1 in the fifth pixel circuit 20F, and the channel width-to-length ratio W6 / L6 of the first transistor T1 in the sixth pixel circuit 20M is smaller than the channel width-to-length ratio W7 / L7 of the first transistor T1 in the seventh pixel circuit 20N. That is, W4 / L4<W5 / L5, W6 / L6<W7 / L7.

[0081] Alternatively, if Fig.12As shown, the channel width W4 of the first transistor T1 in the fourth pixel circuit 20E is the same as the channel width W5 of the first transistor T1 in the fifth pixel circuit 20F, and the channel length L4 of the first transistor T1 in the fourth pixel circuit 20E is greater than the channel length L5 of the first transistor T1 in the fifth pixel circuit 20F; the channel width W6 of the first transistor T1 in the sixth pixel circuit 20M is the same as the channel width W7 of the first transistor T1 in the seventh pixel circuit 20N, and the channel length L6 of the first transistor T1 in the sixth pixel circuit 20M is greater than the channel length L7 of the first transistor T1 in the seventh pixel circuit 20N. That is, W4=W5, L4>L5; W6=W7, L6>L7. Thus, the channel width-to-length ratio W4 / L4 of the first transistor T1 in the fourth pixel circuit 20E is smaller than the channel width-to-length ratio W5 / L5 of the first transistor T1 in the fifth pixel circuit 20F, and the channel width-to-length ratio W6 / L6 of the first transistor T1 in the sixth pixel circuit 20M is smaller than the channel width-to-length ratio W7 / L7 of the first transistor T1 in the seventh pixel circuit 20N. That is, W4 / L4<W5 / L5, W6 / L6<W7 / L7.

[0082] It should be noted that Fig.11 and Fig.12 Only two modes of gradually changing the channel width-to-length ratio of the first transistor T1 are illustrated. In addition, the gradually changing channel width-to-length ratio of the first transistor T1 may also be achieved in other modes.

[0083] In the embodiment of the present application, the signal transmitted by the first shift register circuit 30 will generate a voltage drop on the first scan line S1, and the first transistor T1 in the pixel circuit 20 that is farther from the first end S11 of the first scan line S1 between the first end S11 and the middle position S13 thereof will receive a smaller control voltage; and the first transistor T1 in the pixel circuit 20 that is farther from the second end S12 of the first scan line S1 between the second end S12 of the first scan line S1 between the second end S13 thereof will receive a smaller control voltage. In the embodiment of the present application, the channel width-to-length ratio of the first transistor T1 that receives the smaller control voltage is set to be larger, so that the opening degree of the first transistor T1 in the plurality of pixel circuits 20 electrically connected to the first scan line S1 becomes the same, which is beneficial to reduce the difference in resistance value of the first transistor T1 in different pixel circuits 20, thereby reducing the difference in brightness of the light-emitting elements 10 respectively driven by different pixel circuits 20, and further reducing the difference in brightness at different positions of the display panel 100, thereby improving the display effect.

[0084] Fig.13 for Figure 4 A schematic diagram of a pixel circuit shown.

[0085] Please continue to refer to Figure 2-Figure 4In one embodiment of the present application, the pixel circuit 20 further includes a data voltage writing module 23, a threshold voltage capture module 24, a first reset module 25, a second reset module 26 and a first capacitor C1, the input terminal 231 of the data voltage writing module 23 is electrically connected to the data voltage signal line DL2, the output terminal 232 is electrically connected to the first electrode of the driving transistor Td, and the control terminal 233 is electrically connected to the second scan line S2, and the data voltage writing module 23 is used to transmit the data voltage Vdata transmitted by the data voltage signal line DL2 to the first electrode of the driving transistor Td; the input terminal 241 of the threshold voltage capture module 24 is electrically connected to the second electrode of the driving transistor Td, the output terminal 242 is electrically connected to the third electrode of the driving transistor Td, and the control terminal 243 is electrically connected to the second scan line S2; the input terminal 231 of the first reset module 25 is electrically connected to the data voltage signal line DL2, the output terminal 232 is electrically connected to the first electrode of the driving transistor Td, and the control terminal 233 is electrically connected to the second scan line S2; 251 is electrically connected to the first reset signal line SL1, the output terminal 252 is electrically connected to the third electrode of the driving transistor Td, and the control terminal 253 is electrically connected to the third scan line S3. The first reset module 25 is used to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the third electrode of the driving transistor Td; the input terminal 261 of the second reset module 26 is electrically connected to the second reset signal line SL2, the output terminal 262 is electrically connected to the input terminal 11 of the light-emitting element 10, and the control terminal 263 is electrically connected to the second scan line S2. The second reset module 26 is used to transmit the second reset voltage Vref2 transmitted by the second reset signal line SL2 to the input terminal 11 of the light-emitting element 10; one plate of the first capacitor C1 is electrically connected to the power supply voltage signal line DL1, and the other plate is electrically connected to the third electrode of the driving transistor Td.

[0086] The first electrode of the driving transistor Td may be its source electrode, the second electrode may be its drain electrode, and the third electrode may be its gate electrode.

[0087] Alternatively, if Fig.13As shown, the data voltage writing module 23 includes a second transistor T2, the source of the second transistor T2 is electrically connected to the input terminal 231 of the data voltage writing module 23, the drain is electrically connected to the output terminal 232 of the data voltage writing module 23, and the gate is electrically connected to the control terminal 233 of the data voltage writing module 23; the threshold voltage capture module 24 includes a third transistor T3, the source of the third transistor T3 is electrically connected to the input terminal 241 of the threshold voltage capture module 24, the drain is electrically connected to the output terminal 242 of the threshold voltage capture module 24, and the gate is electrically connected to the control terminal 233 of the threshold voltage capture module 24. The control terminal 243 is electrically connected; the first reset module 25 includes a fourth transistor T4, the source of the fourth transistor T4 is electrically connected to the output terminal 251 of the first reset module 25, the drain is electrically connected to the output terminal 252 of the first reset module 25, and the gate is electrically connected to the control terminal 253 of the first reset module 25; the second reset module 26 includes a fifth transistor T5, the source of the fifth transistor T5 is electrically connected to the input terminal 261 of the second reset module 26, the drain is electrically connected to the output terminal 262 of the second reset module 26, and the gate is electrically connected to the control terminal 263 of the second reset module 26.

[0088] It should be noted that the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , and the fifth transistor T5 may all be P-type transistors. Of course, any one of them may also be an N-type transistor.

[0089] Fig.14 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0090] Fig.14 The pixel circuit 20 shown is Fig.13 The pixel circuit 20 shown is different only in that the third transistor T3 and the fourth transistor T4 are N-type transistors including an oxide active layer, and the gate of the third transistor T3 is electrically connected to the fourth scan line S4.

[0091] Fig.15 A schematic diagram of a shift register circuit driving a pixel circuit related to the present application.

[0092] In one embodiment of the present application, Fig.15 As shown, to drive Fig.13Taking the pixel circuit 20 shown as an example, the display panel 100 may further include a second shift register circuit 40 and a third shift register circuit 50, wherein the output terminal 41 of the second shift register circuit 40 is electrically connected to the first terminal S21 of the second scan line S2, and the output terminal 51 of the third shift register circuit 50 is electrically connected to the first terminal S31 of the third scan line S3. The signal transmitted by the second shift register circuit 40 is used to control the switching state of the second transistor T2, the third transistor T3 and the fifth transistor T5, and the signal transmitted by the third shift register circuit 50 is used to control the switching state of the fourth transistor T4. The first shift register circuit 30, the second shift register circuit 40 and the third shift register circuit 50 jointly drive the pixel circuit 20 to work.

[0093] Fig.16 This is a schematic diagram of a first shift register circuit driving a pixel circuit group related to the present application.

[0094] like Fig.16 As shown, in one embodiment of the present application, a plurality of pixel circuits 20 electrically connected to the same first scan line S1 form a plurality of pixel circuit groups P, the pixel circuit group P includes at least two adjacent pixel circuits 20, and the channel width-to-length ratio of the first transistor T1 included in each pixel circuit 20 of the same pixel circuit group P is the same.

[0095] It should be noted that Fig.16 The example only illustrates a situation where one pixel circuit group P includes two pixel circuits 20 , and the number of pixel circuits 20 included in different pixel circuit groups P may be the same or different.

[0096] Among them, the multiple pixel circuit groups P include a first pixel circuit group P1 and a second pixel circuit group P2, and along the extension direction of the first scan line, that is, along the first direction X, the distance between the first end S11 of the first scan line S1 and the first pixel circuit group P1 is smaller than the distance between it and the second pixel circuit group P2, and the channel width-to-length ratio of the first transistor T1 in the first pixel circuit group P1 is smaller than the channel width-to-length ratio of the first transistor T1 in the second pixel circuit group P2.

[0097] That is, along the extension direction of the first scan line S1, the distance between the first pixel circuit group P1 and the output end 31 of the first shift register circuit 30 is smaller than the distance between the second pixel circuit group P2 and the output end 31 of the first shift register circuit 30. At this time, the channel width-to-length ratio of the first transistor T1 in the first pixel circuit group P1 is smaller than the channel width-to-length ratio of the first transistor T1 in the second pixel circuit group P2.

[0098] From the above analysis, it can be known that in the embodiment of the present application, along the extension direction of the first scan line S1, the control voltage received by the first transistor T1 in the second pixel circuit group P2 farther from the first end S11 of the first scan line S1 is smaller than the control voltage received by the first transistor T1 in the first pixel circuit group P1 closer to the first end S11 of the first scan line S1. By setting the channel width-to-length ratio of the first transistor T1 in the second pixel circuit group P2 to be greater than the channel width-to-length ratio of the first transistor T1 in the first pixel circuit group P1, it is possible to make the opening degree of the first transistor T1 in the second pixel circuit group P2 the same as the opening degree of the first transistor T1 in the first pixel circuit group P1, which is beneficial to reduce the resistance difference between the first transistor T1 in the second pixel circuit group P2 and the first transistor T1 in the first pixel circuit group P1, thereby helping to reduce the brightness difference of the light-emitting element 10 driven by the pixel circuit 20 in the second pixel circuit group P2 and the pixel circuit 20 in the first pixel circuit group P1, and further helping to improve the brightness uniformity of the display panel 100 and improve the display effect.

[0099] Moreover, considering that the control voltages received by the first transistors T1 in adjacent pixel circuits 20 are slightly different, the degree of their on or off is not much different, and the difference in the brightness of the light-emitting device 10 can be ignored. In the embodiment of the present application, the channel width-to-length ratios of the first transistors T1 included in each pixel circuit 20 in the same pixel circuit group P are set to be the same, which is conducive to simplifying the manufacturing process of the first transistor T1 and reducing the difficulty of manufacturing the display panel 100.

[0100] Fig.17 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application.

[0101] In one embodiment of the present application, Fig.16 As shown, a first scan line S1 is electrically connected to a first shift register circuit 30, that is, in the first scan line S1, only the first end S11 thereof is electrically connected to the output end 31 of the first shift register circuit 30, and the other ends of the first scan line S1 are no longer electrically connected to the first shift register circuit 30. Among the plurality of pixel circuit groups P electrically connected to the same first scan line S1, along the extension direction of the first scan line S1, that is, along the first direction X, the farther the first transistor T1 in the pixel circuit group P is from the first end S11 of the first scan line S1, the larger the channel width-to-length ratio is.

[0102] For example, Fig.16As shown, the multiple pixel circuit groups P electrically connected to the same first scan line S1 also include a third pixel circuit group P3. Along the extension direction of the first scan line S1, the distances between the first pixel circuit group P1, the second pixel circuit group P2 and the third pixel circuit group P3 and the first end S11 of the first scan line S1 gradually increase, and the channel width-to-length ratio of the first transistor T1 in the first pixel circuit group P1, the second pixel circuit group P2 and the third pixel circuit group P3 gradually increases.

[0103] From the above analysis, it can be known that the channel of the first transistor T1 may be the portion where the active layer YC overlaps with the first scan line S1, the length of the channel of the first transistor T1 in the extension direction of the active layer YC may be the channel length L of the first transistor T1, and the width of the channel of the first transistor T1 in the extension direction of the first scan line S1 may be the channel width W of the first transistor T1. The extension direction of the active layer YC intersects with the extension direction of the first transistor T1. In some optional embodiments, the extension direction of the active layer YC is perpendicular to the extension direction of the first transistor T1.

[0104] Alternatively, if Fig.16 As shown, the channel length L1 of the first transistor T1 in the first pixel circuit group P1, the channel length L2 of the first transistor T1 in the second pixel circuit group P2, and the channel length L3 of the first transistor T1 in the third pixel circuit group P3 are the same, the channel width W1 of the first transistor T1 in the first pixel circuit group P1 is smaller than the channel width W2 of the first transistor T1 in the second pixel circuit group P2, and the channel width W2 of the first transistor T1 in the second pixel circuit group P2 is smaller than the channel width W3 of the first transistor T1 in the third pixel circuit group P3. That is, L1=L2=L3, W1<W2<W3. Thus, the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit group P1 is smaller than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit group P2, and the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit group P2 is smaller than the channel width-to-length ratio W3 / L3 of the first transistor T1 in the third pixel circuit group P3. That is, W1 / L1<W2 / L2<W3 / L3.

[0105] In addition, you can Fig.17As shown, the channel width W1 of the first transistor T1 in the first pixel circuit group P1, the channel width W2 of the first transistor T1 in the second pixel circuit group P2, and the channel width W3 of the first transistor T1 in the third pixel circuit group P3 are the same, the channel length L1 of the first transistor T1 in the first pixel circuit group P1 is greater than the channel length L2 of the first transistor T1 in the second pixel circuit group P2, and the channel length L2 of the first transistor T1 in the second pixel circuit group P2 is greater than the channel length L3 of the first transistor T1 in the third pixel circuit group P3. That is, W1=W2=W3, L1>L2>L3. Thus, the channel width-to-length ratio W1 / L1 of the first transistor T1 in the first pixel circuit group P1 is smaller than the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit group P2, and the channel width-to-length ratio W2 / L2 of the first transistor T1 in the second pixel circuit group P2 is smaller than the channel width-to-length ratio W3 / L3 of the first transistor T1 in the third pixel circuit group P3. That is, W1 / L1<W2 / L2<W3 / L3.

[0106] From the above analysis, it can be seen that in the embodiment of the present application, the channel width-to-length ratio of the first transistor T1 in the pixel circuit group P that receives the smaller control voltage is set to be larger, so that it is possible to have the same degree of opening of the first transistor T1 in the pixel circuit groups P at different distances from the first end S11 of the first scan line S1, which is beneficial to reducing the resistance value difference of the first transistor T1 in different pixel circuit groups P, thereby helping to reduce the brightness difference of the light-emitting elements 10 respectively driven by the pixel circuits 20 in different pixel circuit groups P, and further helping to reduce the brightness difference at different positions of the display panel 100, improve the brightness uniformity of the display panel 100, and improve the display effect.

[0107] Fig.18 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application, Fig.19 A schematic diagram of a gradual change in the channel width-to-length ratio of another first transistor provided in an embodiment of the present application.

[0108] In one embodiment of the present application, Fig.18 and Fig.19 As shown, the first end S11 and the second end S12 of the first scan line S1 are electrically connected to the output ends 31 of different first shift register circuits 30, respectively, that is, the same first scan line S1 receives signals transmitted by two first shift registers 30, and the display panel 100 adopts a bilateral driving method to drive multiple pixel circuit groups P electrically connected to the same first scan line S1 to work.

[0109] In the plurality of pixel circuit groups P electrically connected to the same first scan line S1, the channel width-to-length ratio of the first transistor T1 in the pixel circuit group P gradually increases along the direction extending from both ends of the first scan line S1 to the middle. In other words, along the direction extending from the first end S11 of the first scan line S1 to the middle of the first scan line S1 and along the direction extending from the second end S12 of the first scan line S1 to the middle of the first scan line S1, the channel width-to-length ratio of the first transistor T1 in the plurality of pixel circuit groups P gradually increases.

[0110] For example, Fig.18 and Fig.19 As shown, the plurality of pixel circuit groups P electrically connected to the same first scan line S1 include a fourth pixel circuit group P4, a fifth pixel circuit group P5, a sixth pixel circuit group P6 and a seventh pixel circuit group P7, the fourth pixel circuit group P4 and the fifth pixel circuit group P5 are located between the first end S11 of the first scan line S1 and the middle position S13 of the first scan line S1, and the distance between the first end S11 of the first scan line S1 and the fifth pixel circuit group P5 is greater than the distance between the fifth pixel circuit group P5 and the fourth pixel circuit group P4. The sixth pixel circuit group P6 and the seventh pixel circuit group P7 are located between the second end S12 of the first scan line S1 and the middle position S13 of the first scan line S1, and the distance between the second end S12 of the first scan line S1 and the seventh pixel circuit group P7 is greater than the distance between the seventh pixel circuit group P7 and the sixth pixel circuit group P6.

[0111] Among them, the channel width-to-length ratio of the first transistor T1 in the fifth pixel circuit group P5 is greater than the channel width-to-length ratio of the first transistor T1 in the fourth pixel circuit group P4, and the channel width-to-length ratio of the first transistor T1 in the seventh pixel circuit group P7 is greater than the channel width-to-length ratio of the first transistor T1 in the sixth pixel circuit group P6.

[0112] From the above analysis, it can be known that the channel of the first transistor T1 may be the portion where the active layer YC overlaps with the first scan line S1, the length of the channel of the first transistor T1 in the extension direction of the active layer YC may be the channel length L of the first transistor T1, and the width of the channel of the first transistor T1 in the extension direction of the first scan line S1 may be the channel width W of the first transistor T1. The extension direction of the active layer YC intersects with the extension direction of the first transistor T1. In some optional embodiments, the extension direction of the active layer YC is perpendicular to the extension direction of the first transistor T1.

[0113] Alternatively, if Fig.18As shown, the channel length L4 of the first transistor T1 in the fourth pixel circuit group P4 is the same as the channel length L5 of the first transistor T1 in the fifth pixel circuit group P5, and the channel width W4 of the first transistor T1 in the fourth pixel circuit group P4 is smaller than the channel width W5 of the first transistor T1 in the fifth pixel circuit group P5; the channel length L6 of the first transistor T1 in the sixth pixel circuit group P6 is the same as the channel length L7 of the first transistor T1 in the seventh pixel circuit group P7, and the channel width W6 of the first transistor T1 in the sixth pixel circuit group P6 is smaller than the channel width W7 of the first transistor T1 in the seventh pixel circuit group P7. That is, L4=L5, W4<W5; L6=L7, W6<W7. Thus, the channel width-to-length ratio W4 / L4 of the first transistor T1 in the fourth pixel circuit group P4 is smaller than the channel width-to-length ratio W5 / L5 of the first transistor T1 in the fifth pixel circuit group P5, and the channel width-to-length ratio W6 / L6 of the first transistor T1 in the sixth pixel circuit group P6 is smaller than the channel width-to-length ratio W7 / L7 of the first transistor T1 in the seventh pixel circuit group P7. That is, W4 / L4<W5 / L5, W6 / L6<W7 / L7.

[0114] Alternatively, if Fig.19 As shown, the channel width W4 of the first transistor T1 in the fourth pixel circuit group P4 is the same as the channel width W5 of the first transistor T1 in the fifth pixel circuit group P5, and the channel length L4 of the first transistor T1 in the fourth pixel circuit group P4 is greater than the channel length L5 of the first transistor T1 in the fifth pixel circuit group P5; the channel width W6 of the first transistor T1 in the sixth pixel circuit group P6 is the same as the channel width W7 of the first transistor T1 in the seventh pixel circuit group P7, and the channel length L6 of the first transistor T1 in the sixth pixel circuit group P6 is greater than the channel length L7 of the first transistor T1 in the seventh pixel circuit group P7. That is, W4=W5, L4>L5; W6=W7, L6>L7. Thus, the channel width-to-length ratio W4 / L4 of the first transistor T1 in the fourth pixel circuit group P4 is smaller than the channel width-to-length ratio W5 / L5 of the first transistor T1 in the fifth pixel circuit group P5, and the channel width-to-length ratio W6 / L6 of the first transistor T1 in the sixth pixel circuit group P6 is smaller than the channel width-to-length ratio W7 / L7 of the first transistor T1 in the seventh pixel circuit group P7. That is, W4 / L4<W5 / L5, W6 / L6<W7 / L7.

[0115] It should be noted that Fig.18 and Fig.19 Only two modes of gradually changing the channel width-to-length ratio of the first transistor T1 are illustrated. In addition, the gradually changing channel width-to-length ratio of the first transistor T1 may also be achieved in other modes.

[0116] In the embodiment of the present application, the signal transmitted by the first shift register circuit 30 will generate a voltage drop on the first scan line S1, and the first transistor T1 in the pixel circuit group P that is farther from the first end S11 of the first scan line S1 between the first end S11 and the middle position S13 thereof will receive a smaller control voltage; and the first transistor T1 in the pixel circuit group P that is farther from the second end S12 of the first scan line S1 between the second end S12 of the first scan line S1 between the second end S13 thereof will receive a smaller control voltage. In the embodiment of the present application, the channel width-to-length ratio of the first transistor T1 in the pixel circuit group P that receives the smaller control voltage is set to be larger, so that the first transistors T1 in the plurality of pixel circuit groups P electrically connected to the first scan line S1 can be opened to the same degree, which is beneficial to reduce the difference in resistance of the first transistors T1 in different pixel circuit groups P, thereby facilitating the reduction of the brightness difference of the light-emitting elements 10 respectively driven by the pixel circuits 20 in different pixel circuit groups P, and further facilitating the reduction of the brightness difference at different positions of the display panel 100, thereby improving the display effect.

[0117] Fig. 20 A schematic diagram of a display device provided in an embodiment of the present application.

[0118] The present application embodiment provides a display device 200, such as Fig. 20 As shown, the display device 200 includes the display panel 100 provided in the above embodiment. The display device 200 may be a mobile phone. In addition, the display device 200 provided in the embodiment of the present application may also be an electronic device such as a computer or a television.

[0119] In the display device 200, along the extension direction of the first scan line S1, the control voltage received by the first transistor T1 in the second pixel circuit 20B farther from the first end S11 of the first scan line S1 is smaller than the control voltage received by the first transistor T1 in the first pixel circuit 20A closer to the first end S11 of the first scan line S1. By setting the channel width-to-length ratio of the first transistor T1 in the second pixel circuit 20B to be greater than the channel width-to-length ratio of the first transistor T1 in the first pixel circuit 20A, it is possible to make the opening degree of the first transistor T1 in the second pixel circuit 20B the same as the opening degree of the first transistor T1 in the first pixel circuit 20A, which is beneficial to reduce the resistance difference between the first transistor T1 in the second pixel circuit 20B and the first transistor T1 in the first pixel circuit 20A, thereby helping to reduce the brightness difference of the light-emitting element 10 driven respectively by the second pixel circuit 20B and the first pixel circuit 20A, and further helping to improve the brightness uniformity of the display panel 100 and improve the display effect.

[0120] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: Light emitting element; A pixel circuit, the pixel circuit comprising: A driving transistor, the driving transistor is used to provide a driving current for the light emitting element; a first transistor, the driving current flowing through the first transistor; A first shift register circuit, wherein the output end of the first shift register circuit is electrically connected to the first end of a first scan line, and the first scan line is electrically connected to the control end of the first transistor in a plurality of the pixel circuits; wherein the plurality of pixel circuits electrically connected to the same first scan line include a first pixel circuit and a second pixel circuit; along an extension direction of the first scan line, a distance between the first end of the first scan line and the first pixel circuit is smaller than a distance between the first end of the first scan line and the second pixel circuit, and a channel width-to-length ratio of the first transistor in the first pixel circuit is smaller than a channel width-to-length ratio of the first transistor in the second pixel circuit.

2. The display panel according to claim 1, characterized in that: A channel length of the first transistor in the first pixel circuit is the same as a channel length of the first transistor in the second pixel circuit, and a channel width of the first transistor in the first pixel circuit is smaller than a channel width of the first transistor in the second pixel circuit.

3. The display panel according to claim 1, characterized in that: A channel width of the first transistor in the first pixel circuit is the same as a channel width of the first transistor in the second pixel circuit, and a channel length of the first transistor in the first pixel circuit is greater than a channel length of the first transistor in the second pixel circuit.

4. The display panel according to claim 1, characterized in that: A channel width of the first transistor in the first pixel circuit is different from a channel width of the first transistor in the second pixel circuit, and a channel length of the first transistor in the first pixel circuit is different from a channel length of the first transistor in the second pixel circuit.

5. The display panel according to claim 1, characterized in that: The first electrode of the first transistor is electrically connected to the power supply voltage signal line, and the second electrode of the first transistor is electrically connected to the first electrode of the driving transistor; or the first electrode of the first transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the input end of the light-emitting element.

6. The display panel according to claim 1, characterized in that: The pixel circuit includes two first transistors, one of which has a first electrode electrically connected to a power supply voltage signal line and a second electrode electrically connected to a first electrode of the driving transistor, and the other of which has a first electrode electrically connected to a second electrode of the driving transistor and a second electrode electrically connected to an input end of the light-emitting element.

7. The display panel according to claim 1, characterized in that: A first scan line is electrically connected to a first shift register circuit. Among the multiple pixel circuits electrically connected to the same first scan line, along the extension direction of the first scan line, the farther away from the first end of the first scan line, the larger the channel width-to-length ratio of the first transistor in the pixel circuit.

8. The display panel according to claim 1, characterized in that: The first end and the second end of the first scan line are electrically connected to different output ends of the first shift register circuits, respectively. In the plurality of pixel circuits electrically connected to the same first scan line, the channel width-to-length ratio of the first transistor in the pixel circuit gradually increases along a direction extending toward the middle from both ends of the first scan line.

9. The display panel according to claim 1, characterized in that: The plurality of pixel circuits electrically connected to the same first scan line form a plurality of pixel circuit groups, wherein the pixel circuit group includes at least two adjacent pixel circuits, and the channel width-to-length ratio of the first transistors included in each pixel circuit in the same pixel circuit group is the same; The multiple pixel circuit groups include a first pixel circuit group and a second pixel circuit group. Along the extension direction of the first scan line, the distance between the first end of the first scan line and the first pixel circuit group is smaller than the distance between the first end of the first scan line and the second pixel circuit group, and the channel width-to-length ratio of the first transistor in the first pixel circuit group is smaller than the channel width-to-length ratio of the first transistor in the second pixel circuit group.

10. The display panel according to claim 9, characterized in that: A first scan line is electrically connected to a first shift register circuit. Among the multiple pixel circuit groups electrically connected to the same first scan line, along the extension direction of the first scan line, the farther away from the first end of the first scan line, the larger the channel width-to-length ratio of the first transistor in the pixel circuit group.

11. The display panel according to claim 9, characterized in that: The first end and the second end of the first scan line are electrically connected to different output ends of the first shift register circuits, respectively. In the plurality of pixel circuit groups electrically connected to the same first scan line, the channel width-to-length ratio of the first transistor in the pixel circuit group gradually increases along a direction extending toward the middle from both ends of the first scan line.

12. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-11.

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