semiconductor memory devices

Abstract

One embodiment of the present invention provides a semiconductor memory device capable of performing satisfactory operations. The semiconductor memory device according to one embodiment of the present invention includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting the substrate surface and extending in a second direction intersecting the first direction; a first semiconductor pillar extending in the first direction and opposing the plurality of first conductive layers; a first bit line extending in a third direction intersecting the first and second directions and disposed at a position overlapping the first semiconductor pillar when viewed from the first direction; a first wiring including a portion overlapping the first bit line when viewed from the first direction; and a second wiring including a portion overlapping the first bit line when viewed from the first direction. When a period during which the voltage of the first wiring transitions from a high potential state to a low potential state is defined as a first period, and a period during which the voltage of the second wiring transitions from a low potential state to a high potential state is defined as a second period, at least a portion of the second period overlaps at least a portion of the first period.

Description

[0001] [Related Applications]

[0002] This application claims priority from Japanese Patent Application No. 2021-23360 (filing date: February 17, 2021) as a basic application, and the entire contents of the basic application are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor storage device is known, comprising: a semiconductor substrate; a plurality of conductive layers stacked in a direction intersecting the surface of the semiconductor substrate; a semiconductor pillar extending in a direction intersecting the surface of the semiconductor substrate and opposite to the plurality of conductive layers; and a gate insulating film arranged between the conductive layers and the semiconductor pillar. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device capable of performing satisfactory operations.

[0006] A semiconductor memory device according to one embodiment includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate and extending in a second direction intersecting the first direction; a first semiconductor pillar extending in the first direction and opposing the plurality of first conductive layers; a first bit line extending in a third direction intersecting the first and second directions and provided at a position overlapping the first semiconductor pillar when viewed from the first direction; a first wiring including a portion overlapping the first bit line when viewed from the first direction; and a second wiring including a portion overlapping the first bit line when viewed from the first direction. When a predetermined period during which a voltage of the first wiring transitions from a high potential state to a low potential state is defined as a first period, and a predetermined period during which a voltage of the second wiring transitions from a low potential state to a high potential state is defined as a second period, at least a portion of the second period overlaps with at least a portion of the first period. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a schematic block diagram showing the configuration of a memory die MD according to the embodiment.

[0008] Figure 2 1 is a schematic circuit diagram showing the configuration of a memory cell array MCA.

[0009] Figure 3 2 is a schematic circuit diagram showing the configuration of the sense amplifier module SAM, the cache memory CM, and the conversion circuit 80 .

[0010] Figure 4FIG. 1 is a schematic circuit diagram showing the configuration of a sense amplifier unit SAU of the sense amplifier module SAM.

[0011] Figure 5 is a schematic top view of the memory die MD.

[0012] Figure 6 It will Figure 5 The structure shown is a schematic cross-sectional view taken along lines AA' and BB' and viewed in the direction of arrows.

[0013] Figure 7 yes Figure 5 The transistor layer L shown in C TR Schematic enlarged diagram of .

[0014] Figure 8 yes Figure 5 Schematic enlarged view of the portion shown in D.

[0015] Figure 9 It will Figure 8 The structure shown is a schematic cross-sectional view taken along line EE' and viewed in the direction of the arrow.

[0016] Figure 10 yes Figure 9 Schematic enlarged view of the portion shown in F.

[0017] Figure 11 yes Figure 5 G is a schematic enlarged view of the portion shown.

[0018] Figure 12 It will Figure 11 The structure shown is a schematic cross-sectional view taken along line HH' and viewed in the direction of the arrow.

[0019] Figure 13 It will Figure 11 The structure shown is a schematic cross-sectional view taken along line II' and viewed in the direction of the arrow.

[0020] Figure 14 is Figure 7 The control signal transmission wiring m1 is superimposed on the diagram shown L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVR To represent the schematic diagram.

[0021] Figure 15 yes Figure 14 Schematic enlarged view of the portion shown in J.

[0022] Figure 16It will Figure 15 The portion shown in K is a schematic diagram showing the bit line BL together.

[0023] Figure 17 It is a schematic cross-sectional view for explaining the read operation.

[0024] Figure 18 It is a schematic waveform diagram used to explain the read operation.

[0025] Figure 19 It is a schematic waveform diagram used to illustrate the data transmission operation.

[0026] Figure 20 (a) to (g) are schematic waveform diagrams for explaining compensation of asynchronous noise during read operation.

[0027] Figure 21 It is a schematic cross-sectional view for explaining a writing operation.

[0028] Figure 22 It is a schematic waveform diagram used to explain the writing operation.

[0029] Figure 23 (a) to (f) are schematic waveform diagrams for explaining compensation of asynchronous noise during a write operation. DETAILED DESCRIPTION

[0030] Next, semiconductor memory devices according to various embodiments will be described in detail with reference to the accompanying drawings. The following embodiments are merely examples and are not intended to limit the present invention. The following drawings are schematic and, for ease of explanation, may omit portions of the components. Common components across multiple embodiments are denoted by the same reference numerals, and their description may be omitted.

[0031] In this specification, the term "semiconductor memory device" may refer to a bare memory chip, or a memory system including a controller bare chip, such as a memory chip, memory card, or SSD (Solid State Drive). Furthermore, it may also refer to a configuration including a host computer, such as a smartphone, tablet computer, or personal computer.

[0032] In this specification, the term "control circuit" sometimes refers to a peripheral circuit such as a sequencer provided on a memory die, sometimes refers to a controller die or controller chip connected to a memory die, and sometimes refers to a configuration including both.

[0033] In this specification, when it is stated that a first configuration and a second configuration are "electrically connected," the first configuration and the second configuration may be directly connected or connected via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even when the second transistor is in the OFF state.

[0034] In this specification, when it is stated that the first configuration is “connected between” the second configuration and the third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0035] In addition, in this specification, when it is described that a circuit or the like "conducts" two wirings, for example, it may mean that the circuit or the like includes a transistor or the like, and the transistor or the like is provided in a current path between the two wirings and is in an ON state.

[0036] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0037] In this specification, a direction along a predetermined surface is sometimes referred to as a first direction, a direction along the predetermined surface and intersecting the first direction is sometimes referred to as a second direction, and a direction intersecting the predetermined surface is sometimes referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0038] In this specification, expressions such as "upper" and "lower" are relative to the substrate. For example, the direction away from the substrate in the Z direction is referred to as "upper," and the direction approaching the substrate in the Z direction is referred to as "lower." Furthermore, when a component is referred to as a lower surface or lower end, it refers to the surface or end of the component on the substrate side. When referred to as an upper surface or upper end, it refers to the surface or end of the component opposite to the substrate. Furthermore, surfaces intersecting the X or Y directions are referred to as side surfaces, etc.

[0039] [First embodiment]

[0040] [Circuit Configuration of Memory Bare Chip MD]

[0041] Figure 1 This is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figures 2 to 4 This is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0042] also, Figure 1, multiple control terminals are shown. The multiple control terminals may be shown as control terminals corresponding to high-level signals (positive logic signals), as control terminals corresponding to low-level signals (negative logic signals), or as control terminals corresponding to both high-level and low-level signals. Figure 1 In this specification, the symbol of the control terminal corresponding to the low-level signal includes an overline. In this specification, the symbol of the control terminal corresponding to the low-level signal includes a slash (" / "). In addition, Figure 1 The description is for example only, and the specific form can be adjusted appropriately. For example, part or all of the high-level signals can be changed to low-level signals, or part or all of the low-level signals can be changed to high-level signals.

[0043] like Figure 1 As shown, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generating circuit VG and a row decoder RD. Figure 3 As shown, the peripheral circuit PC includes a sense amplifier module SAM, cache memories CM0, CM1...CM15...CMn (hereinafter, cache memories CM0, CM1...CM15...CMn may be simply referred to as "cache memories CM"; in addition, n is a natural number), a conversion circuit 80, a data cache control circuit 90, and a data cache inversion control circuit 91. In addition, as Figure 1 As shown, the peripheral circuit PC includes a sequencer SQC, an address register ADR, a command register CMR, a status register STR, an input / output control circuit I / O, and a logic circuit CTR.

[0044] [Circuit Configuration of Memory Cell Array MCA]

[0045] like Figure 2 As shown, the memory cell array MCA includes multiple memory blocks BLK. Each of the multiple memory blocks BLK includes multiple string assemblies SU. Each of the multiple string assemblies SU includes multiple memory strings MS. One end of each of the multiple memory strings MS is connected to a peripheral circuit PC via a bit line BL. In addition, the other ends of each of the multiple memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0046] The memory string MS includes a drain-side selection transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC (memory transistors), a source-side selection transistor STS, and a source-side selection transistor STSb. Hereinafter, the drain-side selection transistor STD, the source-side selection transistor STS, and the source-side selection transistor STSb may be simply referred to as selection transistors (STD, STS, STSb).

[0047] A memory cell MC is a field-effect transistor comprising a portion of a semiconductor pillar functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of a memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of the multiple memory cells MC corresponding to a single memory string MS. These word lines WL are commonly connected to all memory strings MS within a single memory block BLK.

[0048] The selection transistors (STD, STS, STSb) are field-effect transistors that include a portion of a semiconductor column that functions as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the selection transistors (STD, STS, STSb) are connected to selection gate lines (SGD, SGS, SGSb), respectively. The drain-side selection gate line SGD is provided corresponding to the string assembly SU and is commonly connected to all memory strings MS in one string assembly SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in multiple string assemblies SU. The source-side selection gate line SGSb is commonly connected to all memory strings MS in multiple string assemblies SU.

[0049] [Circuit Configuration of Voltage Generating Circuit VG]

[0050] Voltage generating circuit VG( Figure 1 ) For example, it includes a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit. These step-down circuits and step-up circuits are respectively connected to the supply voltage V CC and ground voltage V SS The voltage generating circuit VG generates a plurality of operating voltages to be applied to the bit lines BL, source lines SL, word lines WL, and select gate lines (SGD, SGS, SGSb) during read, write, and erase operations on the memory cell array MCA, in accordance with control signals from the sequencer SQC, and simultaneously outputs these voltages to the plurality of voltage supply lines. The operating voltages output from the voltage supply lines can be appropriately adjusted in accordance with the control signals from the sequencer SQC.

[0051] [Circuit Configuration of Row Decoder RD]

[0052] Row decoder RD( Figure 1 ) includes, for example, a decoding circuit and a switching circuit. The decoding circuit decodes the row address RA stored in the address register ADR. The switching circuit connects the word line WL and select gate lines (SGD, SGS, SGSb) corresponding to the row address RA to the corresponding voltage supply lines based on the output signal of the decoding circuit.

[0053] [Circuit Configuration of Sense Amplifier Module SAM]

[0054] For example, Figure 3 As shown, the sense amplifier module SAM includes a plurality of sense amplifier elements SAU0 to SAU15 corresponding to a plurality of bit lines BL. The sense amplifier elements SAU0 to SAU15 each include: a sense amplifier SA connected to the bit line BL; a wiring LBUS connected to the sense amplifier SA; latch circuits SDL, DL0 to DLn (n is a natural number) connected to the wiring LBUS; and a pre-charge transistor 55 ( Figure 4 ) and is connected to wiring LBUS. Each wiring LBUS within sense amplifier units SAU0-SAU15 is connected to wirings DBUS0-DBUS15 (hereinafter, wirings DBUS0-DBUS15 may be simply referred to as "wirings DBUS") via, for example, switching transistors DSW. Furthermore, each wiring DBUS0-DBUS15 is connected to a precharge transistor 61.

[0055] like Figure 4 As shown in FIG. 1 , the sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charge in the wiring LBUS according to the current flowing in the bit line BL. The source electrode of the sense transistor 41 is connected to the supply ground voltage V SS The drain electrode is connected to the wiring LBUS via the switching transistor 42. The gate electrode is connected to the bit line BL via the sense node SEN, the discharge transistor 43, the node COM, the clamp transistor 44, and the withstand voltage transistor 45. In addition, the sense node SEN is connected to the internal control signal line CLKSA via the capacitor 48.

[0056] In addition, the sense amplifier SA includes a voltage transmission circuit. The voltage transmission circuit makes the node COM and the sensing node SEN equal to the supply voltage V according to the data latched in the latch circuit SDL. DD The voltage supply line or supply voltage V SRC The voltage supply line is selectively turned on. The voltage transmission circuit comprises: a node N1; a charging transistor 46 connected between the node N1 and the sensing node SEN; a charging transistor 49 connected between the node N1 and the node COM; a charging transistor 47 connected between the node N1 and the supply voltage V DDand the discharge transistor 50, connected to the node N1 and the supply voltage V SRC In addition, the gate electrodes of the charging transistor 47 and the discharging transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

[0057] Furthermore, the sensing transistor 41, the switching transistor 42, the discharging transistor 43, the clamping transistor 44, the charging transistor 46, the charging transistor 49, and the discharging transistor 50 are, for example, enhancement-mode NMOS (N-Metal-Oxide-Semiconductor) transistors. The withstand voltage transistor 45 is, for example, a depletion-mode NMOS transistor. The charging transistor 47 is, for example, a PMOSS (P-Metal-Oxide-Semiconductor) transistor.

[0058] Furthermore, a control signal STB is input to the gate electrode of the switching transistor 42. A control signal XXL is input to the gate electrode of the discharge transistor 43. A control signal BLC is input to the gate electrode of the clamp transistor 44. A control signal BLS is input to the gate electrode of the withstand voltage transistor 45. A control signal HLL is input to the gate electrode of the charging transistor 46. A control signal BLX is input to the gate electrode of the charging transistor 49. These control signals STB, XXL, BLC, BLS, HLL, and BLX are output from the sequencer SQC.

[0059] Latch circuit SDL includes nodes LAT_S and INV_S; an inverter 51 having an output terminal connected to node LAT_S and an input terminal connected to node INV_S; an inverter 52 having an input terminal connected to node LAT_S and an output terminal connected to node INV_S; a switching transistor 53 connected to node LAT_S and wiring LBUS; and a switching transistor 54 connected to node INV_S and wiring LBUS. Switching transistors 53 and 54 are, for example, NMOS transistors. A control signal STL outputted from a sequencer SQC is inputted to the gate electrode of switching transistor 53. A control signal STI outputted from the sequencer SQC is inputted to switching transistor 54.

[0060] Latch circuits DL0 to DLn are configured similarly to latch circuit SDL. However, as described above, node INV_S of latch circuit SDL is electrically connected to the gate electrodes of charging transistor 47 and discharging transistor 50 in sense amplifier SA. Latch circuits DL0 to DLn differ from latch circuit SDL in this respect.

[0061] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the signal line DBS ( Figure 3 ) is connected to the sequencer SQC.

[0062] In addition, if Figure 3 As shown in the example, the signal lines transmitting the control signals STB, HLL, XXL, BLX, BLC, and BLS are connected in common between all the sense amplifier elements SAU included in the sense amplifier module SAM. DD The voltage supply line and supply voltage V SRC The voltage supply lines for the sense amplifier circuits SAM and STL are connected in common among all the sense amplifier components SAU included in the sense amplifier module SAM. Furthermore, the signal lines that transmit the control signals STI and STL of the latch circuits SDL are connected in common among all the sense amplifier components SAU included in the sense amplifier module SAM. Similarly, the signal lines TI0 to TIn and TL0 to TLn corresponding to the control signals STI and STL of the latch circuits DL0 to DLn are connected in common among all the sense amplifier components SAU included in the sense amplifier module SAM. Furthermore, the plurality of signal lines DBS are provided corresponding to each of the sense amplifier components SAU included in the sense amplifier module SAM.

[0063] [Circuit Configuration of Cache Memory CM]

[0064] For example, Figure 3 As shown, the cache memory CM includes latch circuits XDL0 to XDL15 connected to the wiring DBUS and wirings XBUS0 to XBUS15 (hereinafter, wirings XBUS0 to XBUS15 may be simply referred to as "wirings XBUS"). Data DAT ( Figure 1 ) are sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O via the DBUS wiring. Specifically, during a read operation, the data (read data) DAT read by the sense amplifier module SAM is temporarily stored in the latch circuits XDL0 to XDL15 before being transmitted from the latch circuits XDL0 to XDL15 to the input / output control circuit I / O. During a write operation, the data (write data) DAT sent from the input / output control circuit I / O is temporarily stored in the latch circuits XDL0 to XDL15 before being transmitted from the latch circuits XDL0 to XDL15 to the sense amplifier module SAM.

[0065] Latch circuits XDL0-XDL15 include nodes LAT_X and INV_X; an inverter 71 having an output terminal connected to node LAT_X and an input terminal connected to node INV_X; an inverter 72 having an input terminal connected to node LAT_X and an output terminal connected to node INV_X; a switching transistor 73 connected to node LAT_X and wiring XBUS; and a switching transistor 74 connected to node INV_X and wiring DBUS. Switching transistors 73 and 74 are, for example, NMOS transistors. Control signals XTL0-XTL15 output from conversion circuit 80 are input to the gate electrodes of switching transistors 73 of latch circuits XDL0-XDL15. Although not shown, control signals XTI0-XTI15 output from conversion circuit 80 are input to the gate electrodes of switching transistors 74 of latch circuits XDL0-XDL15.

[0066] When data is input and output in the latch circuits XDL0 to XDL15 , a control signal XTL is input to the gate electrodes of the switching transistors 73 of the latch circuits XDL0 to XDL15 , so that any of the switching transistors 73 is turned on.

[0067] [Circuit Configuration of Conversion Circuit 80]

[0068] When data is input and output in the latch circuits XDL0 to XDL15, the conversion circuit 80 ( Figure 3 ) receives the data cache control signal XTRS output from the data cache control circuit 90. The conversion circuit 80 performs a logical operation on the data cache control signal XTRS and a control signal (not shown), thereby setting one of the control signals XTL0 to XTLn to a high potential state and the others to a low potential state.

[0069] [Circuit Configuration of Data Cache Control Circuit 90]

[0070] When data is input and output in the latch circuits XDL0 to XDL15, the data cache control circuit 90 decodes the column address CA ( Figure 1 ) and output the data cache control signal XTRS based on the result.

[0071] [Circuit Configuration of Data Cache Inversion Control Circuit 91]

[0072] The data cache inversion control circuit 91 suppresses coupling noise to the bit line BL that may be generated by the output signal of the data cache control circuit 90. The data cache inversion control circuit 91 may be a logic circuit connected to the output terminal of the data cache control circuit 90, for example.

[0073] [Circuit Configuration of Sequencer SQC]

[0074] Sequencer SQC( Figure 1 ) According to the instruction data D stored in the instruction register CMR CMD , outputs internal control signals to the row decoder RD, sense amplifier module SAM and voltage generating circuit VG. In addition, the sequencer SQC appropriately transmits the state data D indicating its own state. ST Output to status register STR.

[0075] Sequencer SQC also generates a ready / busy signal and outputs it to terminal RY / / BY. While terminal RY / / BY is in a low-potential state (busy period), access to memory chip MD is generally prohibited. On the other hand, while terminal RY / / BY is in a high-potential state (ready period), access to memory chip MD is permitted. The signal output from terminal RY / / BY is sometimes referred to as the ready / busy signal RY / / BY.

[0076] [Circuit Configuration of Input / Output Control Circuit I / O]

[0077] Input and output control circuit I / O ( Figure 1 ) has: data signal input and output terminals DQ0 to DQ7; trigger signal input and output terminals DQS and / DQS; and input circuits such as comparators connected to the data signal input and output terminals DQ0 to DQ7, and output circuits such as OCD (Off Chip Driver) circuits. In addition, the input and output circuit I / O has a shift register and a buffer circuit connected to these input circuits and output circuits. The input circuit, output circuit, shift register, and buffer circuit are each supplied with a power supply voltage V CCQ and ground voltage V SS Data input via data signal input / output terminals DQ0 to DQ7 corresponds to an internal control signal from the logic circuit CTR and is output from the buffer circuit to the cache memory CM, the address register ADR, or the instruction register CMR. Furthermore, data output via data signal input / output terminals DQ0 to DQ7 corresponds to an internal control signal from the logic circuit CTR and is input from the cache memory CM or the status register STR to the buffer circuit.

[0078] [Circuit Configuration of Logic Circuit CTR]

[0079] Logic circuit CTR( Figure 1 ) receives external control signals via external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0080] [Structure of memory die MD]

[0081] Figure 5 is a schematic top view of the memory die MD. Figure 6 It will Figure 5 The structure shown is a schematic cross-sectional view taken along the AA' line and the BB' line and observed in the direction of the arrow. Figure 6 The diagram is for explaining a schematic configuration of the memory die MD and does not illustrate the number, shape, arrangement, etc. of specific configurations. Figure 7 yes Figure 5 The transistor layer L shown in C TR Schematic enlarged diagram of . Figure 8 yes Figure 5 Schematic enlarged view of the portion shown in D. Figure 9 It will Figure 8 The structure shown is a schematic cross-sectional view taken along line EE' and viewed in the direction of the arrow. Figure 10 yes Figure 9 Schematic enlarged view of the portion shown in F. Figure 11 yes Figure 5 G is a schematic enlarged view of the portion shown. Figure 12 It will Figure 11 The structure shown is a schematic cross-sectional view taken along line HH' and viewed in the direction of the arrow. Figure 13 It will Figure 11 The structure shown is a schematic cross-sectional view taken along line II' and viewed in the direction of the arrow. Figure 14 is Figure 7 The control signal transmission wiring m1 is superimposed on the diagram shown L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVR To represent the schematic diagram. Figure 15 yes Figure 14 Schematic enlarged view of the portion shown in J. Figure 16 It will Figure 15 The portion shown in K is a schematic diagram showing the bit line BL together.

[0082] For example, Figure 5 As shown, the memory die MD includes a semiconductor substrate 100. In the example shown in the figure, four memory cell array regions R arranged in the X direction and the Y direction are provided on the semiconductor substrate 100. MCA In addition, the memory cell array region R MCA Equipped with: multiple memory hole areas R MH , arranged in the X direction; and a plurality of contact connection areas R C4T , set in these memory hole areas R MHIn addition, in the memory cell array region R MCA The connection area R is set in the center of the X direction HU In addition, in the memory cell array region R MCA One end portion in the Y direction and a plurality of memory hole regions R arranged in the X direction MH Correspondingly, a plurality of contact connection areas R arranged in the X direction are provided. BLT In addition, a peripheral region R is provided at the Y-direction end of the semiconductor substrate 100. P . Surrounding area R P The Y-direction end portion of the semiconductor substrate 100 extends toward the X-direction.

[0083] For example, Figure 6 As shown, the memory die MD comprises: a semiconductor substrate 100; a transistor layer L TR , provided on the semiconductor substrate 100; the wiring layer D0, provided on the transistor layer L TR wiring layer D1, disposed above the wiring layer D0; wiring layer D2, disposed above the wiring layer D1; memory cell array layer L MCA , arranged above the wiring layer D2; wiring layer M0, arranged on the memory cell array layer L MCA wiring layer M1, provided above the wiring layer M0; and a wiring layer M2, provided above the wiring layer M1.

[0084] [Structure of Semiconductor Substrate 100]

[0085] The semiconductor substrate 100 is, for example, a semiconductor substrate comprising P-type silicon (Si) containing P-type impurities such as boron (B). Figure 6 As shown, the surface of semiconductor substrate 100 includes an N-type well region 100N containing N-type impurities such as phosphorus (P), a P-type well region 100P containing P-type impurities such as boron (B), a semiconductor substrate region 100S where neither N-type well region 100N nor P-type well region 100P is provided, and an insulating region 100I. N-type well region 100N, P-type well region 100P, and semiconductor substrate region 100S each function as a portion of multiple transistors Tr and multiple capacitors that constitute peripheral circuit PC.

[0086] [Transistor layer L TR [Structure of

[0087] For example, Figure 6As shown, a wiring layer GC is provided on the upper surface of the semiconductor substrate 100 via an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are connected to a contact CS.

[0088] The plurality of electrodes gc included in the wiring layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, other electrodes of the plurality of capacitors, and the like.

[0089] Contact CS extends in the Z direction and contacts the upper surface of semiconductor substrate 100 or electrode gc at its lower end. An impurity region containing N-type or P-type impurities is provided at the connection between contact CS and semiconductor substrate 100. Contact CS may also include, for example, a laminated film comprising a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0090] In addition, if Figure 7 As shown, in the transistor layer L TR ( Figure 6 ) of the memory hole area R MH The sense amplifier region R is set SA and latch circuit area R XDL In addition, in the transistor layer L TR ( Figure 6 ) of the wiring area R HU The word line switch region R is set WLSW In addition, relative to the transistor layer L TR ( Figure 6 ) of the memory cell array region R MCA The data control area R is set in the area offset in the Y direction. YLOG .

[0091] In the sense amplifier region R SA Configured with sense amplifier module SAM ( Figure 3 ) etc. In the latch circuit area R XDL Cache memory CM ( Figure 3 ) of the latch circuit XDL0 to XDL15. In the word line switch area R WLSW Configure the row decoder RD ( Figure 1 ) switching circuit, etc.

[0092] In the data control area R YLOG A data cache control circuit 90 ( Figure 3 ) and data cache inversion control circuit 91 ( Figure 3 ). In addition, in the data control area R YLOG Configured to control the sense amplifier module SAM ( Figure 1 、 Figure 3 ) and cache memory CM( Figure 1 、 Figure 3 ) control circuit (not shown).

[0093] [Structure of Wiring Layers D0, D1, and D2]

[0094] For example, Figure 6 As shown, a plurality of wirings included in the wiring layers D0, D1, and D2 are electrically connected to at least one of the components in the memory cell array MCA and the components in the peripheral circuit PC.

[0095] The wiring layers D0, D1, and D2 include a plurality of wirings d0, d1, and d2, respectively. The plurality of wirings d0, d1, and d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0096] [Memory cell array layer L MCA The memory hole area R MH [Structure of

[0097] For example, Figure 8 As shown, in the memory cell array layer L MCA A plurality of memory blocks BLK are arranged in the Y direction. The memory block BLK includes a plurality of string assemblies SU arranged in the Y direction. Between two adjacent memory blocks BLK in the Y direction, for example, Figure 9 As shown, an inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided.

[0098] For example, Figure 9 As shown, the memory block BLK includes: a plurality of conductive layers 110 arranged in the Z direction; a plurality of semiconductor pillars 120 extending in the Z direction; and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120 .

[0099] Conductive layer 110 is a generally plate-shaped conductive layer extending in the X-direction. It may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is provided between the multiple conductive layers 110 arranged in the Z-direction.

[0100] Conductive layer 111 is provided below conductive layer 110. Conductive layer 111 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Furthermore, insulating layer 101, such as silicon oxide (SiO 2 ), is provided between conductive layer 111 and conductive layer 110.

[0101] Conductive layer 112 is provided below conductive layer 111. Conductive layer 112 includes a semiconductor layer 113 bonded to the lower end of semiconductor pillar 120, and a conductive layer 114 in contact with the lower surface of semiconductor layer 113. Semiconductor layer 113 may comprise, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Conductive layer 114 may comprise, for example, a metal such as tungsten (W), a tungsten silicide, or other conductive layer. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is provided between conductive layer 112 and conductive layer 111.

[0102] The conductive layer 112 serves as the source line SL ( Figure 2 ) functions. The source line SL is, for example, located in the memory cell array region R MCA ( Figure 5 ) contains all the storage blocks BLK( Figure 2 、 Figure 8 )The CCP is set up through land.

[0103] The conductive layer 111 serves as the source side selection gate line SGSb ( Figure 2 ) and the gate electrodes of the plurality of source side selection transistors STSb connected thereto function. The conductive layer 111 functions as each memory block BLK ( Figure 2 、 Figure 8 ) is electrically independent.

[0104] In addition, one or more conductive layers 110 located at the bottom of the plurality of conductive layers 110 serve as source side selection gate lines SGS ( Figure 2 ) and the gate electrodes of the plurality of source side selection transistors STS connected thereto function. The plurality of conductive layers 110 function for each memory block BLK ( Figure 2 、 Figure 8 ) is electrically independent.

[0105] In addition, the plurality of conductive layers 110 located above serve as word lines WL ( Figure 2 ) and its connected multiple storage units MC ( Figure 2 ) functions as a gate electrode. The plurality of conductive layers 110 are respectively for each memory block BLK ( Figure 2 、 Figure 8 ) is electrically independent.

[0106] In addition, one or more conductive layers 110 located further above serve as drain side selection gate lines SGD and a plurality of drain side selection transistors STD connected thereto ( Figure 2 ) functions as a gate electrode. The width of the plurality of conductive layers 110 in the Y direction is smaller than that of other conductive layers 110. In addition, an inter-string component insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. The plurality of conductive layers 110 are respectively provided for each string component SU ( Figure 2 、 Figure 8 、 Figure 13 ) is electrically independent.

[0107] The semiconductor pillars 120 are arranged in a predetermined pattern in the X direction and the Y direction. The semiconductor pillars 120 serve as one memory string MS ( Figure 2 ) contains a plurality of memory cells MC and a channel region of a selection transistor (STD, STS, STSb). The semiconductor column 120 is, for example, a semiconductor column such as polysilicon (Si). The semiconductor column 120 is, for example, Figure 9 The semiconductor pillars 120 are shown to have a substantially bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided at the center.

[0108] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor pillar 120 . Figure 9 In the example shown in FIG. 1 , the boundary between the upper end of the semiconductor pillar 120 and the lower end of the impurity region 121 is indicated by a dotted line. The impurity region 121 is connected to the semiconductor pillar 120 via the contact Ch and the contact Vy ( Figure 6 ) is connected to the bit line BL.

[0109] An impurity region 122 containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor pillar 120 . Figure 9 In the example shown, the boundary between the lower end of the semiconductor pillar 120 and the upper end of the impurity region 122 is indicated by a dotted line. The impurity region 122 is connected to the semiconductor layer 113 of the conductive layer 112. The portion of the semiconductor pillar 120 directly above the impurity region 122 functions as the channel region of the source-side select transistor STSb. The outer periphery of the impurity region 122 is surrounded by the conductive layer 111 and faces the conductive layer 111.

[0110] The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. For example, Figure 10 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a blocking insulating film 133, which are stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the blocking insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumference of the semiconductor pillar 120, excluding the contact portion between the semiconductor pillar 120 and the semiconductor layer 113.

[0111] also, Figure 102 shows an example in which the gate insulating film 130 includes a charge storage film 132 made of silicon nitride or the like. However, the gate insulating film 130 may also include a floating gate made of, for example, polysilicon containing N-type or P-type impurities.

[0112] [Memory cell array layer L MCA Contact connection area R C4T [Structure of

[0113] For example, the contact connection area R C4T In, such as Figure 12 As shown, two insulating layers ST arranged in the Y direction are provided between two inter-block insulating layers ST arranged in the Y direction. O In addition, the two insulating layers ST O There are contacts connecting small areas r C4T In addition, the inter-block insulating layer ST and the insulating layer ST O A conductive layer is set between the small areas r 110 These regions extend in the X direction along the inter-block insulating layer ST.

[0114] Insulation layer ST O For example, Figure 12 The insulating layer ST extends in the Z direction and is connected to the conductive layer 112 at the lower end. O For example, silicon oxide (SiO2) is included.

[0115] Contacts connect small areas r C4T The device includes a plurality of insulating layers 110A arranged in the Z direction and a plurality of contacts C4 extending in the Z direction.

[0116] The insulating layer 110A is a substantially plate-shaped insulating layer extending in the X direction. The insulating layer 110A may also include an insulating layer such as silicon nitride (SiN). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of insulating layers 110A arranged in the Z direction.

[0117] For example, Figure 11 As shown in FIG, a plurality of contacts C4 are arranged in the X direction. The contacts C4 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Figure 12 As shown in FIG. 1 , the outer peripheral surface of the contact C4 is surrounded by the insulating layer 110A and the insulating layer 101, and is in contact with the insulating layer 110A and the insulating layer 101. Figure 6 As shown, the contact C4 extends in the Z direction, is connected to the wiring m0 in the wiring layer M0 at the upper end, and is connected to the wiring d2 in the wiring layer D2 at the lower end.

[0118] For example, Figure 12 As shown, the conductive layer connects the small area r110 The narrow width portion 110 includes a plurality of conductive layers 110 arranged in the Z direction. C4T For example, Figure 11 As shown, two adjacent memory hole regions R in the X direction MH The plurality of conductive layers 110 included in the embodiment are connected via the narrow width portion 110 C4T And conduct each other.

[0119] [Memory cell array layer L MCA Wiring area R HU [Structure of

[0120] In the wiring area R HU ( Figure 5 、 Figure 8 ) is provided with a portion of the plurality of conductive layers 110. In addition, in the wiring region R HU Multiple contacts CC are provided. These contacts CC extend in the Z direction and contact the conductive layer 110 at their lower ends. For example, the contacts CC may comprise a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). These contacts CC are connected to the drain electrode of the transistor Tr via wirings m0, m1, and m2 in the wiring layers M0, M1, and M2, contact C4, wirings d0, d1, and d2 in the wiring layers D0, D1, and D2, and contact CS.

[0121] [Memory cell array layer L MCA Contact connection area R BLT [Structure of

[0122] For example, Figure 13 As shown, in the contact connection area R BLT A plurality of insulating layers 110A arranged in the Z direction and contacts C4 extending in the Z direction are provided. BL .

[0123] For example, Figure 11 As shown, multiple contacts C4 are arranged in the X direction and the Y direction. BL Contact C4 BL It may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Figure 13 As shown, contact C4 BL The outer peripheral surface of is respectively surrounded by the insulating layer 110A and the insulating layer 101, and is in contact with these insulating layers 110A and the insulating layer 101. Figure 13 As shown, contact C4 BL It extends in the Z direction and is connected to the bit line BL at its upper end. Although not shown in the figure, the contact C4 BL At the lower end, the wiring d2 ( Figure 6 )connect.

[0124] [With respect to the memory cell array region R MCA Composition of the area offset in the Y direction]

[0125] like Figure 6 As shown, in the memory cell array area R MCA The area offset in the Y direction (with Figure 5 The contact C3 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The outer peripheral surface of the contact C3 is connected to the contact C4 ( Figure 6 ) and contact C4 BL ( Figure 13 ), is not surrounded by a conductive layer 110 or an insulating layer 101, but is surrounded by an insulating layer 102 such as silicon oxide (SiO2). Figure 6 As shown, the contact C3 extends in the Z direction, is connected to the wiring m0 in the wiring layer M0 at the upper end, and is connected to the wiring d2 in the wiring layer D2 at the lower end.

[0126] [Structure of Wiring Layers M0, M1, and M2]

[0127] For example, Figure 6 As shown, the wiring layers M0, M1, and M2 include a plurality of wirings, for example, connected to the memory cell array layer L. MCA The structure and transistor layer L TR At least one electrical connection is formed in the present invention.

[0128] The wiring layer M0 includes a plurality of wirings m0 , each of which may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0129] The wiring layer M1 includes a plurality of wirings m1 , each of which may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0130] The wiring layer M2 includes a plurality of wirings m2 , each of which may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as aluminum (Al).

[0131] In addition, the plurality of wirings m0 are provided in the memory hole region R MH The wiring above is used as the bit line BL ( Figure 2 、 Figure 6 、 Figure 13 ) plays a role. The bit line BL is as follows Figure 6 As shown in the X direction, and as Figure 13In addition, the plurality of bit lines BL are respectively connected to each string component SU ( Figure 2 、 Figure 13 ) is connected to a semiconductor column 120 included in the embodiment. Figure 13 As shown, the plurality of bit lines BL are respectively connected to the contacts C4 BL connect.

[0132] In addition, if Figure 14 and Figure 15 As shown, a plurality of wirings m1 are provided in the latch circuit region R XDL A portion of the wiring above is used as 32 control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 Control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 They extend in the X direction and are arranged in the Y direction at predetermined intervals.

[0133] In addition, if Figure 14 and Figure 15 As shown, a plurality of wirings m1 are provided in the latch circuit region R XDL A portion of the wiring above is used as two reverse control signal transmission wiring m1 INVL 、m1 INVR Function. Reverse control signal transmission wiring m1 INVL 、m1 INVR Configured in control signal transmission wiring m1 R7 And control signal transmission wiring m1 L8 The positions between them extend in the X direction and are arranged in the Y direction at a predetermined interval. That is, in the Y direction, the two inversion control signal transmission wirings m1 INVL 、m1 INVR Configured in 32 control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 Central location.

[0134] Control signal transmission wiring m1 L0 Wiring m2 passing through wiring layer M2 L0 and contact C3 L0 ( Figure 15 ) and the data cache control circuit 90 ( Figure 7 ) is electrically connected. In addition, the control signal transmission wiring m1 L0 Via contact C4 ( Figure 6) and the wiring d2, d1, d0 of the wiring layers D2, D1, D0 and the conversion circuit 80 ( Figure 3 ) electrical connection.

[0135] In addition, the control signal transmission wiring m1 R0 Wiring m2 passing through wiring layer M2 R0 and contact C3 R0 ( Figure 15 ) and the data cache control circuit 90 ( Figure 7 ) is electrically connected. In addition, the control signal transmission wiring m1 R0 Via contact C4 ( Figure 6 ) and the wiring d2, d1, d0 of the wiring layers D2, D1, D0 and the conversion circuit 80 ( Figure 3 ) electrical connection.

[0136] Similarly, the control signal transmission wiring m1 L1 、m1 R1 ~m1 L15 、m1 R15 Wiring m2 passing through wiring layer M2 L1 、m2 R1 ~m2 L15 、m2 R15 and contact C3 L1 、C3 R1 ~C3 L15 、C3 R15 ( Figure 15 ) and the data cache control circuit 90 ( Figure 7 ) is electrically connected. In addition, the control signal transmission wiring m1 L1 、m1 R1 ~m1 L15 、m1 R15 Via contact C4 ( Figure 6 ) and the wiring d2, d1, d0 of the wiring layers D2, D1, D0 and the conversion circuit 80 ( Figure 3 ) electrical connection.

[0137] In addition, the inversion control signal transmission wiring m1 INVL Wiring m2 passing through wiring layer M2 INVL and contact C3 INVL ( Figure 15 ) and the data cache inversion control circuit 91 ( Figure 7 ) electrical connection.

[0138] In addition, the inversion control signal transmission wiring m1 INVR Wiring m2 passing through wiring layer M2 INVR and contact C3 INVR ( Figure 15 ) and the data cache inversion control circuit 91 ( Figure 7 ) electrical connection.

[0139] Furthermore, as described above, the control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVR ( Figure 14 、 Figure 15 ) extends in the X direction. In contrast, the bit line BL ( Figure 6 、 Figure 13 ) extends in the Y direction. Therefore, the control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVR The position of the bit line BL in the Z direction is different, but Figure 16 As shown, the XY plane crosses (overlaps) when viewed along the Z direction. As a result, the control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVR Capacitive coupling may occur with the bit lines BL that are close to and intersect (overlap) these wirings.

[0140] [Read the action instructions]

[0141] Figure 17 It is a schematic cross-sectional view for explaining the read operation. Figure 18 1 is a schematic waveform diagram for explaining the read operation. In the following description, the word line WL as the operation target is sometimes referred to as the selected word line WL. S The other word lines WL are called non-selected word lines WL U In the following description, the memory cells MC included in the string unit SU as the target of the operation and the selected word line WL are described. S The following description will take as an example an example where a connected memory cell MC (hereinafter sometimes referred to as a "selected memory cell MC") performs a read operation.

[0142] At time t101 of the read operation, the non-selected word lines WL U Supply readout pass voltage V READ , making all memory cells MC in the on state. In addition, the voltage V is supplied to the selection gate lines (SGD, SGS, SGSb). SGVoltage V SG The size is such that an electron channel can be formed in the channel region of the selection transistor (STD, STS, STSb), thereby turning on the selection transistor (STD, STS, STSb).

[0143] At time t102 of the read operation, the selected word line WL S Supply a specified read voltage V CGR As a result, some of the selected memory cells MC are turned on, and the remaining selected memory cells MC are turned off.

[0144] At time t103 of the read operation, a voltage V is supplied to the bit line BL. DD For example, in Figure 4 In the sense amplifier SA shown in FIG. 1 , transistors 44, 45, 46, 47, and 49 are turned on, and transistors 42 and 43 are turned off. As a result, a voltage V is supplied to the bit line BL and the sense node SEN. DD , and start charging them. In addition, for example, the source line SL is supplied with a voltage V SRC , start charging them. Voltage V SRC For example, with a ground voltage V SS The voltage V SRC For example, it can also be greater than the ground voltage V SS and is less than the voltage V DD .

[0145] At time t104 of the read operation, the sensing operation starts. In the sensing operation, for example, the sense amplifier module SAM ( Figure 3 ), detects the on / off state of the memory cell MC and obtains data indicating the state of the memory cell MC. For example, in the sense amplifier SA ( Figure 4 ), the transistors 43, 44, and 45 are turned on and the transistors 42, 46, and 49 are turned off, thereby conducting the sensing node SEN of the sense amplifier SA and the bit line BL.

[0146] Here, for example, when the memory cell MC is in the on state, Figure 18 As shown by the dashed line, the voltages of bit line BL and sense node SEN become relatively low. Consequently, sense transistor 41 is turned off. On the other hand, for example, when memory cell MC is turned off, as shown by the solid line in the figure, the voltages of bit line BL and sense node SEN become relatively high. Consequently, sense transistor 41 is turned on.

[0147] At time t105 of the read operation, the sensing operation is terminated. For example, in the sense amplifier SA ( Figure 4), transistors 44 and 45 are turned on and transistors 42, 43, 46, and 49 are turned off, so that the sensing node SEN of the sense amplifier SA is electrically isolated from the bit line BL.

[0148] At time t106 of the read operation, the selected word line WL S , non-selected word line WL U , and select gate lines (SGD, SGS, SGSb) supply ground voltage V SS In addition, the bit line BL is supplied with a voltage V SRC .

[0149] In addition, after the sensing operation is performed, the transistor 42 ( Figure 4 ) is in the on state, and the sensing transistor 41 is connected to the wiring LBUS ( Figure 3 、 Figure 4 ) is turned on. As described above, the sensing transistor 41 is turned off or on according to the on / off state of the memory cell MC. Therefore, the charge of the wiring LBUS is discharged or maintained according to the on / off state of the memory cell MC. In addition, the sense amplifier element SAU ( Figure 3 、 Figure 4 ) is connected to the wiring LBUS, and the data of the wiring LBUS is latched by the latch circuit SDL, DL0~DLn.

[0150] In the read operation, data representing the state of the memory cell MC may be used as read data. In addition, in the read operation, operations such as AND and OR may be performed on the data representing the state of the memory cell MC, and the operation results may be used as read data. Figure 3 、 Figure 4 The wiring LBUS, the switching transistor DSW, and the wiring DBUS shown are transmitted to the cache memory CM ( Figure 1 、 Figure 3 ).

[0151] In addition, in the following descriptions, Figure 18 The period from time t103 to time t104 is referred to as “charging period I.” In addition, the period from time t104 to time t105 may be referred to as “sensing operation period II.”

[0152] [Data transfer operation description]

[0153] When the read data acquired by the read operation is output from the memory die MD, a data transfer operation is executed. The data transfer operation is, for example, transferring the cache memory CM ( Figure 1) is transmitted to the input / output circuit I / O ( Figure 1 ), or from the input and output circuit I / O ( Figure 1 ) input write data and other data DAT are transferred to the cache memory CM ( Figure 1 ) action.

[0154] Figure 19 It is a schematic waveform diagram used to illustrate the data transmission operation.

[0155] Furthermore, a page, the minimum unit for read and write operations, is divided into, for example, 16 sections. Hereinafter, each section divided into 16 sections is sometimes referred to as a "tier." Furthermore, the 16 tiers are further divided into tiers L and R. During data transfer, the 16 tiers L and R are sequentially selected, and data corresponding to the selected tiers L and R are sequentially transferred.

[0156] in addition, Figure 19 In the data cache control circuit 90 ( Figure 3 、 Figure 7 ) output signals, showing data cache control signals XTRS_L<0>, XTRS_R<0> to XTRS_L<15>, and XTRS_R<15>. Data cache control signals XTRS_L<0> to XTRS_L<15> correspond to the first through sixteenth levels L, respectively. Data cache control signals XTRS_R<0> to XTRS_R<15> correspond to the first through sixteenth levels R, respectively.

[0157] In addition, from the data cache control circuit 90 ( Figure 7 ) output data cache control signals XTRS_L<0>、XTRS_R<0>~XTRS_L<15>、XTRS_R<15> are referenced Figure 14 and Figure 15 The control signal transmission wiring m1 described L0 、m1 R0 ~m1 L15 、m1 R15 Transmitted to the conversion circuit 80 ( Figure 3 ).

[0158] in addition, Figure 19 In the data cache inversion control circuit 91 ( Figure 3 、 Figure 7) output signals, the figure shows data cache inversion control signals XTRS_INV_L and XTRS_INV_R. Data cache inversion control signal XTRS_INV_L is, for example, the inverted signal obtained by performing an OR operation on all of the data cache control signals XTRS_L<0> to XTRS_L<15>. Data cache inversion control signal XTRS_INV_R is, for example, the inverted signal obtained by performing an OR operation on all of the data cache control signals XTRS_R<0> to XTRS_R<15>.

[0159] In addition, from the data cache inversion control circuit 91 ( Figure 7 ) output data cache inversion control signal XTRS_INV_L, XTRS_INV_R is transmitted to the reference Figure 14 and Figure 15 The inversion control signal transmission wiring m1 described INVL 、m1 INVR .

[0160] like Figure 19 As shown, immediately before the start of data transfer, data cache control signals XTRS_L<0>, XTRS_R<0> to XTRS_L<15>, XTRS_R<15> are set to a low potential state, and data cache inversion control signals XTRS_INV_L, XTRS_INV_R are set to a high potential state.

[0161] At time t201 of the data transfer operation, the data cache control signal XTRS_L<0> transitions to a high potential state, and the data cache inversion control signal XTRS_INV_L transitions to a low potential state.

[0162] During the period from time t201 to time t203 of the data transmission operation, data corresponding to the first layer L is transmitted.

[0163] For example, when inputting an output circuit I / O ( Figure 1 ) When transmitting the data of the first level L, the reference Figure 3 The wirings XBUS0 to XBUS15 are charged. Then, the control signal XTL0 is set to a high potential state and the control signals XTL1 to XTLn are set to a low potential state by the conversion circuit 80. Thus, the data of the latch circuits XDL0 to XDL015 of the cache memory CM0 is transferred to the wirings XBUS0 to XBUS15. Then, the wirings XBUS0 to XBUS15 are connected to the bus DB ( Figure 1 ) is turned on. As a result, the data of the wiring XBUS0 to XBUS15 is transmitted to the input and output circuit I / O ( Figure 1). Similarly, the wirings XBUS0 to XBUS15 are charged sequentially, and one of the control signals XTL1 to XTL15 is sequentially in a high potential state, so that the wirings XBUS0 to XBUS15 are sequentially connected to the bus DB ( Figure 1 ) is turned on.

[0164] In addition, for example, when the input / output circuit I / O ( Figure 1 ) When acquiring data of the first level L, connect the wiring XBUS0 to XBUS15 and the bus DB ( Figure 1 ) is turned on. Thus, the input and output circuit I / O ( Figure 1 ) is transferred to the wirings XBUS0 to XBUS15. Next, the conversion circuit 80 sets the control signal XTL0 to a high potential state and the control signals XTL1 to XTL15 to a low potential state. Thus, the data of the wirings XBUS0 to XBUS15 are transferred to the latch circuit XDL0. Similarly, the wirings XBUS0 to XBUS15 are sequentially connected to the bus DB ( Figure 1 ) is turned on, so that one of the control signals XTL1~XTL15 is in a high potential state in turn.

[0165] At time t202 of the data transfer operation, the data cache control signal XTRS_R<0> transitions to a high potential state, and the data cache inversion control signal XTRS_INV_R transitions to a low potential state.

[0166] During the period from time t202 to time t205 of the data transmission operation, data corresponding to the first layer R is transmitted.

[0167] At time t203 of the data transfer operation, the data cache control signal XTRS_L<0> transitions to a low potential state, and the data cache inversion control signal XTRS_INV_L transitions to a high potential state.

[0168] At time t204 of the data transfer operation, the data cache control signal XTRS_L<1> transitions to a high potential state, and the data cache inversion control signal XTRS_INV_L transitions to a low potential state.

[0169] During the period from time t204 to time t207 of the data transmission operation, data corresponding to the second layer L is transmitted.

[0170] At time t205 of the data transfer operation, the data cache control signal XTRS_R<0> transitions to a low potential state, and the data cache inversion control signal XTRS_INV_R transitions to a high potential state.

[0171] At time t206 of the data transfer operation, the data cache control signal XTRS_R<1> transitions to a high potential state, and the data cache inversion control signal XTRS_INV_R transitions to a low potential state.

[0172] During the period from time t206 to time t208 of the data transmission operation, data corresponding to the second layer R is transmitted.

[0173] At time t207 of the data transfer operation, the data cache control signal XTRS_L<1> transitions to a low potential state, and the data cache inversion control signal XTRS_INV_L transitions to a high potential state.

[0174] Similarly, data cache control signals XTRS_L<2> through XTRS_L<15> sequentially transition to a high state. Furthermore, when any of the data cache control signals XTRS_L<2> through XTRS_L<15> transitions to a high state, the data cache inversion control signal XTRS_INV_L transitions to a low state. Furthermore, when any of the data cache control signals XTRS_R<2> through XTRS_R<15> transitions to a low state, the data cache inversion control signal XTRS_INV_L transitions to a high state. Furthermore, data corresponding to the third through sixteenth levels L are transmitted.

[0175] Similarly, data cache control signals XTRS_R<2> through XTRS_R<15> sequentially transition to a high state. Furthermore, when any of the data cache control signals XTRS_R<2> through XTRS_R<15> transitions to a high state, the data cache inversion control signal XTRS_INV_R transitions to a low state. Furthermore, when any of the data cache control signals XTRS_R<2> through XTRS_R<15> transitions to a low state, the data cache inversion control signal XTRS_INV_R transitions to a high state. Furthermore, data corresponding to the 3rd through 16th levels R is transmitted.

[0176] [Influence of coupling noise during read operation]

[0177] The read operation and the data transfer operation can be performed at independent times (asynchronous times). L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVRCapacitive coupling may occur between the bit lines BL that are close to and cross (overlap) these wirings. Figure 16 (See ). Therefore, when a data transfer operation is performed during a read operation, the voltage of the bit line BL connected to the selected memory cell MC in the OFF state decreases due to capacitive coupling, and there is a risk that the data of the selected memory cell MC will be judged as being in the ON state. In addition, the voltage of the bit line BL connected to the selected memory cell MC in the ON state increases due to capacitive coupling, and there is a risk that the data of the selected memory cell MC will be judged as being in the OFF state.

[0178] [Noise compensation during read operation]

[0179] As described above, the semiconductor memory device of this embodiment includes the inversion control signal transmission wiring m1 INVL 、m1 INVR In addition, in the data transmission operation of this embodiment, the control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 The data cache control signals XTRS_L<0>, XTRS_R<0> to XTRS_L<15>, XTRS_R<15> are inverted at the time of transmission to the inversion control signal transmission wiring m1. INVL 、m1 INVR The data cache inversion control signals XTRS_INV_L and XTRS_INV_R are inverted. This method can suppress the noise on the bit line BL caused by capacitive coupling.

[0180] In addition, the data cache inversion control signals XTRS_INV_L and XTRS_INV_R may be generated all the time when the data transfer operation is executed, or may be generated only when the data transfer operation is executed at a specific time. Figure 18 The data cache inversion control signals XTRS_INV_L and XTRS_INV_R are generated during at least one of the charging period I and the sensing period II.

[0181] For example, Figure 20 In the example, during charging period I, reference is executed Figure 19 The operation at time t201 is described. In addition, during the sensing operation period II, reference is made to Figure 19 The operation at time t202 is described.

[0182] [Second embodiment]

[0183] Next, the second embodiment will be described. The memory die MD of the second embodiment is basically configured similarly to the memory die MD of the first embodiment. However, whereas the first embodiment aims to suppress coupling noise generated on the bit lines during a read operation, the second embodiment aims to suppress coupling noise generated on the bit lines during a write operation.

[0184] [Write action description]

[0185] Figure 21 It is a schematic cross-sectional view for explaining a writing operation. Figure 22 It is a schematic waveform diagram used to explain the writing operation.

[0186] At time t301 of the write operation, for example, the bit line BL connected to the memory cell MC for which the threshold voltage is adjusted (hereinafter sometimes referred to as "write memory cell MC") is connected to the plurality of selected memory cells MC. W Supply voltage V SRC , the bit line BL connected to the memory cell MC whose threshold voltage is not adjusted (hereinafter sometimes referred to as "prohibited memory cell MC") among the plurality of selected memory cells MC P Supply voltage V DD .

[0187] At time t302 of the write operation, the selected word line WL S and non-selected word lines WL U Supply write pass voltage V PASS In addition, the drain side selection gate line SGD is supplied with a voltage V SGD .Write through voltage V PASS The magnitude of V is such that the memory cell MC can be turned on regardless of the threshold voltage of the memory cell MC. SGD The magnitude of φ is such that the drain-side selection transistor STD can be turned on or off according to the voltage of the bit line BL.

[0188] Here, for example Figure 21 As shown, the bit line BL W Supply voltage V SRC In addition, the voltage V supplied to the drain side selection gate line SGD SGD Subtract the supply to the bit line BL W The voltage V SRC The resulting voltage is greater than the threshold value of the drain side selection transistor STD. Therefore, the drain side selection transistor STD becomes on. W The channel supply voltage V of the semiconductor column 120 SRC .

[0189] On the other hand, the bit line BLP Supply voltage V DD In addition, the voltage V supplied to the drain side selection gate line SGD SGD Subtract the supply to the bit line BL P The voltage V DD The resulting voltage is lower than the threshold of the drain side selection transistor STD. Therefore, the drain side selection transistor STD becomes OFF. P The channel of the semiconductor pillar 120 becomes electrically floating. P The channel potential of the semiconductor pillar 120 is related to the selected word line WL S and non-selected word lines WL U Capacitive coupling occurs and the voltage rises to, for example, the write pass voltage V PASS about.

[0190] At time t303 of the write operation, the selected word line WL S Supply programming voltage V PGM . Programming voltage V PGM Greater than the write pass voltage V PASS .

[0191] Here, the bit line BL is connected to W The channel supply voltage V of the semiconductor column 120 SRC Therefore, the bit line BL is connected W The channel of the semiconductor column 120 is connected to the selected word line WL S Thus, electrons in the channel of the semiconductor column 120 pass through the tunnel insulating film 131 ( Figure 10 ) tunnels to the charge storage film 132 ( Figure 10 ). As a result, the threshold voltage of the write memory cell MC increases.

[0192] On the other hand, the bit line BL is connected P The channel potential of the semiconductor column 120 becomes the write pass voltage V PASS Therefore, the bit line BL is connected P The channel of the semiconductor column 120 is connected to the selected word line WL S The electric field generated between the bit lines BL is smaller than that connected W The channel of the semiconductor column 120 is connected to the selected word line WL S Therefore, the electrons in the channel of the semiconductor pillar 120 will not tunnel to the charge storage film 132 ( Figure 10 ). Therefore, the threshold voltage of the inhibited memory cell MC does not increase.

[0193] In the following description, the period from time t302 to time t303 may be referred to as “charging period III.” The period from time t303 to time t304 may be referred to as “programming operation period IV.”

[0194] [Influence of coupling noise during writing operation]

[0195] As described above, the writing operation and the data transfer operation can be performed at independent times (asynchronous times). Here, as described above, the control signal transmission wiring m1 L0 、m1 R0 ~m1 L15 、m1 R15 And reverse control signal transmission wiring m1 INVL 、m1 INVR Capacitive coupling may occur between the bit lines BL that are close to and cross (overlap) these wirings (see Figure 16 ). Therefore, when the data transfer operation is performed in the write operation, the bit line BL P The voltage of the bit line BL is reduced due to capacitive coupling. P The drain side selection transistor STD of the bit line BL is turned on, which may inhibit the increase of the threshold voltage of the memory cell MC. W The voltage of the bit line BL increases due to capacitive coupling. W The drain-side selection transistor STD is turned off, and there is a risk that the threshold voltage of the inhibited memory cell MC cannot be increased.

[0196] [Noise compensation during writing operation]

[0197] In this embodiment as well, the noise on the bit line BL due to capacitive coupling can be suppressed by the same method as in the first embodiment.

[0198] In addition, the data cache inversion control signals XTRS_INV_L and XTRS_INV_R may be generated all the time when the data transfer operation is executed, or may be generated only when the data transfer operation is executed at a specific time. Figure 21 The data cache inversion control signals XTRS_INV_L and XTRS_INV_R are generated during at least one of the charging period III and the programming operation period IV.

[0199] For example, in Figure 23 In the example, during charging period III, reference Figure 19 The operation at time t203 to t206 is described. In addition, during the programming operation period IV, reference is made to the Figure 19 The operations after time t207 are described.

[0200] In addition, in the semiconductor memory device of the second embodiment, similarly to the semiconductor memory device of the first embodiment, Figure 18 The data cache inversion control signals XTRS_INV_L and XTRS_INV_R are generated during at least one of the charging period I and the sensing period II.

[0201] [Other embodiments]

[0202] The semiconductor memory devices according to the first and second embodiments have been described above. However, these semiconductor memory devices are merely examples, and their specific configurations, operations, etc. may be modified as appropriate.

[0203] For example, the semiconductor memory device of the first embodiment and the second embodiment includes one set of inversion control signal transmission wiring m1. INVL 、m1 INVR (Two inversion control signal transmission lines) However, for example, a plurality of inversion control signal transmission lines m1 may be provided in the semiconductor memory device of the first embodiment or the second embodiment. INVL 、m1 INVR In this case, the plurality of inversion control signal transmission wirings m1 may also be connected. INVL 、m1 INVR For example, when seven sets of inversion control signal transmission wirings m1 are provided in the semiconductor memory device of the first embodiment or the second embodiment, INVL 、m1 INVR When 32 control signal transmission lines m1 L0 、m1 R0 ~m1 L15 、m1 R15 In the example, every 4 lines can have 1 set of reverse control signal transmission wiring m1 INVL 、m1 INVR .

[0204] Furthermore, in the first and second embodiments, during data transfer operations, the timing of any inversion of the data cache control signals XTRS_L<0>, XTRS_R<0> to XTRS_L<15>, and XTRS_R<15> coincides with the timing of any inversion of the data cache inversion control signals XTRS_INV_L and XTRS_INV_R. However, these timings do not necessarily need to be strictly aligned. However, from the perspective of noise suppression, it is ideal that at least a portion of the period from the start to the end of the inversion of the data cache control signals XTRS_L<0>, XTRS_R<0> to XTRS_L<15>, and XTRS_R<15> overlaps with at least a portion of the period from the start to the end of the inversion of the data cache inversion control signals XTRS_INV_L and XTRS_INV_R.

[0205] In addition, in the first and second embodiments, the control signal transmission wiring m1 is suppressed. L0 、m1 R0 ~m1 L15 、m1 R15 The coupling noise between the bit line BL and the bit line BL is suppressed, but the present invention is not limited thereto. For example, the present invention can also be applied when suppressing the coupling noise between any two of the wirings m0, m1, and m2.

[0206] Furthermore, while the above embodiment suppresses coupling noise caused by the data cache control signal XTRS, whose signal state (H state, L state) changes asynchronously with respect to read and write operations, the present invention is not limited to this. For example, the present invention can also be applied to suppress coupling noise caused by a signal whose signal state (H state, L state) changes synchronously with respect to read and write operations.

[0207] [other]

[0208] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0209] [Explanation of symbols]

[0210] 90: Data cache control circuit

[0211] 91: Data cache inversion control circuit

[0212] 110: conductive layer

[0213] 120:Semiconductor column

[0214] MD: Memory Die

[0215] MCA: Memory Cell Array

[0216] PC: Peripheral Circuit

[0217] WL: Word Line

[0218] BL: bit line

[0219] m1 L0 ,m1 R0 ~m1 L15 ,m1 R15 :Control signal transmission wiring

[0220] m1 INVL ,m1 INVR : Reverse control signal transmission wiring.

Claims

1. A semiconductor memory device comprising: substrate; a plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate and extending in a second direction intersecting the first direction; a first semiconductor column extending in the first direction and facing the plurality of first conductive layers; a first bit line extending in a third direction intersecting the first direction and the second direction and provided at a position overlapping with the first semiconductor pillar when viewed from the first direction; a first wiring including a portion overlapping the first bit line when viewed from the first direction; and The second wiring includes a portion overlapping the first bit line when viewed from the first direction; and When a predetermined period during which the voltage of the first wiring changes from a high potential state to a low potential state is defined as a first period, When the predetermined period during which the voltage of the second wiring changes from the low potential state to the high potential state is defined as the second period, At least a portion of the second period overlaps with at least a portion of the first period.

2. The semiconductor memory device according to claim 1, wherein When the voltage of the first wiring is changed from a low potential state to a high potential state, a predetermined period after the first period is set as a third period. When the voltage of the second wiring is changed from a high potential state to a low potential state and a predetermined period after the second period is set as a fourth period, At least a portion of the fourth period overlaps with at least a portion of the third period.

3. The semiconductor memory device according to claim 2, comprising a third wiring including a portion overlapping the first bit line when viewed from the first direction, When the voltage of the third wiring is changed from a high potential state to a low potential state, a predetermined period after the third period is set as a fifth period. When the voltage of the second wiring is changed from a low potential state to a high potential state and a predetermined period after the fourth period is set as a sixth period, At least a portion of the sixth period overlaps with at least a portion of the fifth period.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein The first period and the second period are included in a period from the start of charging of the first bit line to the completion of sensing of the first bit line in a read operation.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein The first period and the second period are included in a period from the start of charging of the first bit line to the completion of supplying a programming voltage to any one of the plurality of first conductive layers in a write operation.

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