OLED display panel

Abstract

The present invention provides an OLED display panel, which includes an array substrate, a driving transistor is arranged in the array substrate, a first light-emitting device electrically connected to the driving transistor, and a second light-emitting device electrically connected to the first light-emitting device are arranged above the driving transistor; wherein, in the light emitting direction of the display panel, the first light-emitting device and the second light-emitting device are arranged vertically; the present invention prepares two OLED light-emitting device structures connected in series for a single pixel to improve the light-emitting life of the light-emitting device, thereby solving the problem of the short light-emitting life of the existing OLED panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to an OLED display panel. Background Art

[0002] With the continuous development of the display industry, OLED display panels are considered to be the next generation of new display application technology due to their advantages such as self-luminescence, high contrast, wide viewing angle, fast response, and lighter weight. Especially in the field of high-end displays, they have a broad application market and development prospects and are widely used in smart phones, tablet computers, full-color TVs, etc.

[0003] Since OLED light-emitting devices are current-type organic light-emitting devices, the lifespan of OLED display devices is relatively short. The red light lifespan is as high as 160,000 hours, the green light lifespan is 60,000 hours, and the blue light efficiency is only 8.7cd / A, with a lifespan of only 23,000 hours. The service life of traditional LCD screens is between 40,000 and 60,000 hours. Therefore, the luminous lifespan of OLED panels is shorter than that of LCD screens. It is necessary to propose a new OLED display panel to solve the problem of the short luminous lifespan of OLED display panels. Summary of the invention

[0004] Based on the existing technical problems, the present application provides an OLED display panel, which can solve the problem of short luminous life of the OLED display panel in the existing technology.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] An embodiment of the present invention provides an OLED display panel, which includes an array substrate, a driving transistor is arranged in the array substrate, and a light-emitting device electrically connected to the driving transistor is arranged on the driving transistor; wherein the same driving transistor is electrically connected to at least two of the light-emitting devices, and in the thickness direction of the display panel, the two light-emitting devices are arranged in alignment.

[0007] According to an optional embodiment of the present invention, the driving transistor includes a substrate, a light-shielding layer located on the substrate, a buffer layer covering the light-shielding layer, an active layer located on the buffer layer, a gate insulating layer located on the active layer, a gate located on the gate insulating layer, an interlayer insulating layer covering the gate, a source and a drain located on the interlayer insulating layer, a passivation layer covering the source and the drain, and a planarization layer located on the passivation layer; wherein the drain is electrically connected to the light-shielding layer through a signal via.

[0008] According to an optional embodiment of the present invention, a first light-emitting device is arranged above the driving transistor, and the first light-emitting device includes a first anode located above the planarization layer, a first hole injection layer and a first hole transport layer located above the first anode, a first light-emitting material layer located above the first hole injection layer and the first hole transport layer, a first electron transport layer and a first electron injection layer located above the first light-emitting material layer, and a first cathode layer located above the first electron transport layer and the first electron injection layer; the first anode is electrically connected to the drain through a first anode via.

[0009] According to an optional embodiment of the present invention, a second light-emitting device is arranged above the first light-emitting device, and the second light-emitting device includes a second anode located above the first cathode layer, a second hole injection layer and a second hole transport layer located above the second anode, a second light-emitting material layer located above the second hole injection layer and the second hole transport layer, a second electron transport layer and a second electron injection layer located above the second light-emitting material layer, and a second cathode layer located above the second electron transport layer and the second electron injection layer; wherein the second anode is electrically connected to the first anode through a second anode via, and the second cathode layer is electrically connected to the first cathode layer through a second cathode via.

[0010] According to an optional embodiment of the present invention, a first packaging layer is further disposed between the first cathode layer and the second anode layer.

[0011] According to an optional embodiment of the present invention, a second encapsulation layer is further provided on a side of the second cathode layer away from the second anode.

[0012] According to an optional embodiment of the present invention, the material of the active layer is a semiconductor material selected from the group consisting of low temperature polysilicon material and metal oxide semiconductor material.

[0013] According to an optional embodiment of the present invention, the red / green / blue light-emitting material layers in the first light-emitting material layer and the second light-emitting material layer are arranged in alignment.

[0014] According to an optional embodiment of the present invention, the material of the first cathode layer and the second cathode layer is a light-transmitting material selected from the group consisting of magnesium, silver, IGZO material, IZO material and IGTO material.

[0015] According to an optional embodiment of the present invention, the material of the second anode is transparent ITO.

[0016] The beneficial effects of the present invention are as follows: an embodiment of the present invention provides an OLED display panel, which includes an array substrate, a driving transistor is arranged in the array substrate, and a light-emitting device electrically connected to the driving transistor is arranged on the driving transistor; wherein the same driving transistor is electrically connected to at least two light-emitting devices, and the two light-emitting devices are arranged in alignment in the thickness direction of the display panel; the present invention prepares two OLED light-emitting device structures connected in series for a single pixel to improve the light-emitting life of the device, thereby solving the problem of short life of the light-emitting devices of the existing OLED panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 It is a schematic diagram of the film layer structure of an OLED display panel in the prior art.

[0019] Figure 2 A schematic diagram of a film layer structure of an OLED display panel is provided for an embodiment of the present invention.

[0020] Figures 3 to 6 A structural schematic diagram of a preparation process of an OLED display panel is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following descriptions of the embodiments are made with reference to the attached diagrams to illustrate specific embodiments in which the present invention may be implemented. The directional terms mentioned in the present invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached diagrams. Therefore, the directional terms used are used to illustrate and understand the present invention, rather than to limit the present invention. In the figures, units with similar structures are represented by the same reference numerals, and the dotted lines in the figures represent those that do not exist in the structure and only illustrate the shape and position of the structure.

[0022] like Figure 1As shown, the prior art provides a schematic diagram of the film layer structure of an OLED display panel. The OLED display panel 10 in the prior art includes a substrate 11, a driving circuit layer located on the substrate 11, a light-emitting functional layer located on the driving circuit layer, and an encapsulation layer 29 located on the light-emitting functional layer, the driving circuit layer includes a light-shielding layer 12 located on the substrate 11, a buffer layer 13 covering the light-shielding layer 12, an active layer 14 located on the buffer layer 13, a gate insulating layer 15 located on the active layer 14, a gate 16 located on the gate insulating layer 15, an interlayer insulating layer 17 covering the gate 16, a source electrode 18 and a drain electrode 19 located on the interlayer insulating layer 17, a passivation layer 21 covering the source electrode 18 and the drain electrode 19, and a planarization layer 22 located on the passivation layer 21. The active layer 14 includes a channel region 141, a source doping region 142 and a drain doping region 143 located on both sides of the channel region 141, the source 18 is electrically connected to the source doping region 142 through a source contact hole, and the drain 19 is electrically connected to the drain doping region 143 through a drain contact hole. The light-emitting functional layer includes a pixel definition layer 24 located on the planarization layer 22 and a light-emitting device located in a pixel opening of the pixel definition layer 24, the light-emitting device includes an anode 23 located on the planarization layer 22, a hole injection layer 251 and a hole transport layer 252 located on the anode 23, a light-emitting material layer 26 located on the hole injection layer 251 and the hole transport layer 252, an electron transport layer and an electron injection layer 27 located on the light-emitting material layer 26, and a cathode 28 located on the electron transport layer and the electron injection layer 27, the anode 23 is electrically connected to the drain 19 through an anode via, and the cathode 28 is electrically connected to the negative pole of an external power source.

[0023] The luminescent material layer 26 includes a red luminescent unit 261, a green luminescent unit 262 and a blue luminescent unit 263. The life of the red luminescent unit 261 is up to 160,000 hours, the life of the green luminescent unit 262 is 60,000 hours, and the efficiency of the blue luminescent unit 263 is only 8.7 cd / A, and the life is only 23,000 hours. The lifespans of the red luminescent unit 261, the green luminescent unit 262 and the blue luminescent unit 263 are different, and the lifespan of the blue luminescent unit 263 is even lower than that of the pixel unit of the liquid crystal panel, resulting in the problem of a shorter overall lifespan of the light-emitting devices of the OLED display panel 10.

[0024] In view of the above technical problems, an embodiment of the present invention provides an OLED display panel, which includes an array substrate, a driving transistor is arranged in the array substrate, and a light-emitting device electrically connected to the driving transistor is arranged on the driving transistor; wherein the same driving transistor is electrically connected to at least two light-emitting devices, and the two light-emitting devices are arranged in alignment in the thickness direction of the display panel; the present invention prepares two OLED light-emitting device structures connected in series for a single pixel to improve the light-emitting life of the device, thereby solving the problem of short life of the light-emitting devices of the existing OLED display panels.

[0025] like Figure 2 As shown, an embodiment of the present invention provides a schematic diagram of a structural film layer structure of an OLED display panel. The OLED display panel 30 includes an array substrate, a light-emitting functional layer located on the array substrate, and an encapsulation layer located on the light-emitting functional layer. A driving transistor is arranged on the array substrate, and the driving transistor includes a substrate 31, a light shielding layer 32 located on the substrate 31, a buffer layer 33 covering the light shielding layer 32, an active layer 34 located on the buffer layer 33, a gate insulating layer 35 located on the active layer 34, a gate 36 located on the gate insulating layer 35, an interlayer insulating layer 37 covering the gate 36, a source 38 and a drain 39 located on the interlayer insulating layer 37, a passivation layer 41 covering the source 38 and the drain 39, and a planarization layer 42 located on the passivation layer 41. The active layer 34 includes a channel region 341, a source doping region 342 and a drain doping region 343 located on both sides of the channel region 341, the source 38 is electrically connected to the source doping region 342 through a source contact hole, the drain 39 is electrically connected to the drain doping region 343 through a drain contact hole, and the drain 39 is electrically connected to the light shielding layer 22 through a signal via. The material of the active layer 34 is a semiconductor material selected from the group consisting of low temperature polysilicon material and metal oxide semiconductor material.

[0026] The light-emitting functional layer includes a first light-emitting device electrically connected to the driving transistor, and a second light-emitting device electrically connected to the first light-emitting device; wherein, in the light emitting direction of the display panel, the first light-emitting device and the second light-emitting device are arranged vertically, that is, the first light-emitting device is above the driving transistor, and the second light-emitting device is above the first light-emitting device.

[0027] A first pixel definition layer 44 is arranged on the planarization layer 42, and the first pixel definition layer 44 is arranged at intervals to form a first pixel opening. A first light-emitting device is arranged in the first pixel opening, and the first light-emitting device includes a first anode 43 located on the planarization layer 42, a first hole injection layer 451 and a first hole transport layer 452 located on the first anode 43, a first light-emitting material layer 46 located on the first hole injection layer 451 and the first hole transport layer 452, a first electron transport layer and a first electron injection layer 47 located on the first light-emitting material layer 46, and a first cathode layer 48 located on the first electron transport layer and the first electron injection layer 47; the first anode 43 is electrically connected to the drain 39 through a first anode via.

[0028] A first encapsulation layer 49 is arranged on the first cathode layer 48, a second pixel definition layer 52 is arranged on the first encapsulation layer 49, the second pixel definition layers 52 are arranged at intervals to form a second pixel opening, and a second light-emitting device is arranged in the second pixel opening. The second light-emitting device includes a second anode 51 located on the first encapsulation layer 49, a second hole injection layer 531 and a second hole transport layer 532 located on the second anode 51, a second light-emitting material layer 54 located on the second hole injection layer 531 and the second hole transport layer 532, a second electron transport layer and a second electron injection layer 55 located on the second light-emitting material layer 54, and a second cathode layer 56 located on the second electron transport layer and the second electron injection layer 55; a second encapsulation layer 57 is arranged on the second cathode layer 56. Among them, the second anode 51 is electrically connected to the first anode 43 through the second anode via, and the second cathode layer 56 is electrically connected to the first cathode layer 48 through the second cathode via, so as to realize two OLED light-emitting devices in series in the same pixel; the two layers of anodes are connected and pass the same signal, and the second anode 51 is a light-transmitting material, preferably transparent ITO; the two layers of cathodes are connected and pass the same signal, and the second cathode layer 56 can use the same light-transmitting material as the first cathode layer 48, and the material of the first cathode layer 48 and the second cathode layer 56 is a light-transmitting material selected from magnesium, silver, IGZO material, IZO material and IGTO material.

[0029] The red / green / blue light-emitting material layers in the first light-emitting material layer 46 and the second light-emitting material layer 54 are arranged in alignment. The first light-emitting material layer 46 includes a first red light-emitting material layer 461, a first green light-emitting material layer 462 and a first blue light-emitting material layer 463, the second light-emitting material layer 54 includes a second red light-emitting material layer 541, a second green light-emitting material layer 542 and a second blue light-emitting material layer 543, the first red light-emitting material layer 461 is arranged in alignment with the second red light-emitting material layer 541, the first green light-emitting material layer 462 is arranged in alignment with the second green light-emitting material layer 542, and the first blue light-emitting material layer 463 is arranged in alignment with the second blue light-emitting material layer 543, so that the brightness of the light-emitting device of a single pixel is enhanced and the life is extended, thereby improving the brightness and service life of the entire OLED display panel.

[0030] According to the OLED display panel in the above embodiment, the present invention further provides a method for preparing an OLED display panel, the method comprising:

[0031] Step S10, providing an array substrate, wherein the array substrate has a driving transistor.

[0032] Step S20, preparing a first light-emitting device on the driving transistor, and preparing a second light-emitting device on the first light-emitting device; wherein the driving transistor is electrically connected to the first light-emitting device, and the first light-emitting device is electrically connected to the second light-emitting device.

[0033] Figures 2 to 6 The present invention provides a structural diagram of an OLED display panel manufacturing process. This embodiment takes a driving transistor as an example to illustrate a partial structural diagram of an array substrate. Other structures are similar to conventional array substrate structures and will not be described in detail here.

[0034] like Figure 3 As shown, a substrate 31 is provided, and the substrate 31 is preferably a glass substrate. A light shielding layer 32 is prepared on the substrate 31 by physical vapor deposition. The material of the light shielding layer 32 is a single layer of metal selected from copper, aluminum, molybdenum and titanium, or a superimposed film layer of two or more metal alloys, and its thickness is to A mask is used to define the pattern of the light shielding layer 32. A buffer layer 33 covering the light shielding layer 32 is prepared on the substrate 31. A single layer or a multi-layer structure of silicon oxide or silicon nitride can be used. The thickness of the buffer layer 33 is 1000 mm / s. to

[0035] The material of the active layer 34 is one or more materials selected from the group consisting of indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide. The thickness of the active layer 34 is to The active layer 34 is deposited on the buffer layer 33 by a magnetron sputtering method, a metal organic chemical vapor deposition method or a pulse laser evaporation method. After the active layer 34 is deposited, an annealing treatment is performed. The annealing treatment can be performed in a dry air atmosphere at 400°C for about 0.5 hours. After the annealing treatment is completed, the active layer 34 is etched by a wet etching process or a dry etching process using oxalic acid as an etching solution. After the etching process, the entire metal oxide film of the active layer 34 will be patterned to form an island-shaped metal oxide semiconductor layer. The active layer 34 includes a channel region 341, a source doping region 342 and a drain doping region 343 located on both sides of the channel region 341.

[0036] A gate insulating layer 35 is prepared on the active layer 34, and a gate electrode 36 is prepared on the gate insulating layer 35; the material of the gate insulating layer 35 is generally silicon oxide, silicon nitride, silicon oxynitride, or a sandwich structure of the three; the material of the gate electrode 36 is a metal material, such as copper, aluminum, titanium, tantalum, tungsten, molybdenum, chromium, etc. The gate electrode 36 is formed on the gate insulating layer 35 by a physical vapor deposition method, and then a photolithography process is performed to form a gate pattern. The gate insulating layer 35 is used to separate the gate electrode 36 from the active layer 34, and the thickness of the gate insulating layer 35 is to The mask defines the gate 36 pattern, and the gate metal in the area not covered by the photoresist is etched. The exposed gate insulating layer 35 is then removed by etching. The active layer not covered by the gate insulating layer 35 and the gate 36 is plasma treated with gases such as Ar, N2, He, and H2 to make this part of the area conductive, while the part covered by the gate insulating layer 35 and the gate 36 maintains semiconductor characteristics to form a TFT channel. The source doping region 342 and the drain doping region 343 are both conductive regions, and the channel region 341 is a semiconductor region.

[0037] An interlayer insulating layer 37 is formed on the buffer layer 33. The interlayer insulating layer 37 covers the gate 36, the gate insulating layer 35 and the active layer 34. The material of the interlayer insulating layer 37 is a silicon oxide or silicon nitride film. The thickness of the interlayer insulating layer 37 is 1000 Å. to The opening structure is formed to define the contact holes between the source / drain and the active layer, as well as the signal vias with the light shielding layer. The source 38 and the drain 39 are prepared on the interlayer insulating layer 37. The material of the source 38 and the drain 39 can be a single layer of metal such as copper, aluminum, molybdenum and titanium, or a metal alloy or a multi-layer composite film layer with a thickness of to The source electrode 38 is electrically connected to the source doping region through the source contact hole in the interlayer insulating layer 37, the drain electrode 39 is electrically connected to the drain doping region through the drain contact hole in the interlayer insulating layer 37, and the drain electrode 39 and the light shielding layer 32 are electrically connected through the signal via. A passivation layer 41 covering the source electrode 38 and the drain electrode 39 is prepared on the interlayer insulating layer 37, and a planarization layer 42 is prepared on the passivation layer 41 to complete the preparation of the driving transistor.

[0038] A first anode via is prepared at a position of the passivation layer 41 and the planarization layer 42 corresponding to the drain electrode 39 , and a first anode 43 is prepared on the planarization layer 42 . The first anode 43 is electrically connected to the drain electrode 39 through the first anode via. The interlayer insulating layer 37 is also prepared with a first pixel definition layer 44, and the first pixel definition layer 44 is arranged at intervals to form a first pixel opening. In the first pixel opening, a first hole injection layer 451 and a first hole transport layer 452 are prepared on the first anode 43 by evaporation, and a first light-emitting material layer 46 is evaporated on the first hole injection layer 451 and the first hole transport layer 452 by inkjet printing or metal mask plate. A first electron transport layer and a first electron injection layer 47 are prepared on the first light-emitting material layer 46, a first cathode layer 48 is prepared on the first electron transport layer and the first electron injection layer 47, and a first encapsulation layer 49 is prepared on the first cathode layer 48. The first encapsulation layer 49 is preferably a transparent film layer, which does not affect the light emitted by the first light-emitting material layer 46. The first anode 43, the first light-emitting material layer 46 and the first cathode layer 48 form a first light-emitting device, and the first light-emitting material layer 46 includes a first red light-emitting material layer 461, a first green light-emitting material layer 462 and a first blue light-emitting material layer 463.

[0039] like Figure 4 As shown, a second anode via hole 431 is provided at the end of the first encapsulation layer 49, the first cathode layer 48, the first electron transport layer, the first electron injection layer 47 and the first pixel definition layer 44 corresponding to the first anode 43. Figure 5 As shown, in the non-opening area, a second cathode via hole 481 is opened in the first packaging layer 49 corresponding to the first cathode layer 48 .

[0040] like Figure 6 As shown, a second anode 51 is prepared on the first encapsulation layer 49, and the second anode 51 is electrically connected to the first anode 43 through the second anode via 431. A second pixel definition layer 52 is prepared on the first encapsulation layer 49, and the second pixel definition layer 52 is arranged at intervals to form a second pixel opening. Figure 6 Combination Figure 2, in the second pixel opening, a second hole injection layer 531 and a second hole transport layer 532 are prepared on the second anode 51 by evaporation, a second light-emitting material layer 54 is evaporated on the second hole injection layer 531 and the second hole transport layer 532 by inkjet printing or metal mask plate, a second electron transport layer and a second electron injection layer 55 are prepared on the second light-emitting material layer 54, a second cathode layer 56 is prepared on the second electron transport layer and the second electron injection layer 55, a second encapsulation layer 57 is prepared on the second cathode layer 56, the second encapsulation layer 57 is preferably a superimposed film layer of an inorganic layer and an organic layer, the second cathode via 481 extends the second pixel definition layer 52, the second electron transport layer and the second electron injection layer 55, and the second cathode layer 56 is electrically connected to the first cathode layer 48 through the second cathode via 481.

[0041] The second anode 51, the second light-emitting material layer 54 and the second cathode layer 56 form a second light-emitting device, and the second light-emitting material layer 54 includes a second red light-emitting material layer 541, a second green light-emitting material layer 542 and a second blue light-emitting material layer 543. In this embodiment, the second anode 51 is electrically connected to the first anode 43 through the second anode via hole, and the second cathode layer 56 is electrically connected to the first cathode layer 48 through the second cathode via hole, so as to realize two OLED light-emitting devices connected in series in the same pixel.

[0042] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. An OLED display panel, characterized in that: It comprises an array substrate, wherein a driving transistor is arranged in the array substrate, and a light emitting device electrically connected to the driving transistor is arranged on the driving transistor; In which, the same driving transistor is electrically connected to at least two of the light-emitting devices, and in the thickness direction of the display panel, the two light-emitting devices are arranged in alignment, a first light-emitting device is arranged above the driving transistor, and a second light-emitting device is arranged above the first light-emitting device, the first light-emitting device includes a stacked first anode, a first light-emitting material layer located above the first anode, and a first cathode layer located above the first light-emitting material layer, the second light-emitting device includes a second anode located above the first cathode layer, a second light-emitting material layer located above the second anode, and a second cathode layer located above the second light-emitting material layer, the first anode is electrically connected to the driving transistor through a first anode via, the second anode is electrically connected to the first anode through a second anode via, the second cathode layer is electrically connected to the first cathode layer through a second cathode via, and a first packaging layer is also arranged between the first cathode layer and the second anode.

2. The OLED display panel according to claim 1, characterized in that: The driving transistor includes a substrate, a light-shielding layer located on the substrate, a buffer layer covering the light-shielding layer, an active layer located on the buffer layer, a gate insulating layer located on the active layer, a gate located on the gate insulating layer, an interlayer insulating layer covering the gate, a source and a drain located on the interlayer insulating layer, a passivation layer covering the source and the drain, and a planarization layer located on the passivation layer; wherein the drain is electrically connected to the light-shielding layer through a signal via.

3. The OLED display panel according to claim 2, characterized in that: The first light-emitting device includes the first anode located on the planarization layer, a first hole injection layer and a first hole transport layer located on the first anode, the first light-emitting material layer located on the first hole injection layer and the first hole transport layer, a first electron transport layer and a first electron injection layer located on the first light-emitting material layer, and the first cathode layer located on the first electron transport layer and the first electron injection layer; The first anode is electrically connected to the drain through a first anode via.

4. The OLED display panel according to claim 3, characterized in that: The second light-emitting device includes a second hole injection layer and a second hole transport layer located above the second anode, the second light-emitting material layer located above the second hole injection layer and the second hole transport layer, a second electron transport layer and a second electron injection layer located above the second light-emitting material layer, and the second cathode layer located above the second electron transport layer and the second electron injection layer.

5. The OLED display panel according to claim 1, characterized in that: A second packaging layer is further disposed on a side of the second cathode layer away from the second anode.

6. The OLED display panel according to claim 2, characterized in that: The material of the active layer is a semiconductor material selected from low temperature polysilicon material and metal oxide semiconductor material.

7. The OLED display panel according to claim 1, characterized in that: The red / green / blue light-emitting material layers in the first light-emitting material layer and the second light-emitting material layer are arranged in alignment.

8. The OLED display panel according to claim 1, characterized in that: The material of the first cathode layer and the second cathode layer is a light-transmitting material selected from the group consisting of magnesium, silver, IGZO material, IZO material and IGTO material.

9. The OLED display panel according to claim 1, characterized in that: The material of the second anode is transparent ITO.

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