A chip structure and its manufacturing method

Abstract

This application provides a chip structure and its manufacturing method. The chip structure includes an epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer, and a transparent conductive layer stacked sequentially. A first electrode and a second electrode are disposed on the side of the first type semiconductor layer away from the active layer. The first electrode is connected to the first type semiconductor layer, and the second electrode is connected to the transparent conductive layer. An insulating structure is disposed between the first electrode and the second electrode in a direction parallel to the surface of the first type semiconductor layer to insulate the first electrode from the second electrode. By providing the insulating structure, the risk of short circuits in the chip electrodes can be reduced, and the reliability of the chip can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip structure and its manufacturing method. Background Technology

[0002] With the rapid development of light-emitting diodes (LEDs), their applications are changing rapidly, especially in display technology. As the resolution of LED displays increases, the spacing between LED chips becomes smaller, and the chip size also decreases.

[0003] As chip size decreases, the spacing between LEDs also becomes smaller, making wire bonding and bonding of LED electrodes more difficult, resulting in a greater risk of short circuits and affecting the luminous efficiency and reliability of LEDs. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a chip structure and a method for manufacturing the same, which can reduce the risk of ionization short circuits and improve chip reliability.

[0005] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, embodiments of this application provide a chip structure, including:

[0008] An epitaxial structure, the epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer and a transparent conductive layer stacked sequentially;

[0009] A first electrode and a second electrode are disposed on the side of the first type semiconductor layer away from the active layer;

[0010] The first electrode is connected to a first-type semiconductor layer, and the second electrode is connected to a transparent conductive layer;

[0011] An insulating structure is provided between the first electrode and the second electrode in a direction parallel to the surface of the first type of semiconductor layer, so as to insulate the first electrode and the second electrode.

[0012] In one possible implementation, the insulating structure includes a first transparent substrate, a reflector, and a total insulating layer stacked together.

[0013] In one possible implementation, the insulating structure includes a second transparent substrate and an insulating Bragg reflective layer stacked together.

[0014] In one possible implementation, the insulating structure includes a third substrate.

[0015] In one possible implementation, the first electrode is connected to a first-type semiconductor layer, and the second electrode is connected to a transparent conductive layer, including:

[0016] The first electrode is connected to the first type of semiconductor layer through a first conductive channel;

[0017] The second electrode is connected to the transparent conductive layer through a second conductive channel.

[0018] An isolation layer is provided on the sidewall of the first conductive channel and / or the second conductive channel.

[0019] In one possible implementation, the first transparent substrate, the second transparent substrate, and the third substrate are located on the side of the first electrode away from the second electrode, and on the side of the second electrode away from the first electrode.

[0020] In one possible implementation, the surfaces of the first transparent substrate, the second transparent substrate, and the third substrate located on the side of the first electrode away from the second electrode, and the side of the second electrode away from the first electrode, away from the first electrode, extend beyond the surfaces of the first electrode and the second electrode away from the first semiconductor layer.

[0021] In one possible implementation, the total insulating layer includes a first insulating layer and a second insulating layer;

[0022] In a direction perpendicular to the surface of the first semiconductor layer, the second insulating layer is located on the side of the first insulating layer away from the reflector;

[0023] In a direction parallel to the surface of the first type of semiconductor layer, the first insulating layer is located between the first conductive channel and the second conductive channel;

[0024] The surface of the second insulating layer on the side away from the first type of semiconductor layer extends beyond the surfaces of the first electrode and the second electrode on the side away from the first type of semiconductor layer.

[0025] In one possible implementation, the surface of the insulating Bragg reflector layer on the side away from the first type of semiconductor layer extends beyond the surfaces of the first electrode and the second electrode on the side away from the first type of semiconductor layer.

[0026] In one possible implementation, the surface of the third substrate on the side away from the first type of semiconductor layer extends beyond the surfaces of the first electrode and the second electrode on the side away from the first type of semiconductor layer.

[0027] Secondly, embodiments of this application provide a chip structure manufacturing method, including:

[0028] An epitaxial structure is formed, the epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer and a transparent conductive layer stacked sequentially;

[0029] A first electrode and a second electrode are formed on the side of the first type semiconductor layer away from the active layer;

[0030] An insulating structure is formed between the first electrode and the second electrode in a direction parallel to the surface of the first type of semiconductor layer, so as to insulate the first electrode and the second electrode.

[0031] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0032] This application provides a chip structure and its manufacturing method. The chip structure includes an epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer, and a transparent conductive layer stacked sequentially. A first electrode and a second electrode are disposed on the side of the first type semiconductor layer away from the active layer. The first electrode is connected to the first type semiconductor layer, and the second electrode is connected to the transparent conductive layer. An insulating structure is disposed between the first electrode and the second electrode in a direction parallel to the surface of the first type semiconductor layer to insulate the first electrode from the second electrode. By providing the insulating structure, the risk of short circuits in the chip electrodes can be reduced, and the reliability of the chip can be improved. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0035] Figure 1 A schematic diagram of a chip structure discovered by the applicant through research is shown;

[0036] Figure 2 A schematic diagram of a chip structure provided in an embodiment of this application is shown;

[0037] Figure 3 A schematic diagram of yet another chip structure provided in an embodiment of this application is shown;

[0038] Figure 4 A schematic diagram of another chip structure provided in an embodiment of this application is shown;

[0039] Figure 5 A flowchart illustrating a chip structure manufacturing method provided in an embodiment of this application is shown. Detailed Implementation

[0040] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0042] As described in the background section, the applicant's research has revealed that with the rapid development of light-emitting diodes (LEDs), their applications are evolving rapidly, particularly in display technology. As LED display resolutions increase, the spacing between LED chips becomes smaller, and the chip size also shrinks. This reduction in chip size and spacing presents significant technical challenges for LED electrodes and wire bonding. Currently, conventional LEDs utilize flip-chip electrode structures combined with bonding technology.

[0043] While flip-chip electrode structures offer high light extraction efficiency, the risk of short circuits increases with smaller chip sizes and the decreasing difficulty of wire bonding and LED spacing, leading to reduced LED luminous efficiency and reliability.

[0044] The applicant's research has discovered a structure for a flip chip, such as Figure 1 As shown, the chip includes a transparent substrate 9, a buffer layer 8, a first type semiconductor layer 7, an active layer 6, a second type semiconductor layer 5, a reflector 4, and a protective layer 3 stacked sequentially. The first electrode 1 and the second electrode 2 are located on the side of the protective layer 3 away from the reflector 4. The first electrode 1 is connected to the first type semiconductor layer 7 through a first conductive channel 10, and the second electrode 2 is connected to the second type semiconductor layer 5 through a second conductive channel 12. An insulating layer is provided on the sidewall of the first conductive channel 10. Due to the small chip size, the risk of short circuit between the adjacent first electrode 1 and second electrode 2 is increased.

[0045] The first type semiconductor layer 7 and the second type semiconductor layer 5 can be N-type semiconductor layer and P-type semiconductor layer, respectively, or they can be P-type semiconductor layer and N-type semiconductor layer, respectively. The first electrode 1 and the second electrode 2 can be anode and cathode, respectively, or they can be cathode and anode, respectively.

[0046] To address the above technical problems, this application provides a chip structure comprising: an epitaxial structure, which includes a first type semiconductor layer, an active layer, a second type semiconductor layer, and a transparent conductive layer stacked sequentially; a first electrode and a second electrode disposed on the side of the first type semiconductor layer away from the active layer; the first electrode being connected to the first type semiconductor layer; and the second electrode being connected to the transparent conductive layer; and an insulating structure being disposed between the first electrode and the second electrode in a direction parallel to the surface of the first type semiconductor layer to insulate the first electrode from the second electrode. By providing the insulating structure, the risk of short circuits in the chip electrodes can be reduced, thereby improving the reliability of the chip.

[0047] Exemplary Structure

[0048] See Figure 2 As shown, a chip structure provided in an embodiment of this application includes:

[0049] The epitaxial structure includes a first type semiconductor layer 7, an active layer 6, a second type semiconductor layer 5, and a transparent conductive layer 25 stacked sequentially. A first electrode 1 and a second electrode 2 are disposed on the side of the first type semiconductor layer 7 away from the active layer 6. The first electrode 1 is connected to the first type semiconductor layer 7, and the second electrode 2 is connected to the transparent conductive layer 25. An insulating structure is disposed between the first electrode 1 and the second electrode 2 in a direction parallel to the surface of the first type semiconductor layer 7 to insulate the first electrode 1 and the second electrode 2.

[0050] Specifically, the first electrode 1 and the second electrode 2 can be the anode and the cathode, respectively, or the first electrode 1 and the second electrode 2 can be the cathode and the anode, respectively. In the direction perpendicular to the surface of the first type semiconductor layer 7, the transparent conductive layer 25 is provided with a second type semiconductor layer 5 on the side close to the first type semiconductor layer 7.

[0051] It should be noted that the first type semiconductor layer 7 and the second type semiconductor layer 5 can be N-type conductive layer and P-type conductive layer, respectively, or they can be P-type conductive layer and N-type conductive layer, respectively. The embodiments of this application are not specifically limited here, and the specific settings can be made by those skilled in the art according to the actual situation.

[0052] In one possible implementation, see Figure 2 As shown, the insulating structure provided in this application embodiment may include a first transparent substrate 23, a reflector 4, and a total insulating layer stacked together. Figure 2In the process, the first transparent substrate 23 is in contact with the reflector 4. Specifically, the material of the first transparent substrate 23 can be a sapphire substrate, or it can be a glass, transparent ceramic, or transparent plastic, etc. The total insulating layer includes a first insulating layer 21 and a second insulating layer 22, thereby achieving insulation isolation between the first electrode 1 and the second electrode 2 through the first transparent substrate 23, the reflector 4 and the total insulating layer.

[0053] At the same time, due to Figure 2 A reflector 4 is installed in the middle. The reflector 4 can reflect the light emitted by the chip, thereby improving the light output efficiency. Figure 2 The structure forms an ODR (omnidirectional reflector) structure, which can effectively improve the light output efficiency.

[0054] In one possible implementation, the first electrode 1 can be connected to the first type semiconductor layer 7 through the first conductive channel 10, and the second electrode 2 can be connected to the transparent conductive layer 25 through the second conductive channel 12. The sidewalls of the first conductive channel 10 and / or the second conductive channel 12 are provided with an isolation layer 13.

[0055] For example, see Figure 2 As shown, an isolation layer 13 can be provided on the side wall of the second conductive channel 12. The isolation layer 13 can effectively isolate the second conductive channel 12 from other surrounding structures and prevent short circuits from occurring.

[0056] In one possible implementation, see Figure 2 As shown, the first transparent substrate 23 can be located on the side of the first electrode 1 away from the second electrode 2, and on the side of the second electrode 2 away from the first electrode 1, that is, it can be located on both sides of the chip structure, so as to avoid interference from other chips to this chip and reduce the risk of short circuit.

[0057] Specifically, in order to realize that a first transparent substrate 23 is provided between the first electrode 1 and the second electrode 2, and the first transparent substrate 23 can be located on the side of the first electrode 1 away from the second electrode 2 and on the side of the second electrode 2 away from the first electrode 1, a whole transparent substrate can be used and then a groove is cut to form the first transparent substrate 23.

[0058] In one possible implementation, see Figure 2 As shown, in order to effectively avoid interference from other chips and reduce the risk of short circuit, the surface of the first transparent substrate 23 located on the side of the first electrode 1 away from the second electrode 2 and the side of the second electrode 2 away from the first electrode 1 away from the first electrode 1, away from the first semiconductor layer 7, extends beyond the surfaces of the first electrode 1 and the second electrode 2 away from the first semiconductor layer 7. This can effectively block interference from other chips and reduce the risk of short circuit.

[0059] In one possible implementation, in the direction perpendicular to the surface of the first type semiconductor layer 7, i.e. Figure 2 In the Y direction, the second insulating layer 22 can be located on the side of the first insulating layer 21 away from the reflector 4; in the direction parallel to the surface of the first semiconductor layer 7, i.e. Figure 2 In the X direction, the first insulating layer 21 can be located between the first conductive channel 10 and the second conductive channel 12, so as to achieve omnidirectional isolation between the first electrode 1 and the second electrode 2 through the first insulating layer 21 and the second insulating layer 22.

[0060] Furthermore, the surface of the second insulating layer 22 away from the first semiconductor layer 7 extends beyond the surfaces of the first electrode 1 and the second electrode 2 away from the first semiconductor layer 7, thereby ensuring insulation between the first electrode 1 and the second electrode 2 and acting as a barrier to prevent electrical contact between the first electrode 1 and the second electrode 2.

[0061] In one possible implementation, see Figure 3 As shown, the insulating structure provided in this application embodiment may include a second transparent substrate 31 and an insulating Bragg reflective layer 30 stacked together. Figure 3 In the middle, the surface of the second transparent substrate 31 is in contact with the insulating Bragg reflection layer 30, which is also called a distributed Bragg reflection (DBR).

[0062] The insulating Bragg reflector layer 30 serves to both insulate and isolate the first electrode 1 and the second electrode 2, reducing the risk of short circuits in the chip, and also reflects light, effectively improving the light output efficiency of the chip.

[0063] Similarly, with Figure 2 Similarly, in one possible implementation, the first electrode 1 can be connected to the first type semiconductor layer 7 through the first conductive channel 10, and the second electrode 2 can be connected to the transparent conductive layer 25 through the second conductive channel 12. The sidewalls of the first conductive channel 10 and / or the second conductive channel 12 are provided with an isolation layer 13.

[0064] For example, see Figure 3 As shown, an isolation layer 13 can be provided on the side wall of the second conductive channel 12. The isolation layer 13 can effectively isolate the second conductive channel 12 from other surrounding structures and prevent short circuits from occurring.

[0065] In one possible implementation, see Figure 3As shown, the second transparent substrate 31 can be located on the side of the first electrode 1 away from the second electrode 2, and on the side of the second electrode 2 away from the first electrode 1, that is, it can be located on both sides of the chip structure to avoid interference from other chips to this chip and reduce the risk of short circuit.

[0066] Specifically, in order to realize that a second transparent substrate 31 is provided between the first electrode 1 and the second electrode 2, and the second transparent substrate 31 can be located on the side of the first electrode 1 away from the second electrode 2 and on the side of the second electrode 2 away from the first electrode 1, a single transparent substrate can be used and then a groove is cut to form the second transparent substrate 31.

[0067] In one possible implementation, see Figure 3 As shown, in order to effectively avoid interference from other chips and reduce the risk of short circuit, the surface of the second transparent substrate 31 located on the side of the first electrode 1 away from the second electrode 2 and the side of the second electrode 2 away from the first electrode 1 away from the first electrode 1, away from the first semiconductor layer 7, extends beyond the surfaces of the first electrode 1 and the second electrode 2 away from the first semiconductor layer 7. This can effectively block interference from other chips and reduce the risk of short circuit.

[0068] In one possible implementation, in the direction perpendicular to the surface of the first type semiconductor layer 7, i.e. Figure 3 In the Y direction, the surface of the insulating Bragg reflector layer 30 on the side away from the first type semiconductor layer 7 extends beyond the surfaces of the first electrode 1 and the second electrode 2 on the side away from the first type semiconductor layer 7, thereby ensuring insulation between the first electrode 1 and the second electrode 2 and playing a blocking role to avoid electrical contact between the first electrode 1 and the second electrode 2.

[0069] In one possible implementation, see Figure 4 As shown, the insulating structure provided in this application embodiment may include a third substrate 40, thereby achieving insulation isolation between the first electrode 1 and the second electrode 2 through the third substrate 40.

[0070] Optionally, the material of the third substrate 40 can be a sapphire substrate, or it can be a glass, transparent ceramic, or transparent plastic, or a polymer resin, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0071] Similarly, in one possible implementation, the first electrode 1 can be connected to the first type semiconductor layer 7 through the first conductive channel 10, and the second electrode 2 can be connected to the transparent conductive layer 25 through the second conductive channel 12. The sidewalls of the first conductive channel 10 and / or the second conductive channel 12 are provided with an isolation layer 13.

[0072] For example, see Figure 4 As shown, an isolation layer 13 can be provided on the side wall of the second conductive channel 12. The isolation layer 13 can effectively isolate the second conductive channel 12 from other surrounding structures and prevent short circuits from occurring.

[0073] In one possible implementation, see Figure 4 As shown, the third substrate 40 can be located on the side of the first electrode 1 away from the second electrode 2, and on the side of the second electrode 2 away from the first electrode 1, that is, it can be located on both sides of the chip structure to avoid interference from other chips to this chip and reduce the risk of short circuit.

[0074] Specifically, in order to realize that a third substrate 40 is provided between the first electrode 1 and the second electrode 2, and the third substrate 40 can be located on the side of the first electrode 1 away from the second electrode 2 and on the side of the second electrode 2 away from the first electrode 1, a whole transparent substrate can be used and then a groove is cut to form the third substrate 40.

[0075] In one possible implementation, see Figure 4As shown, in order to effectively avoid interference from other chips and reduce the risk of short circuit, the surface of the third substrate 40 located on the side of the first electrode 1 away from the second electrode 2 and the side of the second electrode 2 away from the first electrode 1 away from the first electrode 1, away from the first semiconductor layer 7, extends beyond the surfaces of the first electrode 1 and the second electrode 2 away from the first semiconductor layer 7. This can effectively block interference from other chips and reduce the risk of short circuit.

[0076] In one possible implementation, the surface of the third substrate 40 on the side away from the first semiconductor layer 7 extends beyond the surfaces of the first electrode 1 and the second electrode 2 on the side away from the first semiconductor layer 7, thereby ensuring insulation between the first electrode 1 and the second electrode 2 and acting as a barrier to prevent electrical contact between the first electrode 1 and the second electrode 2.

[0077] In one possible implementation, see Figure 2 , Figure 3 and Figure 4 As shown, in the direction perpendicular to the surface of the first type semiconductor layer 7, that is, perpendicular to the first type semiconductor layer 7 and the second type semiconductor layer 5, the chip structure provided in this application embodiment may further include a buffer layer 8 between the first type semiconductor layer 7 and the substrate. The buffer layer 8 serves as a transition layer, and the material may include materials such as gallium nitride and lithium nitride. An active layer 6 may be included between the first type semiconductor layer 7 and the second type semiconductor layer 5. A transparent conductive layer 25 may be provided on the side of the second type semiconductor layer 5 away from the active layer 6 so that light emitted by the chip can pass through. The material of the transparent conductive layer 25 may include materials such as ITO (Indium tin oxide). In addition, in order to protect the chip and isolate the internal structure of the chip from external water and oxygen, a protective layer 3 may be provided on the side of the transparent conductive layer 25 away from the second type semiconductor layer 5 to protect the chip.

[0078] In one possible implementation, see Figure 2 , Figure 3 and Figure 4 As shown in the figure, the thicknesses of the first transparent substrate 23, the second transparent substrate 31, and the third substrate 40 can be greater than 15 μm and less than 50 μm; the height difference of the grooves in the first transparent substrate 23, the second transparent substrate 31, and the third substrate 40 can be greater than 2 μm and less than 20 μm; and the area of ​​the grooves in the first transparent substrate 23, the second transparent substrate 31, and the third substrate 40 accounts for no more than 90% of the chip area. By setting the first transparent substrate 23, the second transparent substrate 31, and the third substrate 40, the bonding stability of the chip is also increased, making it less prone to tipping over when the chip is bonded to the circuit carrier.

[0079] This application provides a chip structure comprising an epitaxial structure, which includes a first type semiconductor layer, an active layer, a second type semiconductor layer, and a transparent conductive layer stacked sequentially. A first electrode and a second electrode are disposed on the side of the first type semiconductor layer away from the active layer. The first electrode is connected to the first type semiconductor layer, and the second electrode is connected to the transparent conductive layer. An insulating structure is disposed between the first electrode and the second electrode in a direction parallel to the surface of the first type semiconductor layer to insulate them. By providing the insulating structure, the risk of short circuits in the chip electrodes can be reduced, improving the reliability of the chip.

[0080] Exemplary methods

[0081] See Figure 5 The diagram shown is a flowchart of a chip structure manufacturing method provided in an embodiment of this application, including:

[0082] S101: Form an epitaxial structure, the epitaxial structure comprising a first type semiconductor layer 7, an active layer 6, a second type semiconductor layer 5 and a transparent conductive layer 25 stacked sequentially.

[0083] S102: A first electrode 1 and a second electrode 2 are formed on the side of the first type semiconductor layer 7 away from the active layer 6.

[0084] S103: An insulating structure is formed between the first electrode 1 and the second electrode 2 in a direction parallel to the surface of the first type semiconductor layer 7, so as to insulate the first electrode 1 and the second electrode 2.

[0085] Specifically, in one possible implementation, for Figure 2 The chip structure shown can be manufactured using the following methods:

[0086] 1. A buffer layer 24, a first type semiconductor layer 7, an active layer 6, and a second type semiconductor layer 5 are sequentially epitaxially formed on the upper surface of the first transparent substrate 23;

[0087] 2. A transparent conductive layer 25 and a protective layer 3 are deposited on the surface of the second type semiconductor layer 5 by vapor deposition;

[0088] 3. A groove is formed on the back side of the first transparent substrate 23 using photolithography and etching techniques;

[0089] 4. The reflector 4 and the first insulating layer 21 are sequentially vapor-deposited on the groove;

[0090] 5. A first conductive channel 10 and a second conductive channel 12 are formed on the first insulating layer 21 using photolithography and etching techniques;

[0091] 6. An isolation layer 13 is provided on the side wall of the second conductive channel 12;

[0092] 7. A first electrode 1 and a second electrode 2 are formed on the first insulating layer 21, and the first electrode 1 is electrically connected to the first type semiconductor layer 7 through the metal filled in the first conductive channel 10, and the second electrode 2 is electrically connected to the transparent conductive layer 25 through the metal filled in the second conductive channel 12.

[0093] 8. A second insulating layer 22 is deposited on the surface of the non-electrode portion of the first insulating layer 21 by vapor deposition;

[0094] 9. Cut and separate to form independent chips. Optionally, the chips provided in this application embodiment may include MiniLED (submillimeter-sized light-emitting diode chip).

[0095] Specifically, in one possible implementation, for Figure 3 The chip structure shown can be manufactured using the following methods:

[0096] 1. A buffer layer 24, a first type semiconductor layer 7, an active layer 6, and a second type semiconductor layer 5 are sequentially epitaxially formed on the upper surface of the second transparent substrate 31;

[0097] 2. A transparent conductive layer 25 and a protective layer 3 are deposited on the surface of the second type semiconductor layer 5 by vapor deposition;

[0098] 3. A groove is formed on the back side of the first transparent substrate 23 using photolithography and etching techniques;

[0099] 4. An insulating Bragg reflective layer of 30 mm is deposited on the groove;

[0100] 5. The first and second electrode fabrication areas, the first conductive channel 10 and the second conductive channel 12 are formed on the insulating Bragg reflective layer 30 using photolithography and etching techniques;

[0101] 6. An isolation layer 13 is provided on the side wall of the second conductive channel 12;

[0102] 7. A first electrode 1 and a second electrode 2 are formed on the first and second electrode fabrication areas of the insulating Bragg reflector layer 30, respectively. The first electrode 1 is electrically connected to the first type semiconductor layer 7 through the metal filled in the first conductive channel 10, and the second electrode 2 is electrically connected to the transparent conductive layer 25 through the metal filled in the second conductive channel 12.

[0103] 8. Cut and separate to form independent chips. Optionally, the chips provided in this application embodiment may include MiniLED (submillimeter-sized light-emitting diode chip).

[0104] Specifically, in one possible implementation, for Figure 4The chip structure shown can be manufactured using the following methods:

[0105] 1. A buffer layer 24, a first-type semiconductor layer 7, an active layer 6, and a second-type semiconductor layer 5 are sequentially epitaxially formed on the upper surface of the third substrate 40;

[0106] 2. A transparent conductive layer 25 and a protective layer 3 are deposited on the surface of the second type semiconductor layer 5 by vapor deposition;

[0107] 3. A groove is formed on the back side of the third substrate 40 using photolithography and etching techniques;

[0108] 4. The first and second electrode fabrication areas, the first conductive channel 10 and the second conductive channel 12 are formed on the surface of the groove of the third substrate 40 using photolithography.

[0109] 5. An isolation layer 13 is provided on the side wall of the second conductive channel 12;

[0110] 7. A first electrode 1 and a second electrode 2 are formed on the third substrate 40, and the first electrode 1 is electrically connected to the first type semiconductor layer 7 through the metal filled in the first conductive channel 10, and the second electrode 2 is electrically connected to the transparent conductive layer 25 through the metal filled in the second conductive channel 12.

[0111] 8. Cut and separate to form independent chips. Optionally, the chips provided in this application embodiment may include MiniLED (submillimeter-sized light-emitting diode chip).

[0112] This application provides a method for manufacturing a chip structure. The chip structure formed by this method includes an epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer, and a transparent conductive layer stacked sequentially. A first electrode and a second electrode are disposed on the side of the first type semiconductor layer away from the active layer. The first electrode is connected to the first type semiconductor layer, and the second electrode is connected to the transparent conductive layer. An insulating structure is disposed between the first electrode and the second electrode in a direction parallel to the surface of the first type semiconductor layer to insulate the first electrode from the second electrode. By providing the insulating structure, the risk of short circuits in the chip electrodes can be reduced, and the reliability of the chip can be improved.

[0113] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so they are described more simply; relevant parts can be referred to the descriptions of the method embodiments.

[0114] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A chip structure, characterized in that, include: An epitaxial structure, the epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer and a transparent conductive layer stacked sequentially; A first electrode and a second electrode are disposed on the side of the first type semiconductor layer away from the active layer; The first electrode is connected to the first type of semiconductor layer, and the second electrode is connected to the transparent conductive layer; The first electrode is connected to the first type of semiconductor layer through a first conductive channel; the second electrode is connected to the transparent conductive layer through a second conductive channel; and an isolation layer is provided on the sidewall of the first conductive channel and / or the second conductive channel. An insulating structure is provided between the first electrode and the second electrode in a direction parallel to the surface of the first type of semiconductor layer, so as to insulate the first electrode and the second electrode. The insulating structure includes a first transparent substrate, a reflector, a first insulating layer, and a second insulating layer stacked together. In a direction perpendicular to the surface of the first semiconductor layer, the second insulating layer is located on the side of the first insulating layer away from the reflector; In a direction parallel to the surface of the first type of semiconductor layer, the first insulating layer is located between the first conductive channel and the second conductive channel; The surface of the second insulating layer away from the first semiconductor layer extends beyond the surfaces of the first electrode and the second electrode away from the first semiconductor layer; The surface of the first transparent substrate located on the side of the first electrode away from the second electrode, and the surface of the second electrode located on the side of the second electrode away from the first electrode away from the first electrode, extends beyond the surfaces of the first electrode and the second electrode on the side of the second electrode away from the first electrode.

2. A method for manufacturing a chip structure, characterized in that, include: An epitaxial structure is formed, the epitaxial structure comprising a first type semiconductor layer, an active layer, a second type semiconductor layer and a transparent conductive layer stacked sequentially; A first electrode and a second electrode are formed on the side of the first type semiconductor layer away from the active layer; the first electrode is connected to the first type semiconductor layer, and the second electrode is connected to the transparent conductive layer. The first electrode is connected to the first type of semiconductor layer through a first conductive channel; the second electrode is connected to the transparent conductive layer through a second conductive channel; and an isolation layer is provided on the sidewall of the first conductive channel and / or the second conductive channel. An insulating structure is formed between the first electrode and the second electrode in a direction parallel to the surface of the first semiconductor layer to insulate the first electrode from the second electrode. The insulating structure includes a first transparent substrate, a mirror, a first insulating layer, and a second insulating layer stacked together. In a direction perpendicular to the surface of the first semiconductor layer, the second insulating layer is located on the side of the first insulating layer away from the mirror. In a direction parallel to the surface of the first semiconductor layer, the first insulating layer is located between the first conductive channel and the second conductive channel. The surface of the second insulating layer on the side away from the first semiconductor layer extends beyond the surfaces of the first electrode and the second electrode on the side away from the first semiconductor layer. The surface of the first transparent substrate on the side of the first transparent substrate away from the first semiconductor layer, which is located on the side of the first electrode away from the second electrode and the side of the second electrode away from the first electrode, extends beyond the surfaces of the first electrode and the second electrode on the side away from the first semiconductor layer.

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