An adaptive DC filtering circuit based on synchronous sampling and its DC filtering method

Abstract

An adaptive DC filtering circuit based on synchronous sampling and its DC filtering method, comprising an AC sampling circuit, a device power supply circuit, a DC reference circuit, a signal processing unit and a balancing circuit. The device power supply circuit is used to convert the power supply voltage into a DC voltage. The device power supply circuit is connected to the DC reference circuit and, through the balancing circuit, converts the DC voltage generated by the device power supply circuit into two identical DC reference voltages. One of the DC reference voltages is directly input into the signal processing unit, and the other DC reference voltage is superimposed on the voltage signal output by the AC sampling circuit as a DC bias signal and input into the signal processing unit. The signal processing unit synchronously samples the two input signals and performs a subtraction operation. The present invention realizes the real-time filtering function by using digital difference, has a short sampling period, is not easily affected by spectral leakage, has high precision and does not affect the processing of subsequent software algorithms.

Description

Technical Field

[0001] The present invention relates to analysis and measurement control technologies in the technical field of instruments and meters, and particularly to an adaptive DC filtering circuit based on synchronous sampling and a DC filtering method thereof. Background Art

[0002] Since the DC component is an important factor affecting measurement accuracy, currently in the power industry, DC filtering (reference DC and transient DC) in power sampling is mainly software algorithms, and the full-wave Fourier algorithm is mainly used. However, the full-wave Fourier algorithm has the following disadvantages: First, the CPU load for executing the algorithm is large and the sampling period is long; second, it is easily affected by spectral leakage. When the frequency fluctuates, spectral leakage will surely affect the DC filtering effect (when not hardware frequency tracking), and there is at least a one-week delay for hardware frequency tracking, especially when the full-wave measurement algorithm has a greater impact on high-precision sampling; third, even if the improved full-wave Fourier algorithm (interpolation after estimation calculation) is used, although the accuracy is improved, there are errors in real-time performance and transient DC filtering. Summary of the Invention

[0003] The purpose of the present invention is to overcome the defects of the prior art and provide an adaptive DC filtering circuit based on synchronous sampling and a DC filtering method thereof with real-time performance and relatively high accuracy.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] An adaptive DC filtering circuit based on synchronous sampling includes an AC sampling circuit, a device power supply circuit, a DC reference circuit, a balancing circuit, and a signal processing unit. The AC sampling circuit converts the collected current and voltage into voltage signals. The device power supply circuit is used to convert the power supply voltage into a DC voltage. The DC reference circuit is connected to the device power supply circuit, and the DC reference circuit is connected to a balancing circuit. The DC voltage is converted into two identical DC reference voltages through the DC reference circuit and the balancing circuit. The balancing circuit is used to keep the voltage values of the two voltage outputs equal. One of the DC reference voltages is directly input to the signal processing unit, and the other DC reference voltage is connected to the AC sampling circuit and is input to the signal processing unit after superimposing a DC bias signal on the voltage signal. The signal processing unit synchronously samples the two input signals and performs a subtraction operation.

[0006] Further, the signal processing unit is a microprocessor with an AD sampling module built therein.

[0007] Further, the AC sampling circuit includes a voltage transformer, a voltage-dividing resistor, and a filtering circuit. The AC sampling circuit collects AC signals through the voltage transformer, and the AC signals are converted into voltage signals after passing through the voltage-dividing resistor and the filtering circuit.

[0008] Further, the AC sampling circuit includes a voltage transformer, resistor R1, resistor R2, capacitor C1, capacitor C2, capacitor C3, and capacitor C4. Resistor R1 and capacitor C1 are both connected in parallel with the voltage transformer. One end of capacitor C1 and one end of capacitor C2 are respectively connected to both ends of resistor R1. The other end of capacitor C1 and the other end of capacitor C2 are connected to the power ground. One end of capacitor C4 is connected to one end of capacitor C3 through resistor R2, and one end of capacitor C4 is connected to the signal processing unit. The other end of capacitor C4 is connected to the other end of capacitor C3. The balance circuit is connected to the other end of capacitor C4.

[0009] Further, the DC reference circuit includes two reference voltage chips connected in parallel. The two reference voltage chips are connected to the device power supply circuit and output two identical DC reference voltages after connecting to the balance circuit.

[0010] Further, the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, capacitor C5, capacitor C6, capacitor C7, capacitor C8, and capacitor C9. The balance circuit includes resistor R9, resistor R10, and resistor R11.

[0011] The first V- pin of the first reference voltage chip and the TV pin of the second reference voltage chip are connected to the device power supply circuit. Both ends of resistor R3 are respectively connected to the first V- pin and the second V- pin of the first reference voltage chip. Both ends of resistor R4 are respectively connected to the TV pin and the VS pin of the second reference voltage chip. One end of capacitor C5 is connected to the first V- pin of the first reference voltage chip and the TV pin of the second reference voltage chip, and the other end of capacitor C5 is connected to the signal ground. One end of resistor R5 is connected to the NC pin of the first reference voltage chip. One end of capacitor C6, capacitor C7, and resistor R7 is connected to the fourth V- pin of the first reference voltage chip. The third V- pin of the first reference voltage chip is connected to the fourth V- pin. The other ends of resistor R5, capacitor C6, and capacitor C7 are connected to the signal ground. One end of resistor R11 is connected to the other end of resistor R7 and one end of resistor R9, and one end of resistor R11 is connected to the AC sampling circuit. One end of resistor R6 is connected to the TP pin of the second reference voltage chip. One end of capacitor C8 and capacitor C9 is connected to the OUTPUT pin of the second reference voltage chip. One end of resistor R8, the other end of resistor R6, the other end of capacitor C8, and the other end of capacitor C9 are connected together and connected to the signal ground. The other end of resistor R11 is connected to the other end of resistor R8 and one end of resistor R10. The other end of resistor R11 is connected to the signal processing unit. The other ends of resistor R9 and resistor R10 are connected and connected to the signal ground.

[0012] Further, the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a diode D1, a diode D2 and a capacitor C5, and the balancing circuit includes a resistor R8, a resistor R9, a resistor R10 and a capacitor C10;

[0013] The V+ pins of the first reference voltage chip and the second reference voltage chip are connected to the device power supply circuit, the first V- pin and the second V- pin of the first reference voltage chip are connected together, one end of resistors R18 and R19 are connected to the R pin of the first reference voltage chip, the other end of resistors R18 and R19 are connected to the anode of diode D1, the third V- pin and the fourth V- pin of the first reference voltage chip are connected to the anode of diode D1, the cathode of diode D1 is connected to one end of resistor R7, one end of resistor R9 is connected to the other end of resistor R7, the first V- pin and the second V- pin of the second reference voltage chip are connected, one end of resistors R20 and R21 are connected to the R pin of the second reference voltage chip, and the other end of resistor R20 is connected to The cathode of diode D2 is connected, the other end of resistor R21 is connected to the anode of diode D2, the third V-pin and the fourth V-pin of the second reference voltage chip are connected to the anode of diode D2, one end of resistor R8 is connected to the cathode of diode D2, the other end of resistor R8 is connected to one end of resistor R10, one end of capacitor C5 is connected to the device power supply circuit, the other end of capacitor C5, the other end of resistor R9 and the other end of resistor R10 are connected to the signal ground; one end of resistor R11 is connected to one end of resistor R9 and to the AC sampling circuit, the other end of resistor R11 is connected to one end of resistor R10 and to the signal processing unit, one end of capacitor C10 is connected to the other end of resistor R11, and the other end of capacitor C10 is connected to the power supply ground.

[0014] Further, the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8 and a capacitor C9, the VS pin of the first reference voltage chip and the TV pin of the second reference voltage chip are connected to the device power supply circuit, the two ends of the resistor R3 are respectively connected to the VS pin and the SLEEP pin of the first reference voltage chip, the two ends of the resistor R4 are respectively connected to the TV pin and the VS pin of the second reference voltage chip, one end of the capacitor C5 is connected to the VS pin of the first reference voltage chip and the TV pin of the second reference voltage chip, the other end of the capacitor C5 is connected to the signal ground, and one end of the resistor R5 is connected to the first reference voltage chip. The TP pin of the quasi-voltage chip, one end of the capacitor C6, the capacitor C7 and the resistor R7 are connected to the OUTPUT pin of the first reference voltage chip, the other ends of the resistor R5, the capacitor C6 and the capacitor C7 are connected to the signal ground, the other end of the resistor R7 is connected to one end of the resistor R9, and one end of the resistor R9 is connected to the AC sampling circuit, one end of the resistor R6 is connected to the TP pin of the second reference voltage chip, one end of the capacitor C8 and the capacitor C9 are connected to the OUTPUT pin of the second reference voltage chip, one end of the resistor R8, the other end of the resistor R6, the other end of the capacitor C8 and the other end of the capacitor C9 are connected together and connected to the signal ground, the other end of the resistor R8 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the other end of the resistor R9 and connected to the signal ground.

[0015] Further, the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a diode D1, a diode D2 and a capacitor C5, the V+ pins of the first reference voltage chip and the second reference voltage chip are connected to the device power supply circuit, the first V- pin and the second V- pin of the first reference voltage chip are connected together, one end of the resistor R18 and the resistor R19 are connected to the R pin of the first reference voltage chip, the other end of the resistor R18 and the resistor R19 are connected to the anode of the diode D1, the third V- pin and the fourth V- pin of the first reference voltage chip are connected to the anode of the diode D1, and the The cathode is connected to one end of resistor R7, one end of resistor R9 is connected to the other end of resistor R7, the first V-pin of the second reference voltage chip is connected to the second V-pin, one end of resistor R20 and resistor R21 are connected to the R pin of the second reference voltage chip, the other end of resistor R20 is connected to the cathode of diode D2, the other end of resistor R21 is connected to the anode of diode D2, the third V-pin and the fourth V-pin of the second reference voltage chip are connected to the anode of diode D2, one end of resistor R8 is connected to the cathode of diode D2, the other end of resistor R8 is connected to one end of resistor R10, one end of capacitor C5 is connected to the device power supply circuit, and the other end of capacitor C5, the other end of resistor R9 and the other end of resistor R10 are connected to the signal ground.

[0016] Further, the balancing circuit includes a resistor R17, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a first comparator, a second comparator, a MOS tube Q1 and a MOS tube Q2, one end of the resistor R17 and the resistor R12 are respectively connected to the DC reference circuit, the other end of the resistor R17 and the resistor R12 are respectively connected to the positive input end and the reverse input end of the first comparator, one end of the resistor R13 and the gate of the MOS tube Q1 are connected to the output end of the first comparator, and the drain and source of the MOS tube Q1 are respectively connected to the resistor R17 and the resistor R13. The MOS tube Q2 is connected to one end of the resistor R17 and the resistor R12, the drain and the source of the MOS tube Q2 are respectively connected to one end of the resistor R17 and the resistor R12, the gate of the MOS tube Q2 and one end of the resistor R14 are connected to the output end of the second comparator, the resistor R15 and one end of the resistor R16 are respectively connected to the reverse input end and the forward input end of the second comparator, the other end of the resistor R15 is connected to one end of the resistor R17, the other end of the resistor R16 is connected to one end of the resistor R12, and the other end of the resistor R16 is connected to the signal processing unit, and the other ends of the resistors R13 and R14 are connected to the signal ground.

[0017] A DC filtering method based on the adaptive DC filtering circuit based on synchronous sampling as described above comprises the following steps:

[0018] Step S1: The AC sampling circuit converts the collected current and voltage into a voltage signal;

[0019] Step S2: the power supply circuit of the device converts the power supply voltage into a DC voltage, and the DC reference circuit converts the DC voltage into two identical DC reference voltages at the same time, and the two DC reference voltages are instantaneously consistent in voltage through a balancing circuit, one of which is superimposed on the voltage signal converted by the AC sampling circuit as a DC bias signal to form a sinusoidal voltage signal that can be collected by the signal processing unit, and the other DC reference voltage is directly input into the signal processing unit as a DC reference voltage signal;

[0020] Step S3: the signal processing unit simultaneously collects the sinusoidal voltage signal and the DC reference voltage signal, and directly subtracts the synchronously sampled DC reference discrete signal value from each point of the sampled current and voltage discrete signal value.

[0021] Preferably, the signal processing unit is a microprocessor with a built-in AD sampling module, which implements software calculation to directly subtract the synchronously sampled DC reference discrete signal value from each point of the sampled current and voltage discrete signal value; or, the signal processing unit is an FPGA, which implements filtering to directly subtract the synchronously sampled DC reference discrete signal value from each point of the sampled current and voltage discrete signal value through the differential circuit of the FPGA.

[0022] The adaptive DC filtering circuit and DC filtering method based on synchronous sampling of the present invention processes each sampling point once, and the balancing circuit can ensure the balance of sampling at all times, thereby achieving consistency of input signals, and realizing real-time filtering function by using digital differential. It does not need to wait for a sampling cycle of one week before calculating like the existing Fourier algorithm, so it is not easily affected by spectrum leakage, has high accuracy and does not affect the processing of later software algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a principle diagram of an adaptive direct current filtering circuit based on synchronous sampling of the present invention;

[0024] Figure 2 It is a circuit diagram of an adaptive direct current filtering circuit based on synchronous sampling of the present invention (first embodiment);

[0025] Figure 3 is a circuit diagram of an adaptive direct current filtering circuit based on synchronous sampling of the present invention (second embodiment);

[0026] Figure 4 is a circuit diagram of an adaptive direct current filtering circuit based on synchronous sampling of the present invention (third embodiment);

[0027] Figure 5 It is a circuit diagram of an adaptive DC filtering circuit based on synchronous sampling of the present invention (fourth embodiment). DETAILED DESCRIPTION

[0028] The following is combined with Figures 1 to 5 The given embodiments further illustrate the specific implementation of the adaptive DC filtering circuit based on synchronous sampling and the DC filtering method thereof of the present invention. The adaptive DC filtering circuit based on synchronous sampling and the DC filtering method thereof of the present invention are not limited to the description of the following embodiments.

[0029] An adaptive direct current filtering circuit based on synchronous sampling includes an AC sampling circuit, a device power supply circuit, a DC reference circuit, a balancing circuit and a signal processing unit. The AC sampling circuit converts the collected current voltage into a voltage signal. The device power supply circuit is used to convert the power supply voltage into a DC voltage. The DC reference circuit is connected to the device power supply circuit. The DC reference circuit is connected to a balancing circuit. The DC voltage is converted into two identical DC reference voltages through the DC reference circuit and the balancing circuit. The balancing circuit is used to keep the voltage values ​​of the two voltage outputs equal. One DC reference voltage is directly input into the signal processing unit, and the other DC reference voltage is connected to the AC sampling circuit and input into the signal processing unit after a DC bias signal is superimposed on the voltage signal. The signal processing unit synchronously collects the signals of the two inputs and performs a difference operation.

[0030] The adaptive direct filter circuit based on synchronous sampling of the present invention processes each sampling point once during sampling, and the balancing circuit can ensure the balance of sampling at all times, thereby achieving consistency of the input signal, and realizing real-time filtering function by using digital differential, and does not need to wait for a sampling cycle of one week before calculation like the existing Fourier algorithm, so that it is not easily affected by spectrum leakage, has high accuracy and does not affect the processing of the later software algorithm.

[0031] Combination Figures 1-2A first embodiment of an adaptive DC filtering circuit based on synchronous sampling is provided, wherein the adaptive DC filtering circuit based on synchronous sampling includes an AC sampling circuit, a device power supply circuit, a DC reference circuit, a balancing circuit and a signal processing unit, wherein the AC sampling circuit preferably includes a voltage transformer, a voltage-dividing resistor and a filtering circuit, wherein the AC sampling circuit collects an AC signal through a voltage transformer, and the AC signal is converted into a voltage signal after passing through a voltage-dividing resistor and a filtering circuit; wherein the device power supply circuit is used to convert a power supply voltage into a DC voltage, and typically converts a 220V AC power supply or a DC power supply into a 5V DC voltage, wherein a DC reference circuit is connected to the device power supply circuit, and wherein the DC reference circuit is connected to a balancing circuit, and wherein the DC voltage is converted into two identical DC reference voltages through the DC reference circuit and the balancing circuit, and typically the two DC reference voltages are 1.5V DC reference voltages. , one DC reference voltage is directly input into the signal processing unit, and the other DC reference voltage is connected to the AC sampling circuit. The DC reference voltage is superimposed on the voltage signal converted by the AC sampling circuit as a DC bias signal and input into the signal processing unit together. Due to the existence of the balancing circuit, the two DC reference voltages can maintain synchronous output after the power supply is disturbed and the sampling circuit is disturbed, that is, the balancing circuit can maintain the output of two voltages that are equal in real time. Regardless of whether the interference comes from the power supply or the environmental radiation, it is common mode interference. After synchronously collecting the signals of the two inputs, the signal processing unit can perform a simple difference operation to filter out the DC component. The signal processing unit is preferably a microprocessor with a built-in AD sampling module, such as an ARM chip, or the signal processing unit is an FPGA, and the DC component is filtered out through a hardware differential circuit. Of course, an external AD sampling module can also be used.

[0032] Combination Figure 2 A specific connection method of this embodiment is provided. The AC sampling circuit includes a voltage transformer, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4. The resistor R1 and the capacitor C3 are both connected in parallel with the voltage transformer. One end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the two ends of the resistor R1, and the other end of the capacitor C1 and the other end of the capacitor C2 are connected to the power ground. One end of the capacitor C4 is connected to one end of the capacitor C3 through the resistor R2, and one end of the capacitor C4 is connected to the signal processing unit, the other end of the capacitor C4 is connected to the other end of the capacitor C3, and the balancing circuit is connected to the other end of the capacitor C4.

[0033] The connection method of the DC reference circuit and the balancing circuit is as follows: Figure 2As shown, the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8 and a capacitor C9, and the balancing circuit includes a resistor R9, a resistor R10 and a resistor R11.

[0034] The first V-pin of the first reference voltage chip and the TV pin of the second reference voltage chip are connected to the device power supply circuit, the two ends of the resistor R3 are respectively connected to the first V-pin and the second V-pin of the first reference voltage chip, the two ends of the resistor R4 are respectively connected to the TV pin and the VS pin of the second reference voltage chip, one end of the capacitor C5 is connected to the first V-pin of the first reference voltage chip and the TV pin of the second reference voltage chip, the other end of the capacitor C5 is connected to the signal ground, one end of the resistor R5 is connected to the NC pin of the first reference voltage chip, the third V-pin of the first reference voltage chip is connected to the fourth V-pin, the capacitor C6, the capacitor C7 and one end of the resistor R7 are connected to the fourth V-pin of the first reference voltage chip, the resistor R5, the capacitor C6 and the other end of the capacitor C7 are connected to the signal ground, one end of the resistor R11 is connected to the other end of the resistor R7 and one end of the resistor R9, and one end of the resistor R11 is connected to the AC sampling circuit, and one end of the resistor R6 is connected to the second reference voltage chip. The TP pin of the voltage chip, one end of the capacitor C8 and the capacitor C9 are connected to the OUTPUT pin of the second reference voltage chip, one end of the resistor R8, the other end of the resistor R6, the other end of the capacitor C8 and the other end of the capacitor C9 are connected together and connected to the signal ground, the other end of the resistor R11 is connected to the other end of the resistor R8 and one end of the resistor R10, the other end of the resistor R11 is connected to the signal processing unit, the resistor R9 and the other end of the resistor R10 are connected and connected to the signal ground, wherein the resistor R9, the resistor R10 and the resistor R11 form a balanced circuit, and two identical DC reference voltages are formed by the DC reference circuit and the balanced circuit, wherein the other end of the capacitor C4 is used as a DC bias point, one DC reference voltage is connected to the AC sampling circuit through the capacitor C4, and is superimposed on the voltage signal converted by the AC sampling circuit as a DC bias signal to form a sinusoidal voltage signal that can be collected by the signal processing unit, and the other DC reference voltage is input into the signal processing unit through the other end of the resistor R11. The balancing principle is: based on Kirchhoff's current theorem, when resistance R11 is much smaller than resistance R9, and resistance R9 = resistance R10, under ideal conditions, when the upper loop (the upper end of resistance R9) has a current greater than resistance R10, the current flowing through is divided into two parts, one part passes through resistance R9 and returns to the negative end, and the other part passes through resistance R11 and resistance R10. Since resistance R11≈0, and resistance R9=resistance R10, the voltages at both ends must be equal.

[0035] Combination Figure 1 , 3 A connection method of a second embodiment is provided, which is the same as the connection method of the first embodiment. The AC sampling circuit includes a voltage transformer, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, and its connection method is the same as the first connection method.

[0036] The connection method of the DC reference circuit and the balancing circuit is as follows: Figure 3 As shown, the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R7, a resistor R8, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C5, a diode D1 and a diode D2, and the balancing circuit includes a resistor R9, a resistor R10, a resistor R11 and a capacitor C10.

[0037] The V+ pins of the first reference voltage chip and the second reference voltage chip are connected to the device power supply circuit, the first V- pin and the second V- pin of the first reference voltage chip are connected together, one end of the resistor R18 and the resistor R19 are connected to the R pin of the first reference voltage chip, the other end of the resistor R18 and the resistor R19 are connected to the anode of the diode D1, the anode of the diode D1 is respectively connected to the third V- pin and the fourth V- pin of the first reference voltage chip, the cathode of the diode D1 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R9 and the resistor R11, and one end of the resistor R11 is also used to connect to the AC sampling circuit, that is, connected to the other end of the capacitor C4; the first V- pin and the second V- pin of the second reference voltage chip are connected to Together, one end of resistor R20 and resistor R21 are respectively connected to the R pin of the second reference voltage chip, the other end of resistor R20 is connected to the cathode of diode D2, the third V-pin, the fourth V-pin of the second reference voltage chip and the other end of resistor R21 are connected to the anode of diode D2, one end of resistor R8 is connected to the cathode of diode D2, the other end of resistor R8 is connected to one end of resistor R10 and the other end of resistor R11, the other end of resistor R11 is also used to connect to the signal processing unit, one end of capacitor C5 is connected to the device power supply circuit, one end of capacitor C10 is connected to the signal processing unit, the other end of capacitor C5, the other end of resistor R9 and the other end of resistor R10 are connected to the signal ground, and the other end of capacitor C10 is connected to the power ground.

[0038] Combination Figure 1 , 4A third embodiment of an adaptive DC filtering circuit based on synchronous sampling is provided. The connection method of the AC sampling circuit in this embodiment is the same as that of the first and second embodiments. The DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8 and a capacitor C9. The VS pin of the first reference voltage chip and the TV pin of the second reference voltage chip are connected to the device power supply circuit, the two ends of the resistor R3 are respectively connected to the VS pin and the SLEEP pin of the first reference voltage chip, the two ends of the resistor R4 are respectively connected to the TV pin and the VS pin of the second reference voltage chip, one end of the capacitor C5 is connected to the VS pin of the first reference voltage chip and the TV pin of the second reference voltage chip, and the other end of the capacitor C5 is connected to the signal The first reference voltage chip is connected to the TP pin of the first reference voltage chip, one end of the resistor R5 is connected to the TP pin of the first reference voltage chip, one end of the capacitor C6, the capacitor C7 and the resistor R7 are connected to the OUTPUT pin of the first reference voltage chip, the other ends of the resistor R5, the capacitor C6 and the capacitor C7 are connected to the signal ground, the other end of the resistor R7 is connected to one end of the resistor R9, and one end of the resistor R9 is connected to the AC sampling circuit, that is, connected to the other end of the capacitor C4, one end of the resistor R6 is connected to the TP pin of the second reference voltage chip, one end of the capacitor C8 and the capacitor C9 are connected to the OUTPUT pin of the second reference voltage chip, one end of the resistor R8, the other end of the resistor R6, the other end of the capacitor C8 and the other end of the capacitor C9 are connected together and connected to the signal ground, the other end of the resistor R8 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the other end of the resistor R9 and connected to the signal ground.

[0039] Different from the first and second embodiments, the balancing circuit of this embodiment includes a resistor R17, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a first comparator, a second comparator, a MOS transistor Q1 and a MOS transistor Q2. One end of the resistor R17 and the resistor R12 are respectively connected to the DC reference circuit, that is, one end of the resistor R17 is connected to one end of the resistor R9, one end of the resistor R12 is connected to one end of the resistor R10, and the other ends of the resistor R17 and the resistor R12 are respectively connected to the positive input terminal and the reverse input terminal of the first comparator. One end of the resistor R13 and the gate of the MOS transistor Q1 are connected to the positive input terminal and the reverse input terminal of the first comparator. At the output end, the drain and source of the MOS tube Q1 are connected to one end of the resistor R17 and the resistor R12 respectively, the drain and source of the MOS tube Q2 are connected to one end of the resistor R17 and the resistor R12 respectively, the gate of the MOS tube Q2 and one end of the resistor R14 are connected to the output end of the second comparator, one end of the resistor R15 and the resistor R16 are connected to the reverse input end and the forward input end of the second comparator respectively, the other end of the resistor R15 is connected to one end of the resistor R17, the other end of the resistor R16 is connected to one end of the resistor R12, and the other end of the resistor R16 is connected to the signal processing unit, and the other ends of the resistors R13 and R14 are connected to the signal ground. Figure 4 In the above, TV refers to the threshold value of the MOS tube in the unsaturated region, U GS is the voltage between the gate and source of the MOS tube. GS <2TV, the current I between the drain and source of the MOS tube DS Follow U GS increase and increase rapidly.

[0040] Combination Figure 1 , 5 ​A fourth embodiment of an adaptive DC filtering circuit based on synchronous sampling is provided in the present embodiment. The connection method of the AC sampling circuit in the present embodiment is the same as that of the third embodiment. The DC reference circuit includes a first reference voltage chip, a second reference voltage chip, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a diode D1, a diode D2 and a capacitor C5. The V+ pins of the first reference voltage chip and the second reference voltage chip are connected to the device power supply circuit, the first V- pin and the second V- pin of the first reference voltage chip are connected together, one end of the resistor R18 and the resistor R19 are connected to the R pin of the first reference voltage chip, the other end of the resistor R18 and the resistor R19 are connected to the anode of the diode D1, and the third V- pin of the first reference voltage chip is connected to the anode of the diode D1. , the fourth V-pin is connected to the anode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R7, one end of the resistor R9 is connected to the other end of the resistor R7, the first V-pin of the second reference voltage chip is connected to the second V-pin, one end of the resistor R20 and the resistor R21 are connected to the R pin of the second reference voltage chip, the other end of the resistor R20 is connected to the cathode of the diode D2, the other end of the resistor R21 is connected to the anode of the diode D2, the third V-pin and the fourth V-pin of the second reference voltage chip are connected to the anode of the diode D2, one end of the resistor R8 is connected to the cathode of the diode D2, the other end of the resistor R8 is connected to one end of the resistor R10, one end of the capacitor C5 is connected to the device power supply circuit, and the other end of the capacitor C5, the other end of the resistor R9 and the other end of the resistor R10 are connected to the signal ground.

[0041] The balancing circuit includes a first comparator, a second comparator, a resistor R17, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a MOS tube Q1, a MOS tube Q2 and a capacitor C10. One end of the resistor R17 and the resistor R12 are respectively connected to the voltage reference circuit, that is, one end of the resistor R17 is connected to the other end of the resistor R7, one end of the resistor R12 is connected to the other end of the resistor R8, the other end of the resistor R17 and the other end of the resistor R12 are respectively connected to the positive input end and the reverse input end of the first comparator, one end of the resistor R13 and the gate of the MOS tube Q1 are connected to the output end of the first comparator, and the drain and source of the MOS tube Q1 are respectively connected. The MOS tube Q2 is connected to one end of the resistor R17 and the resistor R12 respectively, the drain and source of the MOS tube Q2 are connected to one end of the resistor R17 and the resistor R12 respectively, the gate of the MOS tube Q2 and one end of the resistor R14 are connected to the output end of the second comparator, one end of the resistor R15 and the resistor R16 are connected to the reverse input end and the forward input end of the second comparator respectively, the other end of the resistor R15 is connected to one end of the resistor R17, the other end of the resistor R16 is connected to one end of the resistor R12, and the other end of the resistor R16 and one end of the capacitor C10 are connected to the signal processing unit, the other ends of the resistor R13 and the resistor R14 are connected to the signal ground, and the other end of the capacitor C10 is connected to the power ground.

[0042] Compared with the balancing circuits in the first and second embodiments, the third and fourth embodiments use comparators in the balancing circuits. Compared with the three resistors in the first and second embodiments, the balancing circuits have higher sensitivity, but their cost is higher than that of the balancing circuit in the first embodiment. Therefore, different balancing circuits can be selected according to different application scenarios.

[0043] In addition, in the above four embodiments, the DC reference voltage uses two parallel reference voltage chips to output two DC voltages, and then the two DC voltages are balanced into a synchronous and consistent DC reference voltage through a balancing circuit. This parallel connection method has high reliability. Of course, two reference voltage chips can be connected in series or only one reference voltage chip can be used, and then two DC reference voltages are generated through resistor voltage division. The two DC reference voltages generated in this way have higher consistency and lower cost.

[0044] A DC filtering method based on the above-mentioned adaptive DC filtering circuit based on synchronous sampling comprises the following steps:

[0045] Step S1: The AC sampling circuit converts the collected current and voltage into a voltage signal;

[0046] Step S2: the power supply circuit of the device converts the power supply voltage into a DC voltage, and the DC reference circuit simultaneously converts the DC voltage into two identical DC reference voltages. The two DC reference voltages are instantaneously consistent in voltage through a balancing circuit, one of which is superimposed on the voltage signal converted by the AC sampling circuit as a DC bias signal to form a sinusoidal voltage signal that can be collected by the signal processing unit, and the other DC reference voltage is directly input into the signal processing unit as a DC reference voltage signal;

[0047] Step S3: The signal processing unit simultaneously collects the sinusoidal voltage signal and the DC reference voltage signal, and directly subtracts the synchronously sampled DC reference discrete signal value from each point of the sampled current and voltage discrete signal value. Preferably, the signal processing unit is an ARM chip with a built-in AD module, that is, the signal processing unit is a microprocessor with a built-in AD sampling module, and software calculation is used to directly subtract the synchronously sampled DC reference discrete signal value from each point of the sampled current and voltage discrete signal value, or the signal processing unit is an FPGA, and the differential circuit of the FPGA realizes the differential processing of the sinusoidal voltage signal and the DC reference voltage signal.

[0048] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An adaptive DC filtering circuit based on synchronous sampling, characterized in that: It includes an AC sampling circuit, a device power supply circuit, a DC reference circuit, a balance circuit and a signal processing unit. The AC sampling circuit converts the collected current and voltage into voltage signals. The device power supply circuit is used to convert the power supply voltage into a DC voltage. The DC reference circuit is connected to the device power supply circuit, and the DC reference circuit is connected with a balance circuit. The DC voltage is converted into two identical DC reference voltages through the DC reference circuit and the balance circuit. The balance circuit is used to keep the voltage values of the two voltage outputs equal. One of the DC reference voltages is directly input to the signal processing unit, and the other DC reference voltage is connected to the AC sampling circuit and input to the signal processing unit after superimposing a DC bias signal on the voltage signal. The signal processing unit synchronously samples the two input signals and performs a subtraction operation; the DC reference circuit includes two parallel reference voltage chips, and the two reference voltage chips are connected to the device power supply circuit and output two identical DC reference voltages after connecting the balance circuit.

2. The adaptive DC filtering circuit based on synchronous sampling according to claim 1, characterized in that: The signal processing unit is a microprocessor with an AD sampling module built in.

3. The adaptive DC filtering circuit based on synchronous sampling according to claim 1, characterized in that: The AC sampling circuit includes a voltage transformer, a voltage dividing resistor and a filtering circuit. The AC sampling circuit collects AC signals through the voltage transformer, and the AC signals are converted into voltage signals after passing through the voltage dividing resistor and the filtering circuit.

4. The adaptive DC filtering circuit based on synchronous sampling according to claim 1, characterized in that: The AC sampling circuit includes a voltage transformer, resistor R1, resistor R2, capacitor C1, capacitor C2, capacitor C3 and capacitor C4. Resistor R1 and capacitor C1 are both connected in parallel with the voltage transformer. One end of capacitor C1 and one end of capacitor C2 are respectively connected to both ends of resistor R1. The other end of capacitor C1 and the other end of capacitor C2 are connected to the power supply ground. One end of capacitor C4 is connected to one end of capacitor C3 through resistor R2, and one end of capacitor C4 is connected to the signal processing unit. The other end of capacitor C4 is connected to the other end of capacitor C3. The balance circuit is connected to the other end of capacitor C4.

5. The adaptive DC filtering circuit based on synchronous sampling according to claim 1, characterized in that: The DC reference circuit includes a first reference voltage chip, a second reference voltage chip, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9. The balance circuit includes resistor R9, resistor R10 and resistor R11; The first V- pin of the first reference voltage chip, the TV pin of the second base voltage chip are connected to the device power supply circuit. Both ends of the resistor R3 are respectively connected to the first V- pin and the second V- pin of the first reference voltage chip. Both ends of the resistor R4 are respectively connected to the TV pin and the VS pin of the second reference voltage chip. One end of the capacitor C5 is connected to the first V- pin of the first reference voltage chip and the TV pin of the second reference voltage chip, and the other end of the capacitor C5 is connected to the signal ground. One end of the resistor R5 is connected to the NC pin of the first reference voltage chip. One ends of the capacitor C6, the capacitor C7 and the resistor R7 are connected to the fourth V- pin of the first reference voltage chip. The third V- pin of the first reference voltage chip is connected to the fourth V- pin. The other ends of the resistor R5, the capacitor C6 and the capacitor C7 are connected to the signal ground. One end of the resistor R11 is connected to the other end of the resistor R7 and one end of the resistor R9, and one end of the resistor R11 is connected to the AC sampling circuit. One end of the resistor R6 is connected to the TP pin of the second reference voltage chip. One ends of the capacitor C8 and the capacitor C9 are connected to the OUTPUT pin of the second reference voltage chip. One end of the resistor R8, the other end of the resistor R6, the other end of the capacitor C8 and the other end of the capacitor C9 are connected together and connected to the signal ground. The other end of the resistor R11 is connected to the other end of the resistor R8 and one end of the resistor R10. The other end of the resistor R11 is connected to the signal processing unit. The other ends of the resistor R9 and the resistor R10 are connected and connected to the signal ground.

6. The adaptive DC filtering circuit based on synchronous sampling according to claim 1, characterized in that: the DC reference circuit includes a first reference voltage chip, a second reference voltage chip, resistors R7, R8, R9, R10, R18, R19, R20, R21, diodes D1, D2 and a capacitor C5, and the balancing circuit includes resistors R8, R9, R10 and a capacitor C10; The V+ pins of the first reference voltage chip and the second reference voltage chip are connected to the device power supply circuit. The first V- pin and the second V- pin of the first reference voltage chip are connected together. One ends of resistor R18 and resistor R19 are connected to the R pin of the first reference voltage chip, and the other ends of resistor R18 and resistor R19 are connected to the anode of diode D1. The third V- pin and the fourth V- pin of the first reference voltage chip are connected to the anode of diode D1. The cathode of diode D1 is connected to one end of resistor R7. One end of resistor R9 is connected to the other end of resistor R7. The first V- pin and the second V- pin of the second reference voltage chip are connected. One ends of resistor R20 and resistor R21 are connected to the R pin of the second reference voltage chip. The other end of resistor R20 is connected to the cathode of diode D2, and the other end of resistor R21 is connected to the anode of diode D2. The third V- pin and the fourth V- pin of the second reference voltage chip are connected to the anode of diode D2. One end of resistor R8 is connected to the cathode of diode D2, and the other end of resistor R8 is connected to one end of resistor R10. One end of capacitor C5 is connected to the device power supply circuit, and the other end of capacitor C5, the other end of resistor R9, and the other end of resistor R10 are connected to the signal ground. One end of resistor R11 is connected to one end of resistor R9 and is connected to the AC sampling circuit. The other end of resistor R11 is connected to one end of resistor R10 and is connected to the signal processing unit. One end of capacitor C10 is connected to the other end of resistor R11, and the other end of capacitor C10 is connected to the power ground.

7. An adaptive filter DC circuit based on synchronous sampling according to claim 1, characterized in that: The DC reference circuit includes a first reference voltage chip, a second reference voltage chip, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5, capacitor C6, capacitor C7, capacitor C8, and capacitor C9. The VS pin of the first reference voltage chip and the TV pin of the second reference voltage chip are connected to the device power supply circuit. The two ends of resistor R3 are respectively connected to the VS pin and the SLEEP pin of the first reference voltage chip. The two ends of resistor R4 are respectively connected to the TV pin and the VS pin of the second reference voltage chip. One end of capacitor C5 is connected to the VS pin of the first reference voltage chip and the TV pin of the second reference voltage chip, and the other end of capacitor C5 is connected to the signal ground. One end of resistor R5 is connected to the TP pin of the first reference voltage chip. One ends of capacitor C6, capacitor C7, and resistor R7 are connected to the OUTPUT pin of the first reference voltage chip. The other ends of resistor R5, capacitor C6, and capacitor C7 are connected to the signal ground. The other end of resistor R7 is connected to one end of resistor R9, and one end of resistor R9 is connected to the AC sampling circuit. One end of resistor R6 is connected to the TP pin of the second reference voltage chip. One ends of capacitor C8 and capacitor C9 are connected to the OUTPUT pin of the second reference voltage chip. One end of resistor R8, the other end of resistor R6, the other end of capacitor C8, and the other end of capacitor C9 are connected together and connected to the signal ground. The other end of resistor R8 is connected to one end of resistor R10, and the other end of resistor R10 is connected to the other end of resistor R9 and connected to the signal ground.

8. The adaptive filter DC circuit based on synchronous sampling according to claim 1, characterized in that: The DC reference circuit includes a first reference voltage chip, a second reference voltage chip, resistor R7, resistor R8, resistor R9, resistor R10, resistor R18, resistor R19, resistor R20, resistor R21, diode D1, diode D2, and capacitor C5. The V+ pins of the first reference voltage chip and the second reference voltage chip are connected to the device power supply circuit. The first V- pin and the second V- pin of the first reference voltage chip are connected together. One ends of resistor R18 and resistor R19 are connected to the R pin of the first reference voltage chip, and the other ends of resistor R18 and resistor R19 are connected to the anode of diode D1. The third V- pin and the fourth V- pin of the first reference voltage chip are connected to the anode of diode D1. The cathode of diode D1 is connected to one end of resistor R7. One end of resistor R9 is connected to the other end of resistor R7. The first V- pin and the second V- pin of the second reference voltage chip are connected. One ends of resistor R20 and resistor R21 are connected to the R pin of the second reference voltage chip. The other end of resistor R20 is connected to the cathode of diode D2, and the other end of resistor R21 is connected to the anode of diode D2. The third V- pin and the fourth V- pin of the second reference voltage chip are connected to the anode of diode D2. One end of resistor R8 is connected to the cathode of diode D2, and the other end of resistor R8 is connected to one end of resistor R10. One end of capacitor C5 is connected to the device power supply circuit, and the other end of capacitor C5, the other end of resistor R9, and the other end of resistor R10 are connected to the signal ground.

9. An adaptive DC filtering circuit based on synchronous sampling according to claim 7 or 8, characterized in that: The balancing circuit includes resistor R17, resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, a first comparator, a second comparator, MOS transistor Q1, and MOS transistor Q2. One ends of resistor R17 and resistor R12 are respectively connected to the DC reference circuit. The other ends of resistor R17 and resistor R12 are respectively connected to the positive input terminal and the negative input terminal of the first comparator. One end of resistor R13 and the gate of MOS transistor Q1 are connected to the output terminal of the first comparator. The drain and source of MOS transistor Q1 are respectively connected to one ends of resistor R17 and resistor R12. The drain and source of MOS transistor Q2 are respectively connected to one ends of resistor R17 and resistor R12. The gate of MOS transistor Q2 and one end of resistor R14 are connected to the output terminal of the second comparator. One ends of resistor R15 and resistor R16 are respectively connected to the negative input terminal and the positive input terminal of the second comparator. The other end of resistor R15 is connected to one end of resistor R17, and the other end of resistor R16 is connected to one end of resistor R12. And the other end of resistor R16 is connected to the signal processing unit. The other ends of resistor R13 and resistor R14 are connected to the signal ground.

10. A DC filtering method based on the adaptive DC filtering circuit based on synchronous sampling according to any one of claims 1-9, characterized in that: comprises the following steps Step S1: The AC sampling circuit converts the collected current and voltage into voltage signals; Step S2: The device power supply circuit converts the power supply voltage into a DC voltage. The DC reference circuit simultaneously converts the DC voltage into two identical DC reference voltages, and the two DC reference voltages achieve instantaneous voltage consistency through the balance circuit. One of the DC reference voltages is superimposed on the voltage signal converted by the AC sampling circuit as a DC bias signal to form a sine voltage signal that can be collected by the signal processing unit, and the other DC reference voltage is directly input into the signal processing unit as a DC reference voltage signal; Step S3: The signal processing unit simultaneously collects the sine voltage signal and the DC reference voltage signal, and directly subtracts the DC reference discrete signal value synchronously sampled from each point of the discrete signal value of the current and voltage obtained by sampling.

11. A DC filtering method according to claim 10, characterized in that: The signal processing unit is a microprocessor with an AD sampling module built in, and realizes directly subtracting the DC reference discrete signal value synchronously sampled from each point of the discrete signal value of the current and voltage obtained by sampling through software calculation; or, the signal processing unit is an FPGA, and realizes filtering by directly subtracting the DC reference discrete signal value synchronously sampled from each point of the discrete signal value of the current and voltage obtained by sampling through the differential circuit of the FPGA.

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