A method for monitoring ground resistance to improve chip testing efficiency

Abstract

The present invention discloses a method for monitoring ground resistance to improve chip test efficiency, comprising the following steps: step S1, connecting an adjustable current source between a ground pin to be tested and a digital input port, and disconnecting a power supply end of a corresponding digital circuit; step S2, setting a first current value for the current source, positively or negatively stimulating the digital input port to be tested, and recording the forward voltage or reverse voltage of the digital input port; step S3, setting a second current value for the current source, positively or negatively stimulating the digital input port to be tested, and recording the forward voltage or reverse voltage of the digital input port; step S4, calculating the overall standard compliance rate of the current test according to the measurement result; step S5, judging whether the current test meets the standard according to the obtained overall standard compliance rate, if so, outputting the test result as success, and performing the next set of chip tests; otherwise, judging whether to return to step S3 to perform the DTD test according to the DTD flag bit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a method for monitoring grounding resistance to improve chip testing efficiency. Background Art

[0002] Usually, some key analog parameters such as reference voltage Vref, low-dropout regulated output voltage Vldo, erase voltage VEE, programming voltage VEP, etc. need to be corrected and verified during chip testing (wafer testing, probe testing CP). Except for the ground pins GND pins, other chip pins can be monitored by the power management unit (PMU). Since the ground pins GND pins are physically connected to the system ground, it is difficult to directly monitor to determine whether the ground pins GND pins are well connected.

[0003] The disadvantages of not being able to monitor the GND pins connection are:

[0004] 1. If the contact resistance of the GND pins is high, the ground reference level will be raised, which will lead to incorrect test results. Moreover, the higher the power consumption of the circuit under test, the higher the test error.

[0005] 2. The digital acceptable range DAC correction will be seriously affected;

[0006] 3. The DTD (Double Touch Down) method can solve the problem of large contact resistance, but this is at the expense of test time and lifting costs;

[0007] 4. Since the contact resistance of the ground pins GND pins is directly related to the quality of the pad, it will affect the back-end packaging;

[0008] 5. An extra baking cycle is required, wasting time

[0009] For example: Assume that, during the first probe test (CP1), the bandgap reference voltage BGR is corrected at a high temperature of 85°C, and during the second probe test (CP2), the bandgap reference voltage BGR is verified at a normal temperature of 25°C; Assume that, during CP1, the ground resistance R GCT =1ohm, at CP2, grounding resistance R GCT =21ohm, circuit current consumption Ivcc=2mA, the minimum digital acceptable DAC level is 10mV;

[0010] The reference level caused by the ground pin will be raised by 2mA*(21-1)ohm, that is, 40mV. Correspondingly, the bandgap reference BGR reference voltage Vref of the digital acceptable range DAC will be raised by 40mV, which will cause an error of 4 times the minimum range and greatly affect the measurement result. Summary of the invention

[0011] In order to overcome the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for monitoring ground resistance to improve chip testing efficiency, so that the ground resistance R of the ground pins GND pins can be monitored without the need for an additional power management unit (PMU) or channel. GCT , to achieve the goal of improving test efficiency and accuracy.

[0012] To achieve the above and other purposes, the present invention provides a method for monitoring ground resistance to improve chip testing efficiency, comprising the following steps:

[0013] Step S1, connecting an adjustable current source between a ground pin to be tested and a digital input port, and disconnecting a power supply terminal of a corresponding digital circuit;

[0014] Step S2, setting a first current value for the current source, forwardly or reversely stimulating the current test digital input port, and recording the forward voltage or reverse voltage of the digital input port;

[0015] Step S3, setting a second current value for the current source, positively or negatively stimulating the digital input port, and recording the positive voltage or negative voltage of the digital input port;

[0016] Step S4, calculating the overall standard compliance rate of the current test according to the measurement results of steps S2 and S3;

[0017] Step S5, determine whether the current test meets the standard based on the obtained overall standard compliance rate. If it does, output the test result as successful and perform the next set of chip tests; otherwise, determine whether to return to step S3 for DTD testing based on the DTD flag bit.

[0018] Preferably, in step S1, a test device is connected, an input circuit with a digital input port is selected, an adjustable current source is connected between the digital input port of the selected input circuit and the system ground, and the power supply terminal of the selected input circuit is disconnected.

[0019] Preferably, in step S1, the DTD flag N is initialized.

[0020] Preferably, the adjustable current source is a test channel of a power management unit.

[0021] Preferably, in step S2, the current source is set to a first current value, the same digital input terminal of each chip currently being tested is stimulated in a positive or negative direction, and the voltage V1 of the digital port of each chip is recorded.

[0022] Preferably, the current source is set to a second current value, the same digital input terminal of each chip currently being tested is stimulated in a positive or negative direction, and the voltage V2 of the digital port of each chip is recorded.

[0023] Preferably, in step S4, the voltage ratio and voltage difference in the forward or reverse direction are calculated for each chip, the number of chips with a voltage ratio less than a first threshold and the number of chips with a voltage difference less than a second threshold are calculated, and the overall standard compliance rate is calculated.

[0024] Preferably, in step S5, the overall standard compliance rate is compared with a third threshold value. If it is greater than the third threshold value, the test result is output as success, and the next set of chip tests are performed; otherwise, it is determined whether the DTD flag N is greater than 0. If it is greater than 0, the test result is output as failure and marked. If the DTD flag N is 0, the DTD flag N is set to 1, and the process returns to step S2 for DTD testing.

[0025] Preferably, before step S1, the method further includes the following steps:

[0026] Select forward or reverse excitation mode for testing.

[0027] Preferably, the step of selecting a forward or reverse excitation mode for testing is to select a bias mode with a larger I / V slope in the forward conduction and reverse breakdown current voltage curves as the setting for the current batch chip test based on the test results of the forward conduction and reverse breakdown current tests on the input port during small batch chip testing.

[0028] Compared with the prior art, the present invention provides a method for monitoring ground resistance to improve chip test efficiency. The method connects an adjustable current source between a ground pin to be tested and a digital input port and disconnects the power supply end of a corresponding digital circuit, sets a first current value and a second current value for the current source respectively, stimulates the digital input port in a positive or negative direction, and records the forward voltage or the reverse voltage of the digital input port respectively. The overall standard compliance rate of the current test is calculated according to the recorded results, and whether the current test meets the standard is determined according to the obtained overall standard compliance rate. If it meets the standard, the test result is output as success, and the next group of chip tests are performed; otherwise, it is determined whether to return to the DTD test according to the DTD flag bit. The present invention realizes monitoring the ground resistance R of the ground pins GND pins without the need for an additional power management unit (PMU) or channel. GCT , to achieve the goal of improving test efficiency and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An equivalent circuit diagram of a method for monitoring ground resistance to improve chip testing efficiency and accuracy of the present invention;

[0030] Figure 2 It is a schematic diagram of the principle of the excitation method based on the forward current-forward voltage or reverse current-reverse voltage slope;

[0031] Figure 3 The present invention is a flowchart of a method for monitoring ground resistance to improve chip testing efficiency. DETAILED DESCRIPTION

[0032] The following describes the implementation of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Figure 1 The present invention is a monitoring grounding resistance R GCT The equivalent circuit of the method for improving chip testing efficiency and accuracy, D1, D2 are the anti-static ESD equivalent diodes corresponding to the input port IO, P1, N1 are the pull-up PMOS tube and pull-down NMOS tube of the input port, and the grounding resistor R GCT The equivalent contact resistance from the ground pin GND pins to the system ground. The cathode of D1, the anode of D2, the gate of the PMOS tube P1 and the gate of the NMOS tube N1 are connected to form the input port IO of the input circuit. The cathode of D2 is connected to the source of the PMOS tube P1 to form the power supply terminal VCC of the input circuit. The anode of D1 is connected to the source of the NMOS tube N1 to form the ground pin GND pins of the input circuit. The grounding resistance R GCT Connect between the GND pins and system ground.

[0034] Figure 2 The schematic diagram of the principle of the excitation method based on the forward current-forward voltage or reverse current-reverse voltage slope of the present invention is shown in FIG. f is the forward conduction voltage), and the forward voltage difference (ΔV f ) and voltage ratio, and the reverse current-reverse voltage relationship during reverse breakdown (U BR is the reverse breakdown voltage), and the reverse voltage difference (ΔV bV) and voltage ratio. If the overall standard compliance rate of the voltage difference and voltage ratio is less than the standard (threshold 3) in one test, DTD test is required.

[0035] Figure 3 FIG. 1 is a flow chart of the steps of a method for monitoring ground resistance to improve chip testing efficiency. Figure 3 As shown, the present invention provides a method for monitoring ground resistance to improve chip testing efficiency, comprising the following steps:

[0036] Step S1, connecting an adjustable current source between a ground pin to be tested and a digital input port, and disconnecting a power supply terminal VCC of a corresponding digital circuit.

[0037] Specifically, the test equipment is connected, an input circuit with an input port is selected, an adjustable current source, i.e., a test channel of a power management unit PMU, is connected between a digital input port IO of the selected input circuit and a system ground, a power supply terminal VCC of the selected input circuit is disconnected, and a DTD flag N is initialized, i.e., the DTD flag N=0;

[0038] Step S2, setting a first current value I1 for the current source, positively or negatively stimulating the input port IO, and recording the positive voltage or negative voltage V1 of the digital input port IO respectively, wherein I1 is much larger than a normal value.

[0039] Specifically, the current source is set to a first current value I1 (eg, 10 mA, generally much larger than the conventional 100 uA), and the same digital input terminal of each chip is stimulated in the forward or reverse direction according to selection, and the voltage V1 of the digital port of each chip is recorded.

[0040] Preferably, before step S1, a forward or reverse excitation mode should be selected for testing.

[0041] Specifically, based on the test results of the forward conduction and reverse breakdown current tests on the input port during the early small-batch chip testing, the bias setting with a larger I / V slope in the forward conduction and reverse breakdown current-voltage curves is selected as the setting for the batch chip test, that is, forward or reverse excitation is selected for testing.

[0042] Step S3, setting a second current value I2 for the current source, positively or negatively stimulating the input port IO, and recording the positive voltage or negative voltage V2 of the digital input port IO respectively, wherein I2>I1 and is much larger than the normal value (100uA), such as 20mA.

[0043] Specifically, the current source is set to a second current value I2 (eg, 20 mA, generally much larger than the conventional 100 uA), and the voltage V2 of the digital port of each chip is recorded according to the selection of forward or reverse excitation of the same digital input terminal of each chip.

[0044] Step S4, calculating the overall standard compliance rate of the current test according to the measurement results of steps S2 and S3.

[0045] Specifically, the voltage ratio V2 / V1 and voltage difference V2-V1 in the forward or reverse direction are calculated for each chip, the number of chips Y1 whose voltage ratio is less than the first threshold (assuming that the total number of chips currently tested is Y) and the number Y2 whose voltage difference is less than the second threshold are calculated, and then the overall standard compliance rate Yield is calculated, that is, Yield = (Y1+Y2) / 2Y.

[0046] Step S5, judge whether the test meets the standard according to the obtained overall standard compliance rate Yield, if it does, output the test result as success, and perform the next set of chip tests; otherwise, judge whether the DTD test has been performed according to the DTD flag N, if the DTD test has been performed, output the test result as failure, and mark it, otherwise set the DTD flag N to 1, and return to step S3 to perform the test, that is, the DTD test.

[0047] Specifically, after obtaining the overall standard compliance rate Yield, the overall standard compliance rate Yield is compared with the preset third threshold value. If it is greater than the third threshold value, it means that the current test meets the standard, the test result is output as success, and the next set of chip tests are performed; otherwise, it is determined whether the DTD flag N is greater than 0. If it is greater than 0, it means that the DTD test has been performed, and the test result is output as failure and marked. If the DTD flag N is 0, the DTD flag N is set to 1, and return to step S3 to perform the DTD test.

[0048] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art may modify and change the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A method for monitoring ground resistance to improve chip testing efficiency, comprising the following steps: Step S1, connecting an adjustable current source between a ground pin to be tested and a digital input port, and disconnecting a power supply terminal of a corresponding digital circuit; Step S2, setting a first current value for the current source, forwardly or reversely stimulating the current test digital input port, and recording the forward voltage or reverse voltage of the digital input port; Step S3, setting a second current value for the current source, positively or negatively stimulating the digital input port, and recording the positive voltage or negative voltage of the digital input port; Step S4, calculating the overall standard compliance rate of the current test according to the measurement results of steps S2 and S3; Step S5, judging whether the current test meets the standard according to the obtained overall standard compliance rate, if it does, outputting the test result as success and proceeding to the next group of chip tests; otherwise, judging whether to return to step S3 to perform DTD testing according to the DTD flag bit; In step S4, the voltage ratio and voltage difference in the forward or reverse direction are calculated for each chip, the number of chips with a voltage ratio less than a first threshold and the number of chips with a voltage difference less than a second threshold are calculated, and the overall standard compliance rate is calculated.

2. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 1, characterized in that: In step S1, a test device is connected, an input circuit with a digital input port is selected, an adjustable current source is connected between the digital input port of the selected input circuit and the system ground, and the power supply terminal of the selected input circuit is disconnected.

3. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 2, characterized in that: In step S1 , the DTD flag N is initialized.

4. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 3, characterized in that: The adjustable current source is a test channel of the power management unit.

5. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 4, characterized in that: In step S2, the current source is set to a first current value, the same digital input terminal of each chip under test is stimulated in a positive or negative direction, and the voltage V1 of the digital port of each chip is recorded.

6. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 5, characterized in that: The current source is set to a second current value, and the same digital input terminal of each chip under current testing is stimulated in a positive or negative direction, and the voltage V2 of the digital port of each chip is recorded.

7. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 6, characterized in that: In step S5, the overall standard compliance rate is compared with the third threshold value. If it is greater than the third threshold value, the test result is output as success and the next set of chip tests are performed; otherwise, it is determined whether the DTD flag N is greater than 0. If it is greater than 0, the test result is output as failure and marked. If the DTD flag N is 0, the DTD flag N is set to 1, and return to step S2 for DTD testing.

8. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 7, characterized in that: Before step S1, the method further includes the following steps: Select forward or reverse excitation mode for testing.

9. A method for monitoring ground resistance to improve chip testing efficiency as claimed in claim 8, characterized in that: The step of selecting the forward or reverse excitation mode for testing is to select the bias mode with a larger I / V slope in the forward conduction and reverse breakdown current voltage curves as the setting for the current batch chip test based on the test results of the forward conduction and reverse breakdown current tests on the input port during small batch chip testing.

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