Double pulse test method, circuit and system

Abstract

The present application provides a double-pulse test method, circuit and system. The double-pulse test method controls the inductance of the load inductor connected to the module to be tested to be less than the first threshold value during the first pulse of controlling the conduction of the switch tube to be tested. That is, even if the module to be tested adopts a load inductor with a smaller inductance during the first pulse, the energy transmitted from the DC bus capacitor to the load inductor can be reduced, and the degree of bus voltage drop of the high-power module when performing double-pulse testing can be reduced; no external capacitor pool is required, thereby avoiding the problem of low accuracy of test results caused by the external capacitor pool in the prior art. In addition, after the end of the first pulse, the present application can adopt a load inductor with a larger inductance. Therefore, during the double-pulse interval, the energy consumption of the load inductor is slow, and the current difference between the load inductor at the beginning of the second pulse and the end of the first pulse is small, thereby ensuring the accuracy of the test results.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a double-pulse test method, circuit, and system. Background Art

[0002] With the continuous development of the new energy industry, power modules in power electronic converters such as inverters and rectifiers tend to be high-power. In order to ensure the normal and stable operation of the power modules, it is often necessary to perform double-pulse tests on the power modules to test their working characteristics.

[0003] Figure 1 The figure shows a conventional double-pulse test circuit, which can realize double-pulse testing of modules (including switching tubes Q1 and Q2); however, as the power level increases, the module current level increases. When performing double-pulse testing on high-power modules, the energy transmitted from the bus capacitor Cdc to the load inductor L increases, and there may be a problem of bus voltage drop.

[0004] In order to solve the problem of bus voltage drop during double-pulse testing, one existing solution is to connect a group of large-capacity capacitor pools in parallel at both ends of the bus capacitor Cdc to reduce the degree of bus voltage drop; however, this method will introduce stray inductance between the external capacitor pool and the module bus capacitor pool, resulting in reduced accuracy of the test results. Summary of the Invention

[0005] In view of this, the present application provides a double-pulse test method, circuit, and system to avoid the problem of low test result accuracy caused by the addition of an external capacitor pool.

[0006] To achieve the above objectives, this application provides the following technical solutions:

[0007] The first aspect of the present application provides a double pulse testing method, comprising:

[0008] During the first pulse period, the switch tube to be tested in the module to be tested is controlled to be turned on, and the inductance value of the load connected to the module to be tested is controlled to be less than a first threshold value;

[0009] During the double pulse interval, controlling the switch tube to be tested to be turned off;

[0010] During the second pulse period, the switch tube to be tested is controlled to be turned on.

[0011] Optionally, after controlling the inductance value of the load connected to the module to be tested to be less than a first threshold, the method further includes:

[0012] After the first pulse ends, the inductance of the load is controlled to be greater than a second threshold; the second threshold is greater than or equal to the first threshold.

[0013] Optionally, controlling the inductance value of the load inductor connected to the module to be tested to be less than a first threshold value includes: bypassing part of the series inductance in the load inductor;

[0014] Controlling the load inductance to be greater than a second threshold value includes: releasing the bypass of the part of the series inductance.

[0015] Optionally, controlling the inductance value of the load inductor connected to the module to be tested to be smaller than a first threshold value includes: switching in an inductor having an inductance value smaller than the first threshold value as the load inductor;

[0016] Controlling the inductance value of the load inductor to be greater than a second threshold value includes: switching in an inductor having an inductance value greater than the second threshold value as the load inductor.

[0017] The second aspect of the present application provides a double pulse test circuit, comprising: a DC bus capacitor, a first inductor, a second inductor, and a switch module; wherein,

[0018] The DC bus capacitor is connected in parallel with the module to be tested;

[0019] The first inductor and the second inductor are connected in series, and the series branch is connected in parallel with the freewheeling diode to be tested in the module to be tested;

[0020] The switch module is connected in parallel with the first inductor; when the double-pulse test circuit performs a double-pulse test on the module to be tested, the switch module is in a closed state before the end of the first pulse and is in an open state after the end of the first pulse.

[0021] Optionally, both the first inductor and the second inductor are air-core inductors.

[0022] Optionally, the inductance of the first inductor is greater than the inductance of the second inductor, and the difference between the inductance and the second inductance is greater than a preset value.

[0023] Optionally, the first inductor includes: one inductor, or at least two inductors connected in series;

[0024] The second inductor includes: one inductor, or at least two inductors connected in series.

[0025] Optionally, the current level of the switch module is greater than the maximum load current of the module to be tested.

[0026] Optionally, the switch module includes: a first switch tube and a second switch tube;

[0027] The first switching tube and the second switching tube are both provided with anti-parallel diodes;

[0028] The first switch tube and the second switch tube are connected in reverse series, and the anti-parallel diode of the second switch tube has the same current flow direction as that of the switch tube under test in the module under test;

[0029] The second switch tube is normally off, the first switch tube is in a closed state before the first pulse ends, and is in an open state after the first pulse ends.

[0030] Optionally, it also includes: a DC power supply;

[0031] The DC power supply is connected in parallel with the DC bus capacitor.

[0032] The third aspect of the present application provides a double pulse test system, comprising: a host computer, a control board, and the double pulse test circuit as described in any one of the second aspects above; wherein,

[0033] The host computer is used to control the switch tube in the module to be tested and the action of the switch module in the double pulse test circuit through the control board.

[0034] The double-pulse test method provided by the present application controls the inductance of the load inductor connected to the module to be tested to be less than the first threshold value during the first pulse period of controlling the conduction of the switch tube to be tested. That is, even if the module to be tested adopts a load inductor with a smaller inductance value during the first pulse period, the energy transmitted from the DC bus capacitor to the load inductor can be reduced, and the degree of bus voltage drop of the high-power module during the double-pulse test can be reduced; no external capacitor pool is required, thereby avoiding the problem of low accuracy of test results caused by the external capacitor pool in the prior art. In addition, after the end of the first pulse, the present application can adopt a load inductor with a larger inductance value. Therefore, during the double-pulse interval, the energy consumption of the load inductor is slow, and the current difference between the load inductor at the beginning of the second pulse and the end of the first pulse is small, thereby ensuring the accuracy of the test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings to be used in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1 It is a structural diagram of a double pulse test circuit in the prior art;

[0037] Figure 2a Schematic diagram of double pulse test waveform of double pulse test circuit under ideal conditions in the prior art;

[0038] Figure 2b It is a schematic diagram of double pulse test waveforms of a double pulse test circuit in the prior art when the load inductance is large;

[0039] Figure 3 A flow chart of a double pulse test method provided in an embodiment of the present application;

[0040] Figure 4a It is a schematic diagram of double pulse test waveforms of a double pulse test circuit in the prior art when the load inductance is small;

[0041] Figure 4b A schematic diagram of a double pulse test waveform of a double pulse test circuit provided in an embodiment of the present application;

[0042] Figure 5 Another flow chart of the double pulse testing method provided in an embodiment of the present application;

[0043] Figure 6 and Figure 7 Two structural schematic diagrams of the double-pulse test circuit provided in the embodiments of the present application;

[0044] Figure 8 A schematic diagram of the control signals of the double-pulse test circuit and each switch in the module to be tested provided in an embodiment of the present application;

[0045] Figure 9 A schematic diagram of the structure of a double-pulse test system provided in an embodiment of the present application;

[0046] Figure 10 This is a schematic diagram of the control signals of the switch module and each switch tube in the module to be tested in the double-pulse test circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0048] In this application, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0049] by Figure 1 Take the structure shown in the figure as an example. Assume that the load inductor L is connected in parallel with the switch tube Q2 and its anti-parallel diode. Then the switch tube Q1 is used as the switch tube to be tested in the module to be tested, and the anti-parallel diode of the switch tube Q2 is used as the freewheeling diode to be tested in the module to be tested. When performing a double pulse test on the module to be tested:

[0050] Figure 2a The figure shows the ideal double pulse test waveform, where i L is the current flowing through the load inductor L, i c is the current flowing through the switch tube Q1 to be tested, V ge is the voltage between the base and emitter of the switch tube Q1 to be tested, V ce is the voltage between the collector and emitter of the switch tube Q1 to be tested; under ideal working conditions, the current i flowing through the load inductor L L During the double pulse interval (i.e., t1 to t2), the voltage remains unchanged, and there is no drop in the bus voltage during the double pulse test. Based on this waveform, the current i of the switch Q1 to be tested in the module can be obtained at time t1. c for i c The turn-off characteristic parameter data at (t1) is obtained, and the current i of the switch tube Q1 to be tested is obtained at time t2 c for i c (t2) Opening characteristic parameter data, where i c (t1)=i c (t2)=i, that is, the switching characteristic parameter data of the switch tube to be tested when the current is i can be obtained through the waveform.

[0051] According to W L =0.5·L·I 2 It can be obtained that during the double-pulse test, the energy stored in the load inductor L during the first pulse (i.e., the period from t0 to t1) is:

[0052]

[0053] The energy stored in the load inductor L during the second pulse (i.e., during t2 to t3) is:

[0054]

[0055] When the load inductance L has different values, i c (t2) and i c (t3) are different, and the module switch tube voltage stress can be obtained at time t1. Therefore, according to the amount of energy stored in the load inductor L during the first pulse, the influence of the size of the load inductor L on the accuracy of the module switch tube voltage stress data is analyzed.

[0056] During double pulse testing, no matter how large the load inductance L is, i c The expected value of (t1) remains unchanged. According to formula (1), when the inductance of the load inductor L is larger, the energy stored during the first pulse is larger, that is, the energy transmitted from the bus capacitor Cdc to the load inductor L is larger, the bus voltage drop is larger, and the module switch tube voltage stress data obtained from the double pulse test is less accurate. Figure 2b The figure shows the double pulse test waveform when the load inductance L is large. ce The waveform shows a bus voltage drop, reducing the accuracy of the voltage stress data. As the module power level and load current increase, the energy stored in the load inductor L during the double-pulse test increases, leading to a deeper bus voltage drop. However, as the load inductor L decreases in value, the energy stored during the first pulse decreases. This means that less energy is transferred from the bus capacitor Cdc to the load inductor L, minimizing the bus voltage drop and improving the accuracy of the module switch voltage stress data obtained from the double-pulse test.

[0057] Therefore, in order to avoid the problem of low accuracy of test results caused by the external capacitor pool in the prior art, the present application provides a double pulse test method, which is as follows: Figure 3 Shown, including:

[0058] S101 . During a first pulse period, the switch tube to be tested in the module to be tested is controlled to be turned on, and the inductance of the load connected to the module to be tested is controlled to be smaller than a first threshold.

[0059] In practical applications, at least two inductors can be connected in series to implement the load inductance, and by bypassing some of the series inductance, the load inductance can be reduced to a value less than a first threshold. Of course, other solutions are not excluded for adjusting the load inductance. For example, at least two inductors with different inductances can be connected in series with corresponding switches and then connected in parallel to implement the load inductance. When executing step S101, the inductor with an inductance less than the first threshold is switched in as the load inductance. This depends on the specific application environment and is within the scope of protection of this application.

[0060] After step S101 is executed, steps S102 and S103 are executed in sequence.

[0061] S102. During the double pulse interval, the switch tube to be tested is controlled to be turned off.

[0062] S103 , during the second pulse period, controlling the switch tube to be tested to be turned on.

[0063] The dual-pulse testing method provided in this embodiment can reduce the energy transmitted from the DC bus capacitor to the load inductor by controlling the module to be tested to adopt a load inductor with a smaller inductance during the first pulse, thereby reducing the degree of bus voltage drop when performing a dual-pulse test on a high-power module; and does not require an external capacitor pool, thereby avoiding the problem of low test result accuracy caused by the external capacitor pool in the prior art.

[0064] It is worth noting that in order to solve the problem of bus voltage drop during double pulse testing, there is also a solution in the prior art that is to connect a DC power supply with a larger output current in parallel with the Figure 1 The bus capacitor Cdc is connected to the DC power supply to maintain a constant voltage. However, this requires the DC power supply to provide a large amount of energy to the bus capacitor Cdc in a short period of time. The higher the module power level, the deeper the bus voltage drop, and the higher the output current level of the DC power supply is required to maintain the bus voltage stability. Therefore, this method has high performance requirements for the DC power supply.

[0065] The dual-pulse testing method provided in this embodiment controls the module to be tested to use a load inductor with a small inductance during the first pulse to reduce the energy transmitted from the DC bus capacitor to the load inductor, thereby reducing the degree of bus voltage drop of the high-power module when performing a dual-pulse test. Therefore, when the bus capacitor Cdc is connected in parallel with a DC power supply, the performance requirements for the DC power supply can also be reduced.

[0066] On the basis of the above embodiment, further, Figure 1 The double pulse test process is explained using the structure shown in the figure as an example. When the load inductance L decreases, although the bus voltage drop decreases, the accuracy of the module switch tube voltage stress data obtained by the double pulse test is improved. However, during the double pulse interval, the inductor current drops more, that is, i c (t2) c (t1) and the difference is large. Therefore, the module switch tube turn-on characteristic parameters obtained at time t2 are significantly different from the expected values, which reduces the accuracy of the double-pulse test data. Figure 4a The figure shows the double pulse test waveform when the load inductance L is relatively small. c The waveform shows that the current flowing through the load inductor L drops significantly during the double pulse period, and the accuracy of the turn-on characteristic parameter data is reduced.

[0067] ​Therefore, this embodiment further provides an optimal dual-pulse test method that leverages the advantages of varying load inductance values. Before the first pulse ends, a smaller load inductor is used to minimize bus voltage drop; after the first pulse, a larger load inductor is used to minimize the inductor current drop. Furthermore, because the module's switching characteristic parameter data can be extracted at both t1 and t2, using a larger load inductor after the first pulse does not affect the accuracy of the dual-pulse test data. Figure 4b The double pulse test waveform is shown in the above scheme of the present application. ce The waveform shows that the bus voltage drop is reduced, the performance requirements of the DC power supply are reduced, and the accuracy of the module switch tube voltage stress data is improved. At the same time, according to i c The waveform shows that the inductor current drop during the double pulse period is reduced, and the accuracy of the turn-on characteristic parameter data is improved.

[0068] See also Figure 5 , the double pulse test method is Figure 3 Based on the situation shown, after executing step S101, the following steps are also included:

[0069] S201 : After the first pulse ends, control the load inductance to be greater than a second threshold.

[0070] The second threshold is greater than or equal to the first threshold. If, in step S101, a load inductance with a small inductance is achieved by bypassing part of the series inductance, then in step S201, a load inductance with a large inductance can be achieved by removing the bypass for the part of the series inductance. If, in step S101, a load inductance with a small inductance is achieved by switching in an inductance with an inductance less than the first threshold as the load inductance, then in step S201, a load inductance with a large inductance can be achieved by switching in an inductance with an inductance greater than the second threshold as the load inductance.

[0071] The values ​​of the first threshold and the second threshold are not limited here and can be determined according to the specific application environment, and are all within the protection scope of this application.

[0072] The dual-pulse testing method provided in this embodiment controls the module under test to use a low-inductance load inductor during the first pulse. This reduces the energy transferred from the DC bus capacitor to the load inductor, lowers the bus voltage drop in high-power modules during dual-pulse testing, and reduces the performance requirements for the DC power supply. Furthermore, after the first pulse ends, a high-inductance load inductor is used. Therefore, during the interval between the two pulses, the load inductor consumes less energy, and the current difference between the load inductor at the beginning of the second pulse and the end of the first pulse is smaller, ensuring the accuracy of the test results.

[0073] Another embodiment of the present application also provides a double pulse test circuit, such as Figure 6 As shown, it includes: a DC bus capacitor Cdc, a first inductor L1, a second inductor L2 and a switch module K; wherein:

[0074] The DC bus capacitor Cdc is connected in parallel with the module to be tested; the first inductor L1 and the second inductor L2 are connected in series, and the series branch is connected to the freewheeling diode to be tested in the module to be tested ( Figure 6 The switch module K is connected in parallel with the first inductor L1.

[0075] When the double-pulse test circuit performs a double-pulse test on the module to be tested, its specific process and principle can be referred to the above embodiment and will not be repeated here; moreover, the switch module K is in a closed state before the end of the first pulse to bypass the first inductor L1, so that the inductance of the load inductor is only the inductance of the second inductor L2, which is less than the first threshold value, forming a small inductance loop; the switch module K is in an open state after the end of the first pulse to release the bypass of the first inductor L1, so that L1 is connected to the circuit, and the inductance of the load inductor is the sum of the inductances of the first inductor L1 and the second inductor L2, which is greater than the second threshold value, forming a large inductance loop.

[0076] In practical applications, the first inductor L1 and the second inductor L2 can both be air-core inductors. Furthermore, the inductance of the first inductor L1 can be set to be greater than the inductance of the second inductor L2, with the difference between the two being greater than a preset value. Optionally, the first inductor L1 can be a single inductor or include at least two inductors connected in series. Similarly, the second inductor L2 can be a single inductor or include at least two inductors connected in series. The specific application environment and the configuration are all within the scope of protection of this application.

[0077] This embodiment improves the traditional dual-pulse test circuit by dividing the load inductance into two parts, connecting them in series and then in parallel at both ends of the freewheeling diode to be tested, and connecting a bypass switch in parallel at both ends of the inductor with large inductance to achieve the change of the load inductance value during the dual-pulse test, reduce the degree of bus voltage drop during the dual-pulse test of high-power modules, reduce the performance requirements of the DC power supply during the test, and improve the accuracy of the switching characteristic parameter data of the module switch tube.

[0078] In practical applications, for the selection of the inductance values ​​of the two inductors, please refer to the following:

[0079] (1) The value of the second inductor L2 should be selected to ensure that the voltage drop of the DC bus capacitor Cdc does not exceed 1% when the first pulse of the double pulse ends. Then:

[0080]

[0081] Where U'=U-0.01U=0.99U, U is the DC bus voltage, then:

[0082]

[0083] Of course, other values ​​may be used to replace 1%, depending on the actual requirements of the specific application environment, and all are within the scope of protection of this application.

[0084] (2) The inductance value of the first inductor L1 should be selected to ensure that the inductor current does not drop by more than 1% during the double pulse interval. Based on U = L·di / dt, we have:

[0085] i c (t2)-i c (t1)=U·(t2-t1) / (L1+L2)≤0.01i c (t1) (5)

[0086] Right now

[0087]

[0088] Of course, other values ​​may be used to replace 1%, depending on the actual requirements of the specific application environment, and all are within the scope of protection of this application.

[0089] In addition, it should be noted that the current level of the switch module K should be greater than the maximum load current of the module to be tested, and the switching speed should be fast. Specifically, it can be a fully controlled power switch device.

[0090] In practical applications, the switch module K can be Figure 7 As shown in , it specifically includes: a first switch tube S1 and a second switch tube S2; wherein:

[0091] The first switch tube S1 and the second switch tube S2 are both provided with anti-parallel diodes; the first switch tube S1 and the second switch tube S2 are connected in reverse series. Figure 7 The series connection position of the first switch tube S1 and the second switch tube S2 is only an example and is not limited thereto. In actual applications, they can also be interchanged.

[0092] If the anti-parallel diode of the second switch tube S2 has the same current flow direction as the switch tube to be tested in the module to be tested, the second switch tube S2 can be set to be normally off, and the first switch tube S1 is in a closed state before the end of the first pulse and in an open state after the end of the first pulse. Figure 8The figure shows a schematic diagram of the control signals of each switch tube, where PWM_Q1 is the PWM control signal for the switch tube Q1 in the module under test, PWM_Q2 is the PWM control signal for the switch tube Q2 in the module under test, PWM_S1 is the PWM control signal for the first switch tube S1, and PWM_S2 is the PWM control signal for the second switch tube S2. The second switch tube S2 is always off. Before the first pulse of the double pulse ends, the first switch tube S1 is closed to bypass the first inductor L1 to form a small inductance loop. After the first pulse ends, the first switch tube S1 is disconnected, and the first inductor L1 is connected to the circuit to form a large inductance loop. By switching the inductors during the double pulse test, the bus voltage drop during the double pulse test of the high-power module is reduced and the accuracy of the switching characteristic information of the module switch tube is improved.

[0093] It should be noted that, in actual applications, the dual-pulse test circuit preferably also includes: a DC power supply connected in parallel with the DC bus capacitor Cdc; the DC power supply is used to provide a DC voltage to the module to be tested, which can maintain the bus voltage unchanged and further reduce the degree of bus voltage drop.

[0094] The dual-pulse test circuit provided in this embodiment reduces the bus voltage drop when performing a dual-pulse test on the module to be tested, and reduces the performance requirements of the DC power supply; moreover, the accuracy of the switching characteristic parameter data of the switch tube of the module to be tested is improved, providing a reference for the whole machine test.

[0095] Another embodiment of the present application also provides a double pulse test system, which is as follows Figure 9 As shown, it includes: a host computer 10, a control board 20 and a double pulse test circuit 30; wherein,

[0096] The host computer 10 is used to control the switch module (such as the switch module) in the test module 40 and the double pulse test circuit 30 through the control board 20. Figure 6 K) action shown in .

[0097] Figure 10 The figure shows a schematic diagram of the control signals output by the control board 20, wherein PWM_Q1 is the PWM control signal for the switch tube Q1 in the module to be tested 40, PWM_Q2 is the PWM control signal for the switch tube Q2 in the module to be tested 40, and PWM_K is the PWM control signal for the switch module K in the dual-pulse test circuit 30; before the end of the first pulse of the dual pulse, the switch module K is closed to form a load inductor with a small inductance; after the end of the first pulse, the switch module K is disconnected to form a load inductor with a large inductance; by switching the inductors during the dual-pulse test, the bus voltage drop during the dual-pulse test of the high-power module is reduced and the accuracy of the switching characteristic information of the module switch tube is improved.

[0098] The same or similar parts between the various embodiments in this specification can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Ordinary technicians in this field can understand and implement it without making any creative efforts.

[0099] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0100] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined to enable those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A double pulse test method, characterized in that: include: During the first pulse period, the switch tube to be tested in the module to be tested is controlled to be turned on, and the inductance of the load inductor with adjustable inductance connected to the module to be tested is controlled to be less than a first threshold value; During the double pulse interval, the switch tube to be tested is controlled to be turned off; and after the first pulse ends, the inductance value of the load inductance is controlled to be greater than a second threshold value; the second threshold value is greater than or equal to the first threshold value; During the second pulse period, the switch tube to be tested is controlled to be turned on.

2. The double pulse test method according to claim 1, characterized in that: Controlling the load inductance to be less than a first threshold value includes: bypassing a portion of the series inductance in the load inductance; Controlling the load inductance to be greater than a second threshold value includes: releasing the bypass of the part of the series inductance.

3. The double pulse test method according to claim 1, characterized in that: Controlling the load inductance to be smaller than a first threshold value includes: switching in an inductor having an inductance value smaller than the first threshold value as the load inductor; Controlling the inductance value of the load inductor to be greater than a second threshold value includes: switching in an inductor having an inductance value greater than the second threshold value as the load inductor.

4. A double pulse test circuit, characterized in that: include: DC bus capacitor, first inductor, second inductor and switch module; wherein, The DC bus capacitor is connected in parallel with the module to be tested; The first inductor and the second inductor are connected in series, and the series branch is connected in parallel with the freewheeling diode to be tested in the module to be tested; The switch module is connected in parallel with the first inductor; when the double-pulse test circuit performs a double-pulse test on the module to be tested, the switch module is in a closed state before the end of the first pulse and is in an open state after the end of the first pulse.

5. The double pulse test circuit according to claim 4, characterized in that: The first inductor and the second inductor are both air-core inductors.

6. The double pulse test circuit according to claim 4, characterized in that: The inductance of the first inductor is greater than the inductance of the second inductor, and the difference between the inductances is greater than a preset value.

7. The double pulse test circuit according to claim 4, characterized in that: The first inductor includes: one inductor, or at least two inductors connected in series; The second inductor includes: one inductor, or at least two inductors connected in series.

8. The double pulse test circuit according to claim 4, characterized in that: The current level of the switch module is greater than the maximum load current of the module to be tested.

9. The double pulse test circuit according to claim 8, characterized in that: The switch module includes: a first switch tube and a second switch tube; The first switching tube and the second switching tube are both provided with anti-parallel diodes; The first switch tube and the second switch tube are connected in reverse series, and the anti-parallel diode of the second switch tube has the same current flow direction as that of the switch tube under test in the module under test; The second switch tube is normally off, the first switch tube is in a closed state before the first pulse ends, and is in an open state after the first pulse ends.

10. The double pulse test circuit according to any one of claims 4 to 9, characterized in that: Also includes: DC power supply; The DC power supply is connected in parallel with the DC bus capacitor.

11. A double pulse test system, characterized in that: include: A host computer, a control board, and a double pulse test circuit as claimed in any one of claims 4 to 10; wherein, The host computer is used to control the switch tube in the module to be tested and the action of the switch module in the double pulse test circuit through the control board.

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