Method for forming semiconductor pattern structure and processing method for semiconductor device

Abstract

The present disclosure provides a method for forming a semiconductor pattern structure and a processing method for a semiconductor device. The method for forming a semiconductor pattern structure includes the following steps. Perform an alignment operation to align a mask plate having a first preset pattern with a bottom alignment layer and obtain alignment parameters. Compensate the alignment parameters by using the read offset parameters to shift the alignment position of the mask plate. Control a lithography apparatus to perform a lithography process on a photoresist layer to pattern the photoresist layer based on the mask plate pattern. Finally, use the photoresist layer having the first preset pattern as a mask, and then control an etching apparatus to etch a dielectric layer to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer. The present disclosure can correct the position offset problem of the semiconductor pattern structure occurring in the subsequent etching process by means of lithography mask overlay compensation in the lithography process, and can significantly improve the yield of semiconductor devices.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor device processing. More specifically, the present disclosure can provide a method for forming a semiconductor pattern structure and a method for processing a semiconductor device. Background Art

[0002] The lithography and etching processes are the basic and core processes for manufacturing semiconductor devices. The lithography process can transfer a corresponding pattern onto a photosensitive thin film layer (photoresist) covering a semiconductor wafer through a photochemical reaction by using the geometric pattern on a mask. However, the pattern on the photosensitive thin film layer is not the final part of the semiconductor device, but only a stamp of the final circuit pattern. The etching process is used for pattern transfer to form a semiconductor pattern structure on a device layer. Generally speaking, as long as a corresponding pattern is formed at a corresponding position on the photoresist layer, a required semiconductor pattern structure can be obtained at a desired position on the device layer.

[0003] However, it is found in the actual process of semiconductor device processing that even when the pattern on the photoresist layer is exactly aligned with the pattern on the alignment layer (theoretically, the overlay error is zero), the semiconductor pattern etched on the device layer still has a problem of deviating from the desired position. Summary of the Invention

[0004] To solve the problem that the semiconductor pattern etched on the device layer deviates from the desired position, the present disclosure can provide a method for forming a semiconductor pattern structure and a method for processing a semiconductor device, achieving at least one technical purpose such as correcting the position of the semiconductor pattern structure etched on the device layer.

[0005] To achieve the above technical purpose, the present disclosure provides a method for forming a semiconductor pattern structure; the method may include but is not limited to at least one of the following steps.

[0006] First, control the lithography equipment to perform an alignment operation to align the mask with the first preset pattern with the bottom alignment layer, and obtain alignment parameters. Then, the pre-generated offset parameters can be read, and after correcting the alignment parameters using the offset parameters, control the lithography equipment to perform a movement operation to shift the alignment position of the mask. Secondly, based on the shifted mask, control the lithography equipment to perform lithography on the photoresist layer to pattern the photoresist layer based on the mask pattern. Finally, use the photoresist layer with the first preset pattern as a mask, and control the etching equipment to etch the dielectric layer to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer. Among them, the photoresist layer can be disposed on the dielectric layer; the process of pre-generating the offset parameters is as follows. Set the lithography alignment conditions, and after alignment, control the lithography equipment to perform lithography to form a second preset pattern on the first pretreatment film layer. Use the first pretreatment film layer with the second preset pattern as a mask, control the etching equipment to etch the second pretreatment film layer to etch out the second preset pattern structure on the second pretreatment film layer. Then compare the position of the second preset pattern structure on the second pretreatment film layer with the preset position, and generate offset parameters according to the comparison result.

[0007] To achieve the above technical objectives, the present disclosure also provides a processing method for semiconductor devices, which may include but is not limited to the method for forming a semiconductor pattern structure in any embodiment of the present disclosure.

[0008] The beneficial effects of the present disclosure are as follows:

[0009] The present disclosure can correct the problem of the position offset of the semiconductor pattern structure occurring in the subsequent etching process by means of lithography mask overlay compensation in the lithography process. For example, for the problem of the semiconductor pattern shift formed near the edge of the wafer, the present disclosure can achieve better results, greatly improving the electrical performance of the device. Especially for the peripheral circuit, the present disclosure can significantly improve the yield of semiconductor devices.

[0010] The present disclosure can form a semiconductor pattern structure at the desired position on the semiconductor device layer, and has outstanding advantages such as controllable position of the semiconductor pattern structure and high reliability of semiconductor device processing.

[0011] The technical solution provided by the present disclosure significantly improves the quality of the etching process for semiconductor device processing, helps to reduce the generation of defects, and greatly improves the yield of semiconductor device products. Description of the Drawings

[0012] Figure 1 A schematic diagram showing the setting of a plurality of alignment marks on the dicing lane in one or more embodiments of the present disclosure.

[0013] Figure 2Schematic diagrams showing the alignment of post-lithography alignment pattern marks with alignment marks on the bottom alignment layer in one or more embodiments of the present disclosure.

[0014] Figure 3 Schematic diagrams showing the misalignment state of non-vertical etching paths caused by different etching rates at different positions on the etched film layer in one or more embodiments of the present disclosure.

[0015] Figure 4 Schematic diagrams showing the misalignment state between the pattern structure position and the preset position due to different etching rates in one or more embodiments of the present disclosure.

[0016] Figure 5 Schematic diagrams showing the post-lithography state where the alignment position of the mask plate is offset according to the offset parameter in one or more embodiments of the present disclosure.

[0017] Figure 6 Schematic diagrams showing in one or more embodiments of the present disclosure based on Figure 5 the alignment state of the etching path formed after etching using the mask formed based on the offset mask plate.

[0018] Figure 7 Schematic diagrams showing in one or more embodiments of the present disclosure based on Figure 5 the semiconductor pattern structure formed on the etched film layer and aligned with the bottom alignment layer using the mask formed based on the offset mask plate. Detailed implementation manners

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0020] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0021] In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component therebetween. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0022] The present disclosure can provide a method for forming a semiconductor pattern structure to form a semiconductor pattern structure aligned with a bottom alignment layer on a target film layer (etching target film layer). A reference pattern is provided on the bottom alignment layer.

[0023] As Figure 1 , 2 shown, lithography alignment conditions are set. And after alignment, a lithography apparatus is controlled to perform lithography processing to form a second preset pattern on a first pretreatment film layer. Specifically, setting the lithography alignment conditions in the present disclosure includes: aligning using one or more alignment marks on the scribe lane of the wafer shown in Figure 1 , where the scribe lane is an interval structure between adjacent different chips on the wafer. It can be understood that in the specific implementation of the present disclosure, a semiconductor substrate can be provided, and then a second pretreatment film layer and a first pretreatment film layer can be formed above the semiconductor substrate, and the first pretreatment film layer can be formed on the second pretreatment film layer.

[0024] As Figure 3 shown, using the first pretreatment film layer having the second preset pattern as a mask, an etching apparatus is controlled to etch the second pretreatment film layer to etch out a second preset pattern structure on the second pretreatment film layer. It can be understood from the figure that when etching certain positions on the wafer (such as positions near the wafer edge), the etching path is sometimes in a non-vertical state. The non-vertical path directly leads to the misalignment problem between the semiconductor pattern structure and the bottom alignment layer, making the etching process uncontrollable and reducing the yield of semiconductor device products.

[0025] As Figure 4As shown, on the premise of complete alignment in the lithography process, the second preset pattern structure obtained by etching still shifts in a certain direction (shown as the lower left direction in the figure). This is caused by different etching rates at different positions on the wafer during etching and defects on the wafer surface (such as the slope generated by Edge Ring). For example, the etching rate difference between the wafer center and the wafer edge is relatively large, resulting in the semiconductor pattern structure obtained by etching being prone to shift in a certain direction. The present disclosure innovatively compensates the position of the semiconductor pattern structure based on the analysis result of the shift reason, and performs preprocessing (i.e., the above processing process) before the actual process of manufacturing semiconductor devices. The purpose of the preprocessing in the embodiments of the present disclosure is to obtain an offset parameter (Overlay Parameter) for characterizing the degree of shift. Although the pre-lithography process in the preprocessing process is a lithography process and the pre-etching process in the preprocessing process is an etching process, the pre-lithography process and the pre-etching process involved in the present disclosure are not used to manufacture semiconductor devices, but to obtain an offset parameter for compensating the position of the mask.

[0026] As Figure 3 、 4 shown, in the embodiments of the present disclosure, the position of the second preset pattern structure on the second preprocessing film layer is specifically compared with a preset position, and an offset parameter is generated according to the comparison result. More specifically, comparing the position of the second preset pattern structure on the second preprocessing film layer with the preset position and generating an offset parameter according to the comparison result include: reading the first position data of the preset position, and obtaining the second position data of the second preset pattern structure on the second preprocessing film layer by means of pattern check. The specific process of pattern check can be reasonably selected and used according to the actual situation, and will not be elaborated in the present disclosure. The corresponding first position data and second position data are subjected to difference calculation to generate an offset parameter according to the difference calculation result. The offset parameter of the present disclosure may specifically include, but is not limited to, the x-direction offset (Offset X), the y-direction offset (Offset Y), the x-direction scaling factor (Scale X), the y-direction scaling factor (Scale Y), the orthogonality value, and the mask rotation value (RROT X / Y), etc.

[0027] Next, the embodiments of the present disclosure perform the actual process of manufacturing semiconductor devices. Control the lithography equipment to perform an alignment operation to align the mask with the first preset pattern with the bottom alignment layer, and obtain alignment parameters under the alignment condition. Read the previously generated offset parameter, that is, through Figure 3 、 4The offset parameter obtained from the shown deviation is used to correct the acquired alignment parameter. Here, the alignment parameter is the overlay data when the mask and the scribeline alignment marks of the bottom alignment layer are aligned. The present disclosure corrects the overlay data under the alignment conditions using the offset parameter.

[0028] It can be understood that the present disclosure can provide a semiconductor substrate, and then a dielectric layer and a photoresist layer are sequentially formed above the semiconductor substrate. It should be understood that the first pretreatment film layer involved in the present disclosure is the same as or different from the photoresist layer, and the second pretreatment film layer is the same as or different from the dielectric layer, and the second preset pattern is the same as or different from the first preset pattern. The photoresist layer is formed on the dielectric layer, and the dielectric layer can be, for example, a silicon nitride layer or a silicon oxide layer, etc.

[0029] As Figure 5 shown, the movement of the lithography apparatus is controlled based on the corrected alignment parameter to cause the alignment position of the mask to shift. It should be understood that "the movement of the lithography apparatus" means moving the wafer or the mask by the lithography apparatus. That is, there are two ways to "cause the alignment position of the mask to shift" in the present disclosure: (1) The more common way is that after the lithography apparatus moves the wafer, the alignment position shifts; or (2) after the lithography apparatus moves the mask, the alignment position shifts. It can be seen that in the present disclosure, after aligning the mask with the bottom alignment layer, the alignment position of the mask is moved, and after the movement, the mask is not directly aligned with the bottom alignment layer. Based on the mask that has deviated from the alignment position, the lithography apparatus is controlled to perform a lithography process on the photoresist layer to pattern the photoresist layer based on the mask pattern at this position.

[0030] As Figure 6 shown, in the embodiment of the present disclosure, next, the photoresist layer with the first preset pattern is used as a mask, and the etching apparatus is controlled to etch the dielectric layer to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer. Through Figure 6 、 Figure 7 it can be seen that even if the etching rates at different positions on the wafer are different, the present disclosure can still form a semiconductor pattern structure aligned with the bottom alignment layer. It can be seen that the present disclosure can align a non-vertical pattern with the bottom alignment layer, thereby effectively solving the overlay error (RealPattern Overlay) problem existing in the real pattern structure.

[0031] It is understandable that the present disclosure can also provide a method for processing a semiconductor device, and the processing method includes the method for forming a semiconductor pattern structure in any embodiment of the present disclosure. The semiconductor devices involved in the present disclosure may include, but are not limited to, semiconductor memory devices or logic devices, etc. The semiconductor memory device may be, for example, a dynamic random access memory (DRAM, Dynamic Random Access Memory). The dynamic random access memory can include a plurality of memory cells arranged in a matrix structure, and each memory cell is composed of a transistor and a semiconductor capacitor controlled by the transistor. The semiconductor device provided based on the technical solution of the present disclosure can be applied to an electronic device, and the electronic device may include, but are not limited to, a smart phone, a computer, a tablet computer, a wearable device, an artificial intelligence device, and a mobile power supply, etc. In addition, each film layer involved in the present disclosure can be formed directly or indirectly on a semiconductor substrate. The semiconductor substrate may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG), etc.

[0032] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. with the desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0033] The above embodiments of the present disclosure have been described. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A method for forming a semiconductor pattern structure, characterized in that, Including: Controlling a lithography apparatus to perform an alignment operation to align a mask having a first preset pattern with a bottom alignment layer, and obtaining alignment parameters; Reading offset parameters generated in advance; After correcting the alignment parameters by using the offset parameters, controlling the lithography apparatus to perform a moving operation so that the alignment position of the mask is offset; Controlling the lithography apparatus to perform a lithography process on a photoresist layer to pattern the photoresist layer based on the mask pattern; Using the photoresist layer having the first preset pattern as a mask, controlling an etching apparatus to etch a dielectric layer to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer; Generating the offset parameters in the following manner: Setting lithography alignment conditions, and after alignment, controlling the lithography apparatus to perform a lithography process to form a second preset pattern on a first pretreatment film layer; Using the first pretreatment film layer having the second preset pattern as a mask, controlling an etching apparatus to etch a second pretreatment film layer to etch out a second preset pattern structure on the second pretreatment film layer; Comparing the position of the second preset pattern structure on the second pretreatment film layer with a preset position and generating the offset parameters according to the comparison result.

2. The method for forming a semiconductor pattern structure according to claim 1, wherein, The comparing the position of the second preset pattern structure on the second pretreatment film layer with a preset position and generating the offset parameters according to the comparison result includes: Reading first position data of the preset position; Obtaining second position data of the second preset pattern structure on the second pretreatment film layer by means of pattern inspection; Performing a difference calculation on the corresponding first position data and the second position data to generate the offset parameters according to the difference calculation result.

3. The method for forming a semiconductor pattern structure according to claim 1 or 2, characterized in that, The setting the lithography alignment conditions includes: Performing alignment by using one or more alignment marks on a scribe lane.

4. The method for forming a semiconductor pattern structure according to claim 1, wherein The first pretreatment film layer is the same as or different from the photoresist layer.

5. The method for forming a semiconductor pattern structure according to claim 1, wherein The second pretreatment film layer is the same as or different from the dielectric layer.

6. The method for forming a semiconductor pattern structure according to claim 1, wherein The second preset pattern is the same as or different from the first preset pattern.

7. The method for forming a semiconductor pattern structure according to claim 1, wherein, The offset parameters include an x-direction offset amount, a y-direction offset amount, an x-direction scaling amount, a y-direction scaling amount, an orthogonal value, and a mask rotation value.

8. The method for forming a semiconductor pattern structure according to claim 1, wherein, The photoresist layer is formed on the dielectric layer.

9. A method for fabricating a semiconductor device, characterized in that Including the method for forming a semiconductor pattern structure according to any one of claims 1 to 8.

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