Memory controller and method of operating the memory controller

Abstract

The present application provides a memory controller for controlling a memory device. The memory controller includes: a workload detector configured to determine a change in workload based on a request for change received from a host or a clock change received from an external device; a device performance controller configured to determine read performance based on a ratio of a size of data output to the host per preset cycle to a size of data requested from the host if the workload is determined to have changed, and configured to output a read-ahead (RLA) command to the memory device based on the determined read performance; a buffer memory configured to store data read from the memory device in response to an RLA command; and a memory size controller configured to control the size of the buffer memory. The RLA command instructs outputting data frequently requested from the host.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0023616, filed on February 22, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a memory controller and a method of operating the memory controller. Background Art

[0004] Generally, a storage device is a device that stores data under the control of a host device such as a computer, a smartphone, or a smart tablet. Depending on the type of device configured to store data, examples of storage devices can be divided into devices that store data in a magnetic disk, such as a hard disk drive (HDD), and devices that store data in a semiconductor memory (particularly a non-volatile memory), such as a solid-state drive (SSD) or a memory card.

[0005] The storage device may include a memory device storing data, and a memory controller configured to store the data in the memory device. The memory device may be divided into a volatile memory and a non-volatile memory. Representative examples of non-volatile memories may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. Summary of the invention

[0006] Various embodiments of the present disclosure relate to a memory controller and a method of operating the memory controller, aiming to improve the performance of a memory device by changing the size of a buffer memory according to the read performance of the memory device.

[0007] Embodiments of the present disclosure may provide a memory controller for controlling a memory device, the memory controller comprising: a workload detector configured to determine a change in the workload based on a request for change received from a host or a clock change received from an external device; a device performance controller configured to determine a read performance based on a ratio of a size of data output to the host per preset cycle to a size of data requested by the host if the workload is determined to have changed, and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance; a buffer memory configured to store data read from the memory device in response to the RLA command; and a memory size controller configured to control the size of the buffer memory, wherein the RLA command indicates outputting data frequently requested from the host.

[0008] Embodiments of the present disclosure may provide a method of operating a memory controller configured to control a memory device, the method comprising: determining a change in workload based on a request for change received from a host or a clock change received from an external device; if the workload is determined to have changed, determining a read performance based on a ratio of a size of data output to the host per preset cycle to a size of data requested by the host; based on the determined read performance, outputting a read-ahead (RLA) command to the memory device; and storing data read from the memory device in response to the RLA command in a buffer memory, wherein the RLA command indicates outputting data frequently requested from the host.

[0009] Embodiments of the present disclosure may provide a memory system, comprising: a memory device configured to store data; a cache memory configured to cache data read from the device and to be provided to the outside; and a controller configured to: when the workload of the system is heavy, perform a read-ahead (RLA) operation on the data stored in the device according to the current read performance of the system, and when the workload of the system is light, adjust the size of the cache memory according to the current read performance of the system, wherein the controller is further configured to adjust the size according to the current read performance of the system during the RLA operation, and wherein the current read performance is a ratio of a first amount to a second amount during a current time period, the first amount being the amount of data output from the system in response to one or more requests from the outside, and the second amount being the amount of data requested by the request. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1A diagram of a configuration of a memory device.

[0012] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 2 Schematic diagram of an embodiment of a memory cell array.

[0013] Figure 4 is a diagram illustrating a process of outputting an RLA command according to an embodiment of the present disclosure.

[0014] Figure 5 is a diagram illustrating a method of determining read performance according to an embodiment of the present disclosure.

[0015] Figure 6 The embodiment according to the present disclosure is shown Figure 4 The configuration of the buffer memory.

[0016] Figure 7 A method of changing the size of a buffer memory according to an embodiment of the present disclosure is illustrated.

[0017] Figure 8 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0018] Fig. 9 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0019] Fig.10 The present invention is a diagram showing an embodiment of the present invention. Figure 1 Schematic diagram of an embodiment of a memory controller.

[0020] Fig.11 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0021] Fig.12 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0022] Fig.13 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0023] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification are only used to describe the embodiments of the present disclosure. These descriptions should not be interpreted as being limited to the embodiments described in this specification.

[0024] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0025] Reference Figure 1, the storage device 50 may include a memory device 100 and a memory controller 200 .

[0026] The storage device 50 may be a device configured to store data under the control of the host 300 such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0027] The storage device 50 may be manufactured as any of various types of storage devices according to a host interface as a communication system for communicating with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices such as an SSD, an MMC, eMMC, RS-MMC or micro MMC type multimedia card, an SD, mini SD, micro SD type secure digital card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0028] The memory device 50 may be manufactured in the form of any of various package types. For example, the memory device 50 may be manufactured in the form of any of various package types such as: a stacked package (POP) type, a system-in-package (SIP) type, a system-on-chip (SOC) type, a multi-chip package (MCP) type, a chip-on-board (COB) type, a wafer-level fabrication package (WFP) type, and a wafer-level stacked package (WSP) type.

[0029] The memory device 100 may store data therein. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells configured to store data therein. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. The plurality of memory cells may form a plurality of pages. In an embodiment, each page may be a unit for storing data in the memory device 100 or reading stored data from the memory device 100. Each memory block may be a unit for erasing data.

[0030] In an embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). In this specification, for the sake of description, the memory device 100 is a NAND flash memory.

[0031] The memory device 100 may be implemented in a two-dimensional array structure or a three-dimensional array structure. Hereinafter, although a three-dimensional array structure will be described for the purpose of illustration, the present disclosure is not limited to the three-dimensional array structure. The present disclosure may be applied not only to a flash memory in which a charge storage layer is formed of a conductive floating gate (FG), but also to a charge trap flash (CTF) memory in which a charge storage layer is formed of an insulating layer.

[0032] In an embodiment, the memory device 100 may be operated in a single-level cell (SLC) mode in which one data bit is stored in each memory cell. Alternatively, the memory device 100 may be operated in a mode in which at least two data bits are stored in each memory cell. For example, the memory device 100 may be operated in a multi-level cell (MLC) mode in which two data bits are stored in each memory cell, in a triple-level cell (TLC) mode in which three data bits are stored in each memory cell, or in a quad-level cell (QLC) mode in which four data bits are stored in each memory cell.

[0033] The memory device 100 can receive a command and an address from the memory controller 200, and access the area selected by the address in the memory cell array. That is, the memory device 100 can perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 can perform a write (programming) operation, a read operation, or an erase operation in response to the received command. For example, when a programming command is received, the memory device 100 can program data in the area selected by the address. If a read command is received, the memory device 100 can read data from the area selected by the address. If an erase command is received, the memory device 100 can erase data from the area selected by the address.

[0034] The memory controller 200 may control the overall operations of the memory device 50 .

[0035] The memory controller 200 may run firmware when the power supply voltage is applied to the memory device 50. In the case where the memory device 100 is a flash memory device, the memory controller 200 may run firmware for controlling communication between the host 300 and the memory device 100, such as a flash translation layer (FTL).

[0036] In an embodiment, the memory controller 200 may include firmware (not shown) that receives data and a logical block address (LBA) from the host 300 and converts the LBA into a physical block address (PBA) indicating an address of a memory cell in which the data is to be stored, the memory cell being included in the memory device 100. The memory controller 200 may store a logical-physical address mapping table indicating a mapping relationship between the logical block address LBA and the physical block address PBA in the buffer memory 230.

[0037] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. For example, if a program request is received from the host 300, the memory controller 200 may change the program request into a program command, and provide the program command, the PBA, and the data to the memory device 100. If a read request and an LBA are received from the host 300, the memory controller 200 may change the read request into a read command, select a PBA corresponding to the LBA, and provide the read command and the PBA to the memory device 100. If an erase request and an LBA are received from the host 300, the memory controller 200 may change the erase request into an erase command, select a PBA corresponding to the LBA, and provide the erase command and the PBA to the memory device 100.

[0038] In an embodiment, the memory controller 200 may autonomously generate a program command, an address, and data and transmit them to the memory device 100 without a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0039] In an embodiment, the memory controller 200 may include a workload detector 210. The workload detector 210 may detect the workload according to a request received from the host 300, and detect the workload according to a change in a clock CLK applied to the memory device 50.

[0040] For example, the workload detector 210 may detect that the workload has been changed in the case of receiving a sequential read request or a sequential write request from the host 300. Since an operation corresponding to the sequential read request or the sequential write request requires more operations than other requests, the workload detector 210 may confirm that the workload has been changed after receiving the sequential read request or the sequential write request.

[0041] For example, if the clock CLK applied to the memory device 50 is changed, the workload detector 210 can detect that the workload has changed. Since the speed of performing operations varies according to the clock CLK, the workload detector 210 can detect that the workload has changed based on the changed clock CLK.

[0042] In an embodiment, the memory controller 200 may include a device performance controller 220. The device performance controller 220 may detect the read performance of the memory device 50.

[0043] For example, the device performance controller 220 may detect the read performance based on the ratio of the size of data output to the host 300 during the reference time to the size of data requested from the host 300. As the ratio increases, the read performance may be higher. Conversely, as the ratio decreases, the read performance may be lower.

[0044] In an embodiment, the memory controller 200 may include a buffer memory 230. The memory controller 200 may control data exchange between the host 300 and the buffer memory 230. Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory 230. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory 230, and thereafter transmit the data temporarily stored in the buffer memory 230 to the memory device 100. The size of the buffer memory 230 may be variable.

[0045] In various embodiments, the buffer memory 230 may be used as an operating memory or a cache memory of the memory controller 200. The buffer memory 230 may store codes or commands to be executed by the memory controller 200. Alternatively, the buffer memory 230 may store data to be processed by the memory controller 200.

[0046] In an embodiment, the buffer memory 230 may be implemented by an SRAM or DRAM such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR4 SDRAM, fourth generation low power double data rate (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) or Rambus dynamic random access memory (RDRAM).

[0047] In various embodiments, the buffer memory 230 may be coupled to the outside of the storage device 50. In this case, a volatile memory device coupled to the outside of the storage device 50 may perform the function of the buffer memory 230.

[0048] In an embodiment, the memory controller 200 may include a memory size controller 240. The memory size controller 240 may control the size of the buffer memory 230.

[0049] For example, based on the read performance detected when the workload is changed, the size of the buffer memory 230 may be changed. More specifically, the memory size controller 240 may increase the size of the buffer memory 230 until the read performance is maximized.

[0050] In an embodiment, when the workload is low, a read-ahead (RLA) operation may be performed so that data frequently read to the host 300 is pre-read from the storage device 50 , thereby implementing a cache read operation.

[0051] For example, if the workload reaches a preset workload, a read-ahead (RLA) command for an RLA operation may be output to the memory device 100 at a preset time, and data corresponding to a preset size of the buffer memory 230 may be received from the memory device 100 .

[0052] However, when an unexpected workload occurs or the clock CLK is changed, the read performance may not be improved due to the read-ahead (RLA) operation.

[0053] For example, the preset size of the buffer memory 230 may be 1MB. However, in this case, when the storage device 50 receives a read request indicating to read data corresponding to a size greater than 1MB from the host 300, the read performance may not be improved even if the read-ahead operation is performed.

[0054] Therefore, the present disclosure proposes a method of variably setting the size of the buffer memory 230 based on the read performance after detecting a change in workload.

[0055] In an embodiment, the memory controller 200 may control at least two or more memory devices. In this case, the memory controller 200 may control the memory devices in an interleaved manner to improve operation performance.

[0056] The host 300 can communicate with the storage device 50 using at least one of various communication standards or interfaces such as: universal serial bus (USB), serial AT attachment (SATA), serial SCSI (SAS), high-speed inter-chip (HSIC), small computer system interface (SCSI), peripheral component interconnect (PCI), PCI express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM), and load reduced DIMM (LRDIMM) communication methods.

[0057] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 A diagram of a configuration of a memory device.

[0058] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0059] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 through a row line RL. The plurality of memory blocks BLK1 to BLKz may be connected to a page buffer group 123 through bit lines BL1 to BLn. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. The memory cells connected to the same word line may be defined as one page. Therefore, each memory block may include a plurality of pages.

[0060] The row line RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0061] Each of the memory cells included in the memory cell array 110 may be formed of a single-level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0062] The peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0063] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0064] The row decoder 121 is connected to the memory cell array 110 through a row line RL. The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word line may include a normal word line and a dummy word line. In an embodiment, the row line RL may further include a pipeline selection line.

[0065] The row decoder 121 may be configured to decode the row address RADD received from the control logic 130. The row decoder 121 may select at least one of the memory blocks BLK1 to BLKz in response to the decoded address. The row decoder 121 may select at least one word line WL of the selected memory block in response to the decoded address, thereby applying the voltage generated by the voltage generator 122 to the at least one word line WL.

[0066] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line, and apply a program pass voltage having a level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line, and apply a verification pass voltage higher than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line, and apply a read pass voltage higher than the read voltage to unselected word lines.

[0067] In an embodiment, an erase operation of the memory device 100 may be performed based on a memory block. During the erase operation, the row decoder 121 may select a memory block in response to a decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to a word line coupled to the selected memory block.

[0068] The voltage generator 122 may operate under the control of the control logic 130. The voltage generator 122 may generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. In detail, the voltage generator 122 may generate various operation voltages Vop for a program operation, a read operation, and an erase operation in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130.

[0069] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated from the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0070] In an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

[0071] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130 .

[0072] The generated voltage may be supplied to the memory cell array 110 through the row decoder 121 .

[0073] The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn may operate under the control of the control logic 130. In detail, the first to nth page buffers PB1 to PBn may operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verification operation, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense the voltage or current of the bit lines BL1 to BLn.

[0074] In detail, during a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn may transmit data DATA received through the data input / output circuit 125 to a selected memory cell through the first to nth bit lines BL1 to BLn. Based on the transmitted data DATA, the memory cells in the selected page are programmed. During a program verification operation, the first to nth page buffers PB1 to PBn may read page data by sensing a voltage or current received from a selected memory cell through the first to nth bit lines BL1 to BLn.

[0075] During a read operation, the first to nth page buffers PB1 to PBn may read data DATA from memory cells in a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the data input / output circuit 125 under the control of the column decoder 124 .

[0076] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or apply an erase voltage to the first to nth bit lines BL1 to BLn.

[0077] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0078] The input / output circuit 125 can convert the Figure 1 The memory controller described ( Figure 1 The memory controller 200 may transmit a command CMD or an address ADDR received by the memory controller 200 to the control logic 130, or may exchange data DATA with the column decoder 124.

[0079] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT, and may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current, and output a pass signal PASS or a fail signal FAIL.

[0080] The control logic 130 may output an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit signal VRYBIT in response to a command CMD and an address ADDR, thereby controlling the peripheral circuit 120. For example, the control logic 130 may control a read operation of a selected memory block in response to a sub-block read command and an address. In addition, the control logic 130 may control an erase operation of a selected sub-block included in a selected memory block in response to a sub-block erase command and an address. In addition, the control logic 130 may determine whether a verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0081] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 2 Schematic diagram of an embodiment of a memory cell array.

[0082] Reference Figure 2 and Figure 3 , Figure 3 It is shown Figure 2 1 is a circuit diagram of a memory block BLKa among a plurality of memory blocks BLK1 to BLKz included in a memory cell array 110.

[0083] The first selection line, the word line, and the second selection line arranged in parallel may be connected to the memory block BLKa. For example, the word line may be arranged in parallel between the first and second selection lines. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0084] In more detail, the memory block BLKa may include a plurality of strings connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be respectively connected to the plurality of strings, and the source line SL may be commonly connected to the plurality of strings. The strings may have the same configuration; therefore, the string ST connected to the first bit line BL1 will be described in detail by way of example.

[0085] The string ST may include a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST connected in series with each other between a source line SL and a first bit line BL1. Each string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and each string ST may include a greater number of memory cells than the number of memory cells F1 to F16 shown in the figure.

[0086] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells F1 to F16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors included in different strings may be connected to the source select line SSL, the gates of the drain select transistors may be connected to the drain select line DSL, and the gates of the memory cells F1 to F16 may be connected to a plurality of word lines WL1 to WL16. Among the memory cells included in different strings, a group of memory cells connected to the same word line may be referred to as a physical page PPG. Therefore, the number of physical pages included in the memory block BLKa may correspond to the number of word lines WL1 to WL16.

[0087] Each memory cell can store 1 bit of data. This memory cell is generally referred to as a single-layer cell (SLC). In this case, each physical page PPG can store the data of a single logical page LPG. The data of each logical page LPG may include data bits corresponding to the number of memory cells included in a single physical page PPG. Optionally, each memory cell can store 2 or more bits of data. This memory cell is generally referred to as a multi-layer cell (MLC). In this case, each physical page PPG can store the data of two or more logical pages LPG.

[0088] A memory cell configured so that 2 or more bits of data are stored in each memory cell is referred to as a multi-layer cell (MLC). Recently, as the number of bits of data stored in each memory cell increases, a multi-layer cell (MLC) refers to a memory cell storing 2 bits of data. A memory cell in which 3 or more bits of data are stored is referred to as a triple-layer cell (TLC), and a memory cell in which 4 or more bits of data are stored is referred to as a quad-layer cell (QLC). In addition, a memory cell storing multi-bit data is being developed. The present embodiment can be applied to a memory device 100 in which 2 or more bits of data are stored.

[0089] In an embodiment, the memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction.

[0090] Figure 4 is a diagram illustrating a process of outputting an RLA command according to an embodiment of the present disclosure.

[0091] Reference Figure 4 , Figure 4 A method is shown in which an RLA command RLA_CMD for improving read performance is output to the memory device 100 , and read data READ_DATA corresponding to the RLA command RLA_CMD is received from the memory device 100 . Figure 4 The memory controller 200 may include a workload detector 210 , a device performance controller 220 , and a buffer memory 230 .

[0092] In an embodiment, the workload detector 210 may receive a read request READ_REQ from the host 300. The read request READ_REQ may be a request indicating reading data stored in the memory device 100. The read request READ_REQ may be a normal read request or a sequential read request. The normal read request may be a request indicating reading data stored in a specific location of the memory device 100, and the sequential read request may be a request indicating reading data continuously stored in the memory device 100.

[0093] When the read request READ_REQ received from the host 300 is a sequential read request, the workload detector 210 can detect that the workload has been changed. When the read request READ_REQ received from the host 300 is a sequential read request, data stored continuously in the memory device 100 can be read. Therefore, a larger amount of data can be read than when data is read in response to a normal read request. Therefore, since a large amount of data needs to be read, the workload may be changed, and the workload detector 210 can detect that the workload has been changed through the received read request READ_REQ.

[0094] In an embodiment, when the workload detector 210 detects that the workload has been changed, the workload detector 210 may generate workload change information WLC_INF and then output it to the device performance controller 220 .

[0095] In an embodiment, the workload detector 210 may receive a clock CLK from an external device. If the cycle of the clock CLK received from the external device is changed, the workload detector 210 may detect that the workload has been changed. Since the cycle of the clock CLK is changed and thus the workload is changed in the storage device 50 (see Figure 1 ) is changed, so the workload detector 210 can detect that the workload has been changed based on the changed clock CLK.

[0096] Even when the clock CLK is changed, the workload detector 210 may generate the workload change information WLC_INF and output it to the device performance controller 220 .

[0097] In an embodiment, if the device performance controller 220 receives the workload change information WLC_INF from the workload detector 210, the device performance controller 220 may detect the storage device 50 (see Figure 1 ) performance. For example, the device performance controller 220 may detect the performance of the storage device 50 (see Figure 1 )’s read performance.

[0098] More specifically, the device performance controller 220 may detect the read performance based on the ratio of the size of the read data READ_Data output to the host 300 during the reference time to the size of the read data READ_DATA requested from the host 300. In an embodiment, as the ratio increases, the read performance may be higher. Conversely, as the ratio decreases, the read performance may be lower. That is, the more the read data READ_DATA requested from the host 300 is output to the host 300 during the reference time, the higher the read performance may be.

[0099] The device performance controller 220 may output an RLA command RLA_CMD for performing an RLA operation to the memory device 100 based on the result of detecting the read performance. The RLA operation may be an operation of pre-caching data in the buffer memory 230 even in the absence of a data request from the host 300. The target of the RLA operation may be data frequently requested from the host 300. The data pre-cached in the buffer memory 230 through the RLA operation may be immediately provided to the host 300 in response to a request for data from the host 300.

[0100] For example, if the read performance is maximum, there is no need to perform a read-ahead (RLA) operation. Therefore, the device performance controller 220 does not need to output the RLA command RLA_CMD to the memory device 100. However, if the read performance is not maximum, the device performance controller 220 may output the RLA command RLA_CMD to the memory device 100 to pre-cache data frequently requested from the host 300 through the read-ahead (RLA) operation in the buffer memory 230.

[0101] In an embodiment, the memory device 100 may output data frequently requested from the host 300 to the buffer memory 230 in response to the RLA command RLA_CMD, and the buffer memory 230 may store the received data. The data stored in the buffer memory 230 may be output to the host 300 through the device performance controller 220.

[0102] Therefore, when the workload is changed, a read-ahead (RLA) operation may be performed based on the detected read performance.

[0103] However, if the area where data received from the memory device 100 is to be stored during the read-ahead (RLA) operation is not sufficiently ensured, the read performance may not be improved. Therefore, the present disclosure proposes a method of changing the size of the buffer memory 230 based on the read performance detected after performing the read-ahead (RLA) operation.

[0104] Figure 5 is a diagram illustrating a method of determining read performance according to an embodiment of the present disclosure.

[0105] Reference Figure 5 , Figure 5 Shows Figure 4 The device performance controller 220 detects a method of reading performance READ_PF.

[0106] In an embodiment, if the device performance controller 220 (see Figure 4) receives information indicating that the workload has been changed from the workload detector 210, then the device performance controller 220 (see Figure 4 ) can detect the read performance READ_PF. When the slave host 300 (see Figure 4 ) receives a sequential read request or the clock CLK received from the external device is changed, the change in workload can be detected.

[0107] In an embodiment, the read performance READ_PF may be determined as output to the host 300 during a reference time (see Figure 4 ) and the size of the request data REQ_DATA requested from the host 300 (see Figure 4 ) ratio. The request data REQ_DATA is the same as the request data from the host 300 (see Figure 4 ) corresponding to the read request, and refers to the data from the memory device 100 (see Figure 4 ) requested data.

[0108] More specifically, when the ratio of the read data READ_DATA to the request data REQ_DATA is “1”, the read performance READ_PF may be the maximum MAX. However, when the ratio of the read data READ_DATA to the request data REQ_DATA is not “1”, the read performance READ_PF may not be the maximum NOT MAX.

[0109] The present disclosure proposes a method of changing the size of a buffer memory to set the read performance READ_PF to the maximum.

[0110] Figure 6 The embodiment according to the present disclosure is shown Figure 4 The configuration of the buffer memory.

[0111] Figure 6 Shows Figure 4 The buffer memory 230 includes a default area DEFAULT and a variable area VARIABLE. The default area DEFAULT is in the storage device 50 (see Figure 1 ) is set to a default size in the initialization step of the variable area VARIABLE from Figure 4 The area changes after the device performance controller 220 outputs the RLA command RLA_CMD.

[0112] In an embodiment, the slave memory device 100 (see Figure 4 ) is stored in the default area DEFAULT. The data stored in the default area DEFAULT can be output to the host 300 (see Figure 4 ).

[0113] In an embodiment, in order to improve the read performance, the size of the buffer memory 230 may be variable. For example, the size of the buffer memory 230 may be variable. Figure 4 )The data read is stored in the variable area VARIABLE and the default area DEFAULT.

[0114] More specifically, in the device performance controller 220 (see Figure 4 ) outputs the RLA command RLA_CMD, the device performance controller 220 (see Figure 4 ) can detect the read performance again. After the RLA command RLA_CMD is output, the host 300 can be output to the host 300 during the reference time (see Figure 4 ) is the same as the size of the read data READ_Data from the host 300 (see Figure 4 )The read performance is detected by comparing the size of the read data READ_DATA requested.

[0115] When the device performance controller 220 (see Figure 4 ) detects that the read performance is not maximum, a portion of the variable area VARIABLE may be allocated as slave memory device 100 (see Figure 4 ) is an area where the read data is to be stored. The size allocated to the variable area VARIABLE can be preset.

[0116] Reference Figure 6 ,when Figure 4 When the device performance controller 220 detects that the read performance is not maximum after outputting the RLA command RLA_CMD, an area corresponding to the size S601 which is a preset size in the variable area VARIABLE may be allocated as an area to be stored with data.

[0117] After that, Figure 4 The device performance controller 220 may detect the read performance until the read performance reaches a maximum, and may allocate an area corresponding to a size S601 as a preset size in the variable area VARIABLE before the read performance reaches a maximum as an area for storing data.

[0118] Therefore, the read performance can be improved by sequentially increasing the portion of the variable area VARIABLE where data is to be stored until the read performance reaches a maximum.

[0119] Figure 7 A method of changing the size of a buffer memory according to an embodiment of the present disclosure is shown.

[0120] Figure 7 Show Figure 4The device performance controller 220 outputs the RLA command RLA_CMD to the memory device 100 and receives the read data READ_DATA corresponding to the RLA command RLA_CMD from the memory device 100 . Figure 7 The memory controller 200 may include a workload detector 210 , a device performance controller 220 , a buffer memory 230 , and a memory size controller 240 .

[0121] In an embodiment, in response to the RLA command RLA_CMD, read data READ_DATA may be received from the memory device 100. The read data READ_DATA corresponding to the RLA command RLA_CMD may be data frequently output to the host 300. The read data READ_DATA read from the memory device 100 may be stored in the buffer memory 230 and then output to the host 300 through the device performance controller 220.

[0122] If read data READ_DATA corresponding to the RLA command RLA_CMD is received from the memory device 100, the corresponding data does not need to be read again from the memory device 100, so that the read performance can be improved. However, it is necessary to perform an operation for maximizing the read performance.

[0123] For example, after receiving the read data READ_DATA corresponding to the RLA command RLA_CMD from the memory device 100, the device performance controller 220 may detect the read performance again at every preset cycle. The read performance may be determined by the ratio of the size of data output to the host 300 during the reference time to the size of data requested from the host 300. When the ratio of the size is close to "1", the read performance may be improved.

[0124] When the device performance controller 220 detects that the read performance is maximum, the device performance controller 220 may not perform a separate operation. Since the read performance is maximum, there may be no need to perform an operation for setting the read performance to the maximum.

[0125] However, when the device performance controller 220 detects that the read performance is not maximum, it may output read performance information RP_INF indicating that the read performance is not maximum to the memory size controller 240 .

[0126] The memory size controller 240 may output size setting information SIZE_SET_INF for changing the size of the buffer memory 230 based on the read performance information RP_INF to the buffer memory 230. The size setting information SIZE_SET_INF may be information indicating that a variable area of ​​the buffer memory 230 is allocated as an area to be stored with data of a preset size. Therefore, the buffer memory 230 may allocate a part of the variable area as an area to be stored with data based on the size setting information SIZE_SET_INF.

[0127] Thereafter, data read from the memory device 100 may be stored in a portion of the variable area of ​​the buffer memory 230 as well as the default area.

[0128] Therefore, an area where data received from the memory device 100 is to be stored may be ensured by changing the size of the buffer memory 230 , and read performance may be improved by increasing data output to the host 300 during the reference time.

[0129] In an embodiment, after the size of the buffer memory 230 is changed, the workload detector 210 may detect that the workload has been changed again. For example, when the read request READ_REQ received from the host 300 is changed from a sequential read request to a normal read request again, or the clock cycle received from the external device is changed, the workload detector 210 may detect that the workload has been changed.

[0130] The workload detector 210 may output workload change information WLC_INF indicating that the workload has been changed to the device performance controller 220. If the device performance controller 220 receives the workload change information WLC_INF, it may stop outputting the RLA command RLA_CMD, and may detect the read performance again. If it is detected that the read performance is maximum, the device performance controller 220 may stop the operation. In addition, if it is detected that the read performance is not maximum, the device performance controller 220 may output read performance information RP_INF indicating the read performance to the memory size controller 240 again, and then may allocate an area in the variable area of ​​the buffer memory 230 for new data to be stored again.

[0131] Figure 8 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0132] Reference Figure 8In operation S801, the memory controller may detect the workload. More specifically, when a request received from the host is changed from a normal read request to a sequential read request, a request received from the host is changed from a sequential read request to a normal read request, or a clock received from an external device is changed, the memory controller may detect the workload.

[0133] In operation S803, the memory controller may determine whether the workload has been changed. If the workload has not been changed (No), the process proceeds to operation S801 again, and the memory controller detects the workload. If the workload has been changed (Yes), the process proceeds to operation S805.

[0134] In operation S805, the memory controller may detect the read performance. The read performance may be determined based on a ratio of the size of data output to the host during the reference time to the size of data requested from the host. For example, when the size of data output to the host during the reference time is equal to the size of data requested from the host, the read performance may be maximum. In other words, as the size of data output to the host during the reference time increases, the read performance may be enhanced.

[0135] In operation S807, the memory controller may determine whether the read performance is maximum. When the read performance is maximum (yes), the process may proceed to operation S801 again so that the memory controller can detect the workload. However, when the read performance is not maximum (no), the process proceeds to operation S809.

[0136] In operation S809, the memory controller may output an RLA command. The RLA command may be a command instructing to output in advance data frequently requested from the host and frequently output. The data output in response to the RLA command may be stored in a buffer memory in the memory controller.

[0137] In an embodiment, data output in response to an RLA command is stored in a buffer memory, so that when the same data is subsequently requested to be read from the host, the memory controller can output the data stored in the buffer memory to the host without outputting a command to read the corresponding data to the memory device. Therefore, since the operation of reading the data stored in the memory device can be omitted, the time required for the read operation can be reduced and the read performance can be improved.

[0138] Fig. 9 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0139] Reference Figure 8 and Fig. 9 , Fig. 9 Shown in Figure 8Operation S809 is an operation after the memory controller outputs the RLA command to the memory device.

[0140] In operation S901, the memory controller may detect read performance at each preset cycle. The read performance may be determined based on a ratio of the size of data output to the host during a reference time to the size of data requested from the host. For example, when the size of data output to the host during the reference time is equal to the size of data requested from the host, the read performance may be maximum. That is, as the size of data output to the host during the reference time increases, the read performance may be enhanced.

[0141] In an embodiment, if the data corresponding to the RLA command is stored in the buffer memory in the memory controller, the data stored in the buffer memory does not need to be read from the memory device again. Therefore, the read performance can be improved. However, an operation for maximizing the read performance can be performed.

[0142] In operation S903, the memory controller may determine whether the read performance is maximum. The case where the read performance is maximum may refer to a case where the size of data output to the host during the reference time is equal to the size of data requested from the host. If the determined read performance is not maximum (N), the process proceeds to operation S905. If the determined read performance is maximum (Y), the process proceeds to operation S907.

[0143] In operation S905, the memory controller may increase the size of the buffer memory. For example, the memory controller may increase the size of the buffer memory by allocating an area in which data of a preset size is to be stored in a variable area among a default area and a variable area included in the buffer memory. By increasing the size of the buffer memory, more data output from the memory device may be stored in the buffer memory. Therefore, since more data corresponding to the RLA command is stored in the buffer memory and there is no need to read the data from the memory device, the time required for the read operation is reduced, thereby improving the read performance.

[0144] In operation S907, the memory controller may maintain the size of the buffer memory. Since the read performance is maximum, the size of the buffer memory may be maintained at a previously set size.

[0145] In operation S909, the memory controller may determine whether the workload has been changed. More specifically, the workload may be changed when a request received from the host is changed from a normal read request to a sequential read request, a request received from the host is changed from a sequential read request to a normal read request, or a clock received from an external device is changed.

[0146] If the workload is not changed (No), the memory controller may proceed to operation S901 again to detect the read performance, and may then increase the size of the buffer memory so that the read performance is maximized.

[0147] However, if the workload is changed (yes), the memory controller may stop outputting the RLA command. When the workload is changed, the memory controller may again determine whether the read performance is maximum in the changed workload, and determine whether to increase the size of the buffer memory based on the result of the determination.

[0148] Fig.10 The present invention is a diagram showing an embodiment of the present invention. Figure 1 Schematic diagram of an embodiment of a memory controller.

[0149] The memory controller 1000 is connected to the host and the memory device. In response to a request from the host, the memory controller 1000 can access the memory device. For example, the memory controller 1000 can control the write operation, read operation, erase operation and background operation of the memory device. The memory controller 1000 can provide an interface between the memory device and the host. The memory controller 1000 can drive firmware for controlling the memory device.

[0150] Reference Fig.10 , the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) circuit 1030 , a host interface 1040 , a buffer control circuit 1050 , a memory interface 1060 , and a bus 1070 .

[0151] The bus 1070 may provide a channel between the components of the memory controller 1000 .

[0152] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host through a host interface 1040 and communicate with a memory device through a memory interface 1060. In addition, the processor 1010 may communicate with a memory buffer 1020 through a buffer control circuit 1050. The processor 1010 may control the operation of a memory device by using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

[0153] The processor 1010 can perform the function of a flash translation layer (FTL). The processor 1010 can convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL can receive the LBA and convert the LBA into the PBA using a mapping table. The address mapping method using the FTL can be modified in various ways according to the mapping unit. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

[0154] The processor 1010 may randomize the data received from the host. For example, the processor 1010 may use a randomization seed to randomize the data received from the host. The randomized data may be provided to the memory device as data to be stored and may be programmed to the memory cell array.

[0155] The processor 1010 may drive software or firmware to perform a randomization operation or a de-randomization operation.

[0156] The memory buffer 1020 may be used as an operation memory, a cache memory, or a buffer controller of the processor 1010. The memory buffer 1020 may store codes and commands to be executed by the processor 1010. The memory buffer 1020 may store data to be processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0157] The ECC circuit 1030 may perform error correction. The ECC circuit 1030 may perform an ECC encoding operation based on data to be written to the memory device through the memory interface 1060. The ECC-encoded data may be transmitted to the memory device through the memory interface 1060. The ECC circuit 1030 may perform an ECC decoding operation on data received from the memory device through the memory interface 1060. For example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0158] The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.

[0159] The buffer control circuit 1050 may control the memory buffer 1020 under the control of the processor 1010 .

[0160] The memory interface 1060 may communicate with the memory device under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0161] For example, the memory controller 1000 may include neither the memory buffer 1020 nor the buffer control circuit 1050 .

[0162] For example, the processor 1010 may control the operation of the memory controller 1000 by using the code. The processor 1010 may load the code from a nonvolatile memory device (eg, a read-only memory) provided in the memory controller 1000. Alternatively, the processor 1010 may load the code from the memory device through the memory interface 1060.

[0163] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transmit data within the memory controller 1000. The control bus may transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus may be separated from each other and may not interfere with or affect each other. The data bus may be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0164] In an embodiment, the processor 1010 may detect a change in workload. A change in workload may refer to a change in the workload from the host 300 (see Figure 1) is changed from a normal read request to a sequential read request or from a sequential read request to a normal read request, or a clock input from an external device is changed. A normal read request may be an instruction to read a sequential read request in the memory device 100 (see Figure 1 ), and a sequential read request may be a request to read data stored in a specific area of ​​the memory device 100 (see Figure 1 ) in a request for data.

[0165] In an embodiment, if a slave host 300 (see Figure 1 ) received by the processor 1010 changes the workload from a normal read request to a sequential read request, the processor 1010 may output an RLA command to the memory device 100 (see Figure 1 ). The RLA command may be output to the memory device 100 (see Figure 1 ) to be sent from the host 300 (see Figure 1 ) frequently requested data is pre-cached in the memory buffer 1020. In order to improve the host 300 (see Figure 1 ) of the sequential read request, the read performance of the slave host 300 (see Figure 1 ) Frequently requested data is stored in the memory buffer 1020. In response to the RLA command, Figure 1 The memory device 100 may output corresponding data, and the memory buffer 1020 may store the corresponding data.

[0166] Subsequently, the processor 1010 may determine the read performance at each preset cycle. The processor 1010 may output the read performance to the host 300 (see Figure 1 ) is the same as the size of the data from the host 300 (see Figure 1 ) The read performance is determined by the ratio of the size of the requested data. Output to the host 300 (see Figure 1 ) the larger the size of the data, the higher the read performance can be. In addition, when outputting to the host 300 (see Figure 1 ) is the same as the size of the data from the host 300 (see Figure 1 ) When the ratio of the size of the requested data is "1", the read performance may be maximized.

[0167] In an embodiment, if the read performance is maximum, the processor 1010 may detect the change in workload again. If the read performance is not maximum, the processor 1010 may increase the size of the memory buffer 1020. Here, the memory buffer 1020 may be composed of the storage device 50 (see Figure 1) is composed of a default area allocated as a default when initialized and a variable area. The processor 1010 can increase the size of the memory buffer 1020 by allocating a part of the variable area as an area to be stored with data in a preset size.

[0168] In an embodiment, if the size of the memory buffer 1020 is increased, the processor 1010 may detect the change of the workload again. If the workload is not changed, the processor 1010 may detect the read performance again at a preset cycle and increase the size of the memory buffer 1020 until the read performance is maximized. However, if the workload is changed, the processor 1010 may detect the read performance again at a preset cycle after stopping outputting the RLA command and increase the size of the memory buffer 1020 until the read performance is maximized.

[0169] Therefore, by increasing the size of the memory buffer 1020, the slave host 300 (see Figure 1 ) The size of the data to be stored in the memory buffer 1020 that is frequently requested. Therefore, since there is no need to Figure 1 ) read from the host 300 (see Figure 1 ) frequently requested data, so the time required for read operations can be reduced and read performance can be improved.

[0170] Fig.11 is a block diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0171] Reference Fig.11 , the memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0172] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control the read operation, write operation, erase operation, and background operation of the memory device 2200. The memory controller 2100 can provide an interface between the memory device 2200 and the host. The memory controller 2100 can drive firmware for controlling the memory device 2200. The memory device 2200 can be connected to the memory device 2200 in a manner similar to that of the reference device 2200. Figure 1 The memory device 100 described (see Figure 1 ) in the same way.

[0173] In an embodiment, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC circuit.

[0174] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the memory controller 2100 may communicate with an external device through at least one of various communication standards or interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High-Speed ​​Non-Volatile Memory (NVMe) protocol. In an embodiment, the connector 2300 may be defined by at least one of the various communication standards or interfaces described above.

[0175] In an embodiment, the memory device 2200 may be implemented as any of various non-volatile memory devices such as: electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0176] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash (CF) card, a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or Micro MMC), an SD card (SD, Mini SD, Micro SD or SDHC), or a Universal Flash Storage (UFS).

[0177] In an embodiment, the memory controller 2100 may detect a change in workload. The change in workload may refer to a change in the workload from the host 300 (see Figure 1 ) A request received by the memory device 2200 is changed from a normal read request to a sequential read request or from a sequential read request to a normal read request, or a clock input from an external device is changed. The normal read request may be a request instructing to read data stored in a specific area of ​​the memory device 2200, and the sequential read request may be a request instructing to read data continuously stored in the memory device 2200.

[0178] In an embodiment, if a slave host 300 (see Figure 1) received by the host 300 (see FIG. 2 ) changes from a normal read request to a sequential read request, the memory controller 2100 may output an RLA command to the memory device 2200. The RLA command may be output to the memory device 2200 to receive the request from the host 300 (see FIG. 2 ). Figure 1 ) frequently requested data is pre-cached in the buffer memory of the memory controller 2100. In order to improve the Figure 1 ) of the sequential read request, the read performance of the slave host 300 (see Figure 1 ) Frequently requested data is stored in the buffer memory in the memory controller 2100. In response to the RLA command, the memory device 2200 may output the corresponding data, and the buffer memory in the memory controller 2100 may store the corresponding data.

[0179] Subsequently, the memory controller 2100 may determine the read performance at each preset cycle. The memory controller 2100 may output the read performance to the host 300 during the reference time (see Figure 1 ) is the same as the size of the data from the host 300 (see Figure 1 ) The read performance is determined by the ratio of the size of the requested data. Output to the host 300 (see Figure 1 ) the larger the size of the data, the higher the read performance can be. In addition, when outputting to the host 300 (see Figure 1 ) is the same as the size of the data from the host 300 (see Figure 1 ) When the ratio of the size of the requested data is "1", the read performance may be maximized.

[0180] In an embodiment, if the read performance is maximum, the memory controller 2100 may detect the change in workload again. If the read performance is not maximum, the memory controller 2100 may increase the size of the buffer memory in the memory controller 2100. Here, the buffer memory in the memory controller 2100 may be composed of the memory device 50 (see Figure 1 ) is composed of a default area allocated as a default when initialized and a variable area that is variable. The memory controller 2100 can increase the size of the buffer memory in the memory controller 2100 by allocating a part of the variable area with a preset size as an area to be stored with data.

[0181] In an embodiment, if the size of the buffer memory in the memory controller 2100 is increased, the memory controller 2100 may detect the change of the workload again. If the workload is not changed, the memory controller 2100 may detect the read performance again at a preset cycle and increase the size of the buffer memory in the memory controller 2100 until the read performance is maximized. However, if the workload is changed, the memory controller 2100 may detect the read performance again at a preset cycle after stopping outputting the RLA command and increase the size of the buffer memory in the memory controller 2100 until the read performance is maximized.

[0182] Therefore, by increasing the size of the buffer memory in the memory controller 2100, the number of slaves 300 (see Figure 1 ) The size of the data to be stored in the buffer memory in the memory controller 2100 that is frequently requested. Therefore, since it is not necessary to read the data from the host 300 (see Figure 1 ) frequently requested data, so the time required for read operations can be reduced and read performance can be improved.

[0183] Fig.12 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0184] Reference Fig.12 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange a signal SIG with the host 3100 through a signal connector 3001, and may receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0185] In an embodiment, the SSD controller 3210 may perform the above reference Figure 1 The memory controller 200 described (see Figure 1 ) function.

[0186] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. In an embodiment, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe) interface.

[0187] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 can be supplied with power PWR from the host 3100 and can be charged by the power PWR. When the power supply from the host 3100 is not stable, the auxiliary power supply 3230 can supply power to the SSD 3200. In an embodiment, the auxiliary power supply 3230 can be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located in the mainboard and can supply auxiliary power to the SSD 3200.

[0188] The buffer memory 3240 is used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0189] In an embodiment, the SSD controller 3210 may detect a change in workload. The change in workload may refer to a request received from the host 3100 being changed from a normal read request to a sequential read request or from a sequential read request to a normal read request, or a clock input from an external device being changed. A normal read request may be a request for instructing to read data stored in a specific area of ​​any one of the plurality of flash memories 3221 to 322n. A sequential read request may be a request for instructing to read data continuously stored in any one of the plurality of flash memories 3221 to 322n.

[0190] In an embodiment, when it is detected that the request received from the host 3100 changes from a normal read request to a workload of a sequential read request, the SSD controller 3210 may output an RLA command to any one of the plurality of flash memories 3221 to 322n. The RLA command may be a command output to the plurality of flash memories 3221 to 322n to pre-cache data frequently requested from the host 3100 in the buffer memory 3240. In order to improve the read performance according to the sequential read request of the host 3100, the data frequently requested from the host 3100 may be stored in the buffer memory 3240. In response to the RLA command, the plurality of flash memories 3221 to 322n may output corresponding data, and the buffer memory 3240 may store the corresponding data.

[0191] Subsequently, the SSD controller 3210 may determine the read performance at each preset cycle. The read performance may be determined by the ratio of the size of the data output to the host 3100 during the reference time to the size of the data requested from the host 3100. The larger the size of the data output to the host 3100, the higher the read performance may be. In addition, when the ratio of the size of the data output to the host 3100 to the size of the data requested from the host 3100 is "1", the read performance may be maximum.

[0192] In an embodiment, if the read performance is maximum, the SSD controller 3210 may detect the change in workload again. If the read performance is not maximum, the SSD controller 3210 may increase the size of the buffer memory 3240. Here, the buffer memory 3240 may be formed by the storage device 50 (see Figure 1 ) is composed of a default area allocated as a default when initialized and a variable area. The SSD controller 3210 can increase the size of the buffer memory 3240 by allocating a part of the variable area as an area to be stored with data in a preset size.

[0193] In an embodiment, if the size of the buffer memory 3240 is increased, the SSD controller 3210 may detect the change of the workload again. If the workload is not changed, the SSD controller 3210 may detect the read performance again in a preset cycle and increase the size of the buffer memory 3240 until the read performance becomes maximum. However, if the workload is changed, the SSD controller 3210 may detect the read performance again in a preset cycle after stopping outputting the RLA command and increase the size of the buffer memory 3240 until the read performance becomes maximum.

[0194] Therefore, by increasing the size of the buffer memory 3240, the size of data frequently requested from the host 3100 to be stored in the buffer memory 3240 can be increased. Therefore, since the data frequently requested from the host 3100 does not need to be read from any of the plurality of flash memories 3221 to 322n, the time required for a read operation can be reduced and the read performance can be improved.

[0195] Fig.13 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0196] Reference Fig.13 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0197] The application processor 4100 may run components, an operating system (OS), or a user program included in the user system 4000. In an embodiment, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0198] The memory module 4200 may be used as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) and may then be provided as a single semiconductor package.

[0199] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth or WI-FI communication. For example, the network module 4300 may be included in the application processor 4100.

[0200] The storage module 4400 may store data therein. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100. In an embodiment, the storage module 4400 may be implemented as a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive) such as a memory card or an external drive of the user system 4000.

[0201] In an embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, and each of the plurality of non-volatile memory devices may be configured as described above with reference to Figures 2 to 3 The memory module 4400 may be operated in the same manner as the memory device 100 described above. Figure 1 The storage device 50 operates in the same manner as described.

[0202] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. In an embodiment, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may further include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, a monitor, etc.

[0203] In an embodiment, the application processor 4100 may detect a change in workload. The change in workload may refer to a change in the workload from the host 300 (see Figure 1 ) A request received by the memory module 4400 is changed from a normal read request to a sequential read request or from a sequential read request to a normal read request, or a clock input from an external device is changed. The normal read request may be a request instructing to read data stored in a specific area of ​​the memory module 4400, and the sequential read request may be a request instructing to read data continuously stored in the memory module 4400.

[0204] In an embodiment, if a slave host 300 (see Figure 1) received by the host 300 (see FIG. 4 ) changes the workload from a normal read request to a sequential read request, the application processor 4100 may output an RLA command to the storage module 4400. The RLA command may be output to the storage module 4400 to Figure 1 ) frequently requested data is pre-cached in the memory module 4200. In order to improve the host 300 (see Figure 1 ) of the sequential read request, the read performance of the slave host 300 (see Figure 1 ) Frequently requested data is stored in the memory module 4200. In response to the RLA command, the storage module 4400 may output the corresponding data, and the memory module 4200 may store the corresponding data.

[0205] Thereafter, the application processor 4100 may determine the read performance at each preset cycle. The read performance may be determined by outputting the read performance to the host 300 during the reference time (see Figure 1 ) is the same as the size of the data from the host 300 (see Figure 1 ) The read performance is determined by the ratio of the size of the requested data. Output to the host 300 (see Figure 1 ) the larger the size of the data, the higher the read performance can be. In addition, when outputting to the host 300 (see Figure 1 ) is the same as the size of the data from the host 300 (see Figure 1 )When the ratio of the size of the requested data is "1", the read performance may be maximum.

[0206] In an embodiment, if the read performance is maximum, the application processor 4100 may detect the change of the workload again. If the read performance is not maximum, the application processor 4100 may increase the size of the memory module 4200. Here, the memory module 4200 may be composed of the storage device 50 (see Figure 1 ) is composed of a default area allocated as a default when initialized and a variable area that is variable. The application processor 4100 can increase the size of the memory module 4200 by allocating a part of the variable area as an area to be stored with data in a preset size.

[0207] In an embodiment, if the size of the memory module 4200 is increased, the application processor 4100 may detect the change of the workload again. If the workload is not changed, the application processor 4100 may detect the read performance again at a preset cycle and increase the size of the memory module 4200 until the read performance becomes maximum. However, if the workload is changed, the application processor 4100 may detect the read performance again at a preset cycle after stopping outputting the RLA command and increase the size of the memory module 4200 until the read performance becomes maximum.

[0208] Therefore, by increasing the size of the memory module 4200, the number of slave hosts 300 (see Figure 1 ) The size of the data to be stored in the memory module 4200 that is frequently requested. Therefore, since it is not necessary to read the data from the host 300 (see Figure 1 )For frequently requested data, the time required for read operations can be reduced and the read performance can be improved.

[0209] According to the present disclosure, an RLA command is output based on a result of determining read performance when the workload is changed, and then the size of the buffer memory is increased based on the measured read performance, so that the read performance of the storage device can be improved.

[0210] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, the embodiments may be combined to form further embodiments.

Claims

1. A memory controller, the memory controller controlling a memory device, the memory controller comprising: a workload detector that determines a change in workload based on a request for change received from a host or a clock change received from an external device; a device performance controller that, if the workload is determined to have changed, determines a read performance based on a ratio of a size of data output to the host to a size of data requested from the host per preset cycle, and outputs a read-ahead command, i.e., an RLA command, to the memory device based on the determined read performance; a buffer memory including a variable area allocated to store data read from the memory device in response to the RLA command; as well as A memory size controller increases the size of the variable area until the read performance is at a maximum.

2. The memory controller according to claim 1, wherein when a request to change from a normal read request to a sequential read request is received from the host, the workload detector determines that the workload is changed, and The normal read request is a request instructing to output data stored in a specific area of ​​the memory device, and the sequential read request is a request instructing to output data continuously stored in the memory device.

3. The memory controller according to claim 1, wherein when the ratio is "1", the device performance controller determines that the read performance is at a maximum. 4 . The memory controller of claim 3 , wherein the device performance controller outputs the RLA command when the read performance is not at a maximum. 5 . The memory controller of claim 4 , wherein if data corresponding to the RLA command is stored in the buffer memory, the device performance controller determines the read performance again at the preset cycle.

6. The memory controller according to claim 5, wherein the buffer memory further includes a default area allocated during initialization, and When it is determined again that the read performance is not at the maximum, the memory size controller allocates a portion of the variable area with a preset size, the portion of the variable area being to store data output from the memory device.

7. The memory controller according to claim 6, wherein the device performance controller determines the read performance again at the preset period until the workload is changed, and The memory size controller increases a portion of the variable area by a preset size until the read performance is at a maximum.

8. The memory controller of claim 6, wherein if the workload detector detects that the workload has been changed after allocating a portion of the variable area with a preset size, the device performance controller determines the read performance again in the preset period after stopping outputting the RLA command, and increases a portion of the variable area with a preset size until the read performance is at a maximum.

9. The memory controller according to claim 5, wherein the buffer memory further includes a default area allocated during initialization, and If the read performance is at a maximum, data is stored only in the default area.

10. A method of operating a memory controller, the memory controller controlling a memory device, the method comprising: determining a change in the workload based on a request for a change received from the host or a clock change received from an external device; If the workload is determined to have changed, determining read performance based on a ratio of a size of data output to the host per a preset cycle to a size of data requested from the host; increasing the size of a variable area included in the buffer memory until the read performance is at a maximum; Based on the determined read performance, outputting a read-ahead command, i.e., an RLA command, to the memory device; and storing data read from the memory device in response to the RLA command in the variable area, The RLA command instructs output of data frequently requested from the host.

11. The method according to claim 10, wherein the workload is determined to have changed when a request to change from a normal read request to a sequential read request is received from the host, and The normal read request is a request instructing to output data stored in a specific area of ​​the memory device, and the sequential read request is a request instructing to output data continuously stored in the memory device.

12. The method according to claim 10, wherein when the ratio is "1", the read performance is determined to be at a maximum.

13. The method of claim 12, wherein the RLA command is output to the memory device when the read performance is not at a maximum.

14. The method according to claim 13, further comprising: After the data read from the memory device is stored in the variable area, the read performance is determined again at the preset cycle.

15. A memory system comprising: A memory device for storing data; a cache memory that caches data read from the device and to be provided to the outside; as well as Controller: When the workload of the system is heavy, a read-ahead operation, i.e., an RLA operation, is performed on the data stored in the device according to the current read performance of the system, and When the workload of the system is light, the size of the cache memory is adjusted according to the current read performance of the system. wherein the controller further determines a current read performance of the system during the RLA operation and increases the size of the cache memory until the current read performance is at a predetermined value, and The current read performance is a ratio of a first amount to a second amount during a current time period, the first amount being an amount of data output from the system in response to one or more requests from the outside, and the second amount being an amount of data requested by the requests.

16. The memory system according to claim 15, The system is under heavy workload when receiving sequential access requests from the outside, and The system has a relatively light workload when receiving a normal access request from the outside.

17. The memory system according to claim 15, When the operating speed of the system becomes greater than a threshold, the workload of the system is heavy, and When the operation speed becomes the threshold or less, the workload of the system is relatively light. 18 . The memory system of claim 15 , wherein the controller performs the RLA operation when the current read performance is the predetermined value or less. 19 . The memory system of claim 15 , wherein when the current read performance is a predetermined value or more, the controller adjusts the size by maintaining the size.

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