FPGA adjacent output multiplexers are directly connected to minimize routing hops

Abstract

Methods and devices are described for providing direct connections between adjacent output multiplexers in an FPGA to reduce and potentially minimize routing hops. Embodiments described herein include adding direct connections from an output multiplexer of one tile to an adjacent tile. An FPGA device includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of an output multiplexer of one or more adjacent logic block tiles. The one or more direct connections are configured to drive one or more lines originating from the one or more adjacent logic block tiles.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 152,122, filed on February 22, 2021, entitled “FPGA NEIGHBOR OUTPUT MUX DIRECT CONNECTIONS TO MINIMIZEROUTING HOPS,” which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments as described herein relate to the field of programmable gate architectures, and in particular, to programmable gate architectures having adjacent output multiplexers directly connected to minimize routing hops. Background Art

[0004] Field Programmable Gate Arrays (FPGAs) are built using repeating tiles, each of which implements some logic and connects to some lines driven at that tile. Each logic block can be connected to other logic blocks using a starting line starting at that logic block and any of the lines connected to the starting line.

[0005] FPGA architects choose wire segment lengths to optimize speed, area, and routing flexibility. Wires typically drive other wires only at their endpoints, while a wire drives some of the logic blocks along its length (not just at its endpoints). When a wire segment length is chosen so that it spans only one tile, then that segment can be used to initiate a combination of wires that can access any logic block on the chip. However, traveling longer distances requires traversing many wires and many multiplexers (muxes), which is slower.

[0006] Longer segment lengths can be used to reduce multiplexing area and increase speed, but this comes at the expense of routing flexibility. A routing network consisting entirely of segments spanning two tiles would make every other logic block inaccessible. For this reason, some combination of different segment lengths is used, and the connections between these segment lengths allow every tile to be accessible to every other tile.

[0007] With existing techniques, even when using a mix of line segments, the number of hops required to get from one tile to any other tile is variable and does not increase monotonically with the distance between tiles. The mix of line segments means that some tiles can be accessed very directly (e.g., up to 10 tiles when using a line of length 10) or very indirectly (e.g., more than 1 and up to 9 tiles when using a mix of line segments of length 10 and length 1). With existing techniques, it is difficult for software to map the design onto the FPGA while meeting the setup constraints. Summary of the Invention

[0008] Methods and devices are described for providing direct connections between adjacent output multiplexers of an FPGA to minimize routing hops. Embodiments described herein include adding direct connections from one tile to an output multiplexer of an adjacent tile. In at least some embodiments, an FPGA device includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of an output multiplexer of one or more adjacent logic block tiles. The one or more direct connections are configured to drive one or more lines originating from the one or more adjacent logic block tiles.

[0009] In at least some embodiments, a device includes a memory and a processor coupled to the memory. The processor is configured to determine one or more logic block tiles from a plurality of FPGA logic block tiles, determine one or more adjacent logic block tiles from the plurality of FPGA logic block tiles, and directly connect the one or more logic block tiles to one or more inputs of output multiplexers of the one or more adjacent logic block tiles to drive one or more lines originating from the one or more adjacent logic block tiles.

[0010] In at least some embodiments, a non-transitory machine-readable medium is provided that stores instructions for causing a data processing system to perform operations including determining one or more logic block tiles from a plurality of FPGA logic block tiles, determining one or more adjacent logic block tiles from the plurality of FPGA logic block tiles, and directly connecting the one or more logic block tiles to one or more inputs of output multiplexers of the one or more adjacent logic block tiles to drive one or more lines originating from the one or more adjacent logic block tiles.

[0011] Other devices, methods, and machine-readable media that provide direct connection of adjacent output multiplexers of an FPGA are also described. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The embodiments of the present application may be best understood by referring to the following description and the accompanying drawings which illustrate the embodiments of the present application. In the drawings:

[0013] Figure 1 is a diagram 100 of a field programmable gate array (FPGA) system architecture according to one embodiment of the present disclosure.

[0014] Figure 2 is a diagram 200 of a portion of a field programmable gate array (FPGA) system architecture according to one embodiment of the present disclosure.

[0015] Figure 3 is a diagram of a switch block (SB) 300 according to one embodiment of the present disclosure.

[0016] Figure 4 is a diagram of a device 400 including a FPGA directly adjacent output multiplexer connection according to one embodiment of the present disclosure.

[0017] Figure 5 FIG. 5 is a map 500 representing an FGPA architecture without direct output multiplexer connections according to one embodiment of the present disclosure.

[0018] Figure 6 FIG. 6 is a map 600 representing an FGPA architecture with direct output multiplexer connections according to one embodiment of the present disclosure.

[0019] Figure 7 FIG. 7 is a flow chart of a method 700 for providing direct connection of adjacent output multiplexers of an FPGA to minimize routing hops according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Methods and apparatus are described for providing direct connections between adjacent FPGA output multiplexers to minimize routing hops. The embodiments described herein include adding direct connections from the output multiplexers of one tile to the output multiplexers of an adjacent tile. Adding direct connections from an FPGA logic block to the output multiplexers of an adjacent FPGA logic block improves the flexibility, area efficiency, and speed of the FPGA routing network compared to conventional techniques.

[0021] In at least some embodiments, a source tile can access a start line that originates from a neighboring tile. This creates a smoother function of the number of routing hops versus the distance between two routing tiles than is currently possible. Additionally, software mapping a design onto an FPGA has more options when attempting to place two logic blocks nearby with as few hops as possible between them. Smoothing the function of the number of hops versus distance makes it easier for software to map a design onto an FPGA while satisfying setup constraints. Furthermore, increasing the number of tiles accessible with fewer hops helps software satisfy setup constraints on multiple paths simultaneously.

[0022] In at least some embodiments, an FPGA device includes a plurality of logic block tiles, the plurality of logic block tiles including one or more first logic block tiles and one or more second logic block tiles. One or more lines originate from the one or more first logic block tiles. One or more direct connections extend from the one or more first logic block tiles to one or more inputs of an output multiplexer of one or more second logic block tiles, the one or more second logic block tiles being logic block tiles adjacent to the one or more first logic block tiles. As described in further detail below, the one or more direct connections are configured to drive the one or more lines originating from the one or more second logic block tiles.

[0023] In at least some embodiments, direct output multiplexer connections are established to any number of adjacent tiles. Increasing the number of direct connections can smooth the function of hops versus distance, but at the expense of increasing the size of the multiplexers in the adjacent tiles. In one embodiment, the decision of how many direct connections to add and to which neighbors to add them is tied to the FPGA logic block architecture and the wire segment architecture. The FPGA architect can also decide where to connect the direct connections within the adjacent tiles. In at least some embodiments, for logic blocks with multiple levels of output multiplexing, direct connections can be established to earlier multiplexer stages or later multiplexer stages, a trade-off tied to the FPGA logic block architecture and the wire segment architecture.

[0024] In at least some embodiments, the introduction of direct output multiplexer connections increases the operating frequency of a typical circuit implemented on an FPGA. Additionally, as described in further detail below, a less flexible wire segment architecture may be selected due to the additional flexibility introduced by adding direct output multiplexer connections.

[0025] Various embodiments and aspects of the present disclosure will be described with reference to the details discussed below, and the accompanying drawings will illustrate various embodiments. The following description and drawings are illustrative of the present disclosure and should not be construed as limiting the present disclosure. Many specific details are described to provide a thorough understanding of the various embodiments of the present disclosure. However, in some cases, well-known or conventional details are not described in order to provide a concise discussion of the embodiments of the present disclosure.

[0026] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0027] Figure 1 FIG1 is a diagram 100 of a field programmable gate array (FPGA) system architecture according to one embodiment. For example, the FPGA system includes a plurality of FPGA tiles, such as FPGA tiles 101, 102, 103, 104, 105, and 111. In some embodiments, FPGA tiles 101, 102, 103, and 104 are logic blocks (LBs), and tiles 105 and 111 are switch blocks (SBs). Tiles are connected using wires. Figure 1 As shown, tile 101 is connected to a line of routing route 106 via line 107. The line of routing route 106 passes through tile 105. Tile 102 is connected to a line of routing route 112 via line 108. The line of this routing route passes through tile 111.

[0028] In at least some embodiments, the LB tile 101 includes one or more direct connections 109 to one or more inputs of the output multiplexers of one or more other LB tiles. In at least some embodiments, the other LB tiles are adjacent LB tiles to the tile 101, such as LB tiles 102, 103, and 104. Generally, a tile A is referred to as an adjacent tile to tile B if it is physically adjacent to tile B. A horizontally adjacent tile A is a tile where tile A is located due east or due west of tile B and there are no other tiles between tiles A and B. A diagonal tile A is a tile where tile A is located due northeast, due northwest, due southeast, or due southwest of tile B and there are no other tiles between A and B. A vertically adjacent tile A is a tile where tile A is located due north or due south of tile B and there are no other tiles between tiles A and B. Schematic 113 represents the north, south, east, and west directions on the FPGA architecture diagram. As Figure 1 As shown, tile 102 is due east of tile 101 , tile 103 is due southeast of tile 101 , and tile 104 is due south of tile 101 .

[0029] In at least some embodiments, one or more direct connections 109 include one or more lines (not shown). In at least some embodiments, one or more of direct connections 109 are configured to drive one or more lines (not shown) originating from one or more other LB tiles. In at least some embodiments, LB tile 101 includes a LB having one or more output multiplexers (not shown), and an adjacent logic block tile includes a logic block having one or more output multiplexers, and the outputs of the one or more output multiplexers of LB tile 101 are directly connected to the inputs of the one or more output multiplexers of the adjacent LB tile. In at least some embodiments, one or more direct connections 109 include one or more lines. In at least some embodiments, one or more direct connections 109 include direct connections from the output of a lookup table (LUT) of LB tile 101 to one or more inputs of the output multiplexers of the one or more adjacent logic block tiles. In at least some embodiments, one or more direct connections 109 are horizontal connections to LB tile 102 in the same row as tile 101. In at least some embodiments, one or more direct connections 109 are vertical connections to tile 104 in the same column as tile 101. In at least some embodiments, for example, one or more direct connections such as direct connection 109 are diagonal connections to tile 103 in an adjacent column and adjacent row as tile 101. In at least some embodiments, the other LB tiles (102, 103, or 104) that provide one or more direct connections 109 from LB tile 101 are determined based on one or both of time and frequency of the circuit design. In at least some embodiments, the number (amount) of one or more direct connections 109 is determined based on circuit design constraints. In at least some embodiments, the number of one or more direct connections 109 is increased to increase accessibility, reduce timing delays, and increase the speed of signal and circuit execution. In at least some embodiments, the other LB tiles (102, 103, or 104) that provide one or more direct connections 109 from LB tile 101 are determined based on a balance between the negative impact on chip area and multiplexer speed and the increase in routing flexibility, which can result in improvements in wire usage and circuit frequency of a design implemented on an FPGA.

[0030] Typically, the routing architecture includes programmable switches and wires. Routing provides connections between input / output (I / O) blocks and logic blocks, and between one logic block and another. The type of routing architecture determines the area occupied by routing and the density of logic blocks. The routing technology used in the FPGA determines the amount of area used by wire segments and programmable switches compared to the area consumed by logic blocks. A wire segment can refer to two endpoints of an interconnect with no programmable switch between them. A sequence of one or more wire segments in an FPGA is called a track. Typically, an FPGA has logic blocks, interconnects, and I / O blocks. I / O blocks are located outside the logic blocks and interconnects. Wire segments connect I / O blocks to wire segments through connection blocks. Connection blocks connect to logic blocks, and one logic block connects to another logic block, and so on, depending on the design requirements.

[0031] Typically, FPGA architectures include wires that have a start point (the location where these wires are driven by a multiplexer) and an end point (the location of the furthest multiplexer input driven by the wire). For example, a wire driven by a multiplexer logically located at grid position (4, 5) and driving a different multiplexer at position (4, 10) has a length of 5. Typically, there are multiple different wire types on an FPGA, each with a different length. For example, an FPGA may have three different wire types, one of which has a length of 1, one of which has a length of 5, and one of which has a length of 14. In at least some other embodiments, the FPGA architecture has one or more of wires of length 1, wires of length 2, wires of length 3, wires of length 4, wires of length 5, wires of other lengths, or any combination thereof.

[0032] Figure 2 FIG2 is a diagram of a portion of a field programmable gate array (FPGA) system architecture according to one embodiment. FIG200 shows a LB tile 201, a SB tile 202, a routing path 206, and a routing path 207. The LB tile 201 includes an input multiplexer, such as input multiplexer 203. In at least some embodiments, as described above with respect to FIG201 , FIG202 is a diagram of a portion of a field programmable gate array (FPGA) system architecture according to one embodiment. FIG203 is a diagram of a portion of a field programmable gate array (FPGA) system architecture according to one embodiment. FIG204 is a diagram of a field programmable gate array (FPGA) system architecture according to one embodiment. FIG205 is a diagram of a field programmable gate array (LB) tile 201, a routing path 206, and a routing path 207. Figure 1 As depicted, LB tile 201, SB tile 202, routing path 206, and routing path 207 represent routing paths and tiles of an FPGA system. Figure 2 As shown, the input multiplexer of LB tile 201 is connected to a line of routing route 206 using line 204. The input multiplexer of LB tile 201 is connected to a line of routing route 207 using line 205. Routing route 207 is connected to SB tile 202. Each of lines 204 and 205 drives a separate input terminal of multiplexer 203, as shown in FIG. Figure 2 shown.

[0033] like Figure 2As shown, LB tile 201 includes one or more direct connections 208 to one or more inputs of an output multiplexer of an adjacent LB tile (not shown). In at least some embodiments, the one or more direct connections 208 include one or more output multiplexers (not shown). In at least some embodiments, the outputs of the one or more output multiplexers of LB tile 201 are directly connected to the inputs of one or more output multiplexers of an adjacent LB tile using lines. In at least some embodiments, the one or more direct connections 208 include a line 211 that is directly connected to the input of the multiplexer of the adjacent LB tile (not shown) and a line 209 that drives other LB tiles. In at least some embodiments, the signal on line 211 is the same as the signal on line 209. In at least some embodiments, as described in further detail below, the one or more direct connections 208 include a direct connection from the output of a lookup table (LUT) of tile 201 to one or more inputs of the output multiplexers of one or more adjacent logic block tiles.

[0034] Figure 3 316 is a diagram of a switch block (SB) 300 according to one embodiment. Diagram 316 represents the north, south, east, and west directions on the FPGA architecture diagram. A line ending at SB 300 can drive one or more multiplexers in SB 300, which drive one or more lines starting at that location. In addition, a logic block located at the same location as the switch block can drive one or more multiplexers in the SB. Figure 3 As shown, SB includes a plurality of multiplexers 302, 303, 304, and 305. Each of the multiplexers 302, 303, 304, and 305 has a plurality of input terminals and an output terminal. In some embodiments, each of the multiplexers 302, 303, 304, and 305 is driven by one or more lines that terminate at and are connected to the input terminals of the multiplexer. Figure 3 As shown, logic block line 306, east line 307, north line 308, and west line 309 end at SB 300. Each of logic block line 306, east line 307, north line 308, and west line 309 ends at a corresponding input of multiplexer 302. In some embodiments, each line starting at SB 300 is driven by a multiplexer. Figure 3 As shown, multiplexer 302 drives north line 311 starting at the output of multiplexer 302. Multiplexer 303 drives west line 314 starting at the output of multiplexer 303. Multiplexer 304 drives east line 312 starting at the output of multiplexer 304. Multiplexer 305 drives south line 313 starting at the output of multiplexer 305. Figure 3As shown, one or more lines 315 pass through the SB. One or more lines 315 bypass the multiplexer in the SB 300.

[0035] Figure 4 4 is a diagram of a device 400 including FPGA direct adjacent output multiplexer connections, according to one embodiment. Device 400 includes multiple FPGA logic block tiles, such as tile 401 and tile 406. In at least some embodiments, tile 406 is an adjacent tile to tile 401. Tile 401 includes logic block 402, and tile 406 includes logic block 407. In some embodiments, each of logic blocks 402 and 407 includes one or more lookup tables (LUTs) and flip-flops (FFs). For example, tile 401 includes an input multiplexer such as input multiplexer 403 and an output multiplexer such as output multiplexer 404. The output multiplexer of tile 401 drives line 405 to other FPGA logic block tiles. For example, tile 406 includes an input multiplexer such as input multiplexer 411 and an output multiplexer such as output multiplexer 408. The output multiplexer of tile 406 drives line 413 .

[0036] like Figure 4 As shown, line 405 originates from logical block tile 401, and line 413 originates from logical block tile 406. In at least some embodiments, input multiplexers 403 and 411 represent the logic blocks described above. Figure 2 In at least some embodiments, output multiplexers 404 and 408 represent the input multiplexers described above with respect to Figure 2 One or more direct connections, such as connection 409 and connection 412, are generated from FPGA logic block tile 401 to one or more inputs of output multiplexer 408. In at least some embodiments, connection 409 is added to the output of multiplexer 404 that drives line 405. Figure 4As shown, line 405 and line 409 are connected to the output of multiplexer 404. Connection 409 is a direct connection from the output of multiplexer 404 to the input of output multiplexer 408 to drive line 413. In at least some embodiments, connection 412 is a direct connection from the output of the LUT of logic block 402 to the input of output multiplexer 408 to drive line 413. In at least some embodiments, direct connection 409 comprises a line. In at least some embodiments, direct connection 412 comprises a line. In at least some embodiments, direct connection 409 carries the same signal as the signal on line 405 that drives another logic block tile, allowing output multiplexer resources to be shared between different logic blocks. In at least some embodiments, a logic cell has the ability to directly drive a line originating at an adjacent cell. For example, the line driver is a multiplexer having multiple inputs, and at least some of the inputs of the multiplexer are directly connected to one or more adjacent logic cells. For example, consider an FPGA logic cell with output multiplexers that drive lines originating at that location. Direct connections can be added from these output multiplexers to the inputs of the multiplexers in adjacent cells to drive lines originating at the adjacent cells. This allows the circuit to directly drive additional lines originating at different locations using only one additional multiplexer, significantly reducing the circuit's time delay.

[0037] Typically, mapping (e.g., placement, routing) a circuit design onto an FPGA requires satisfying predetermined design constraints. In at least some embodiments, the logic block tiles that provide direct connections (e.g., direct connections 409, direct connections 412) are determined based on circuit design constraints (e.g., time, frequency, or both time and frequency). In at least some embodiments, the number of direct connections (e.g., how many direct connections 409, 412 need to be generated) is determined based on the length of the FPGA line segment used to route the circuit. In at least some embodiments, the number of one or more direct connections 409, 412 is increased to increase accessibility, reduce timing delays, and increase the speed of signal and circuit execution. As Figure 4 As shown in , a connection is established from the output of a logic block to the input of the output multiplexer of an adjacent logic block. Figure 4 As shown, each logic block is also connected to a wire whose length is defined by the FPGA wire segment architecture. This has the effect of sharing the output multiplexer resources between different logic blocks.

[0038] Figure 5 5 is a map 500 showing an FGPA architecture without direct output multiplexer connections according to one embodiment of the present disclosure. The map 500 shows the number of wire jumps required to reach a logic block without a direct connection to an adjacent output multiplexer. Figure 5As shown, the FPGA fabric includes 81 tiles. Mapping diagram 500 shows the number of hops (e.g., line segments) required to reach each FPGA tile from the source FPGA tile 511 at the center of the 9-tile x 9-tile grid. The map shows how much delay (hops) are required to get from one location to each other location on the chip. For this example, the FPGA line segment fabric is 2 lines long.

[0039] like Figure 5 As shown, eight FPGA tiles, such as FPGA tile 501, can be reached from FPGA tile 511 via one hop (a line of length 2). Figure 5 As shown, 20 FPGA tiles such as FPGA tile 502 can be reached from FPGA tile 511 through two hops (two lines of length 2). Figure 5 As shown, 24 FPGA tiles such as FPGA tile 503 can be reached from FPGA tile 511 through three hops (three lines of length 2). Figure 5 As shown, 12 FPGA tiles such as FPGA tile 504 can be reached from FPGA tile 511 via four hops (four lines of length 2). Figure 5 As shown, 16 FPGA tiles, such as FPGA tile 505, are not reachable from FPGA tile 511. That is, some locations on map 500 are not reachable via a line of length 2 without a direct output multiplexer connection.

[0040] Figure 6 6 is a map showing an FPGA architecture with direct output multiplexer connections according to one embodiment of the present disclosure. Map 600 shows the number of wire jumps required to reach a logic block when adjacent output multiplexers are directly connected. Map 600 differs from map 500 in that a direct connection 606 is added between the source FPGA tile 611 at the center of the grid and the FPGA tile 607 to the south / east of FPGA tile 611. Direct connection 606 drives the output multiplexer of FPGA tile 607. Figure 6 As shown, for example, 14 FPGA tiles such as FPGA tile 601 can be reached from FPGA tile 611 via one hop. Figure 6 As shown, for example, 28 FPGA tiles such as FPGA tile 602 can be reached from FPGA tile 611 via two hops. Figure 6 As shown, for example, 28 FPGA tiles such as FPGA tile 603 can be reached from FPGA tile 611 via three hops. Figure 6As shown, for example, 12 FPGA tiles such as FPGA tile 604 can be reached from FPGA tile 611 in four hops. Note that the number of wire segments required to reach each of the other tiles on the FPGA has been reduced or remains unchanged. In addition, all logic blocks can now be reached. In mapping 600, there are no tiles that cannot be reached from FPGA tile 611. Because there are fewer discontinuities in the function of routing hops versus distance, mapping 600 is smoother than mapping 500. Compared to conventional techniques, direct output multiplexer connections from source logic block tiles to adjacent logic block tiles smooth out the hop (delay) mapping. Compared to conventional techniques, direct output multiplexer connections from source logic block tiles to adjacent logic simplify the placement and routing of wires, provide greater flexibility, and address timing and frequency constraints in FPGA circuits.

[0041] Figure 7is a flow chart of a method 700 for providing direct connections of adjacent output multiplexers of an FPGA to reduce and potentially minimize routing hops according to an embodiment of the present disclosure. Method 700 begins with operation 701, which involves determining a route for one or more first logic block tiles among a plurality of FPGA logic block tiles, the one or more first logic block tiles comprising one or more first lines originating from and connected to one or more output terminals of the one or more first logic block tiles, as described above. In at least some embodiments, the one or more first logic block tiles are source logic block tiles. Operation 702 involves determining a route for one or more second logic block tiles among a plurality of FPGA logic block tiles, the one or more second logic block tiles being adjacent block tiles to the one or more first logic block tiles, as described above. In at least some embodiments, the one or more second logic block tiles are sink logic block tiles. In operation 703, one or more output terminals of one or more first logic block tiles are directly connected to one or more input terminals of the output multiplexers of one or more second logic block tiles to drive one or more second lines, which originate from and are connected to one or more output terminals of the one or more second logic block tiles, as described above. In at least some embodiments, one or more first logic block tiles include a first logic block having one or more first output multiplexers, and one or more second logic block tiles include a second logic block having one or more second output multiplexers, wherein the output terminals of the one or more first output multiplexers are directly connected to the input terminals of the one or more second output multiplexers, as described above. In at least some embodiments, the output terminal of the lookup table (LUT) of at least one of the one or more first logic block tiles is directly connected to the input terminal of one or more input terminals of the output multiplexers of the one or more second logic block tiles, as described above. In at least some embodiments, the one or more first logic block tiles are directly connected to the one or more input terminals of the output multiplexers of the one or more second logic block tiles using one or more lines, as described above.

[0042] Some portions of the above detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of storage, transmission, combination, comparison, and other manipulations. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0043] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise clear from the following discussion, it should be understood that throughout the description, discussions using terms such as "process" or "compute" or "measure" or "determine" or "display" refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into physical quantities similarly represented within the computer system's memories or registers or other such information storage, transmission, or display devices.

[0044] The present invention also relates to an apparatus for performing the operations described herein. The apparatus may be specially constructed for the desired purpose, or the apparatus may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any other type of medium suitable for storing electronic instructions, each connected to a computer system bus.

[0045] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Based on the teachings herein, various general-purpose systems can be used with the program, or it may prove convenient to construct more specialized equipment to perform the desired method operations. The structures required for these various systems will emerge from the description herein. In addition, the embodiments of the present disclosure are described without reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0046] A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include read-only memory ("ROM"); random access memory ("RAM"); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical, or other propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

[0047] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A field programmable gate array device, i.e., an FPGA device, comprising: a plurality of logic block tiles, including one or more first logic block tiles and one or more second logic block tiles, wherein the one or more first lines are coupled to one or more output terminals of the one or more first logic block tiles; as well as one or more direct connections extending from one or more outputs of the one or more first logic block tiles to one or more inputs of an output multiplexer of the one or more second logic block tiles, wherein the one or more second logic block tiles are adjacent logic block tiles to the one or more first logic block tiles, and wherein the one or more direct connections are used to drive one or more second lines coupled to the one or more outputs of the one or more second logic block tiles, wherein the one or more first logic block tiles include a first logic block having one or more first output multiplexers, and the one or more second logic block tiles include a second logic block having one or more second output multiplexers, wherein outputs of the one or more first output multiplexers are directly connected to inputs of the one or more second output multiplexers. 2 . The apparatus of claim 1 , wherein the one or more direct connections comprise one or more third lines.

3. A device according to claim 1, wherein the one or more direct connections include a direct connection from the output of a lookup table (LUT) of at least one of the one or more first logic block tiles to an input of one or more inputs of an output multiplexer of the one or more second logic block tiles. 4 . The apparatus of claim 1 , wherein the one or more direct connections are at least one of a horizontal connection, a vertical connection, or a diagonal connection. The apparatus of claim 1 , wherein the one or more direct connections carry signals, the signals being signals on the one or more first lines. The apparatus of claim 1 , wherein the one or more second logical block tiles are determined based on one or more of time and frequency. The apparatus of claim 1 , wherein a number of the one or more direct connections is determined based on design constraints.

8. A device comprising: Memory; as well as a processor coupled to the memory, wherein the processor is configured to: Determining routes for one or more first logic block tiles among a plurality of FPGA logic block tiles, wherein one or more first lines are coupled to one or more output terminals of the one or more first logic block tiles; determining a route for one or more second logic block tiles of the plurality of FPGA logic block tiles, the one or more second logic block tiles being adjacent block tiles to the one or more first logic block tiles; directly connecting one or more outputs of the one or more first logic block tiles to one or more inputs of an output multiplexer of the one or more second logic block tiles via one or more direct connections to drive one or more second lines, the one or more second lines being coupled to one or more outputs of the one or more second logic block tiles, wherein the one or more first logic block tiles include a first logic block having one or more first output multiplexers, and the one or more second logic block tiles include a second logic block having one or more second output multiplexers, wherein the processor is further configured to directly connect outputs of the one or more first output multiplexers to inputs of the one or more second output multiplexers.

9. The apparatus of claim 8, wherein the processor is further configured to connect the one or more first logic block tiles directly to one or more inputs of an output multiplexer of the one or more second logic block tiles using one or more third lines.

10. The apparatus of claim 8, wherein the processor is further configured to directly connect an output of a lookup table (LUT) of at least one of the one or more first logic block tiles to an input of one or more inputs of an output multiplexer of the one or more second logic block tiles.

11. The apparatus of claim 8, wherein the one or more direct connections are at least one of a horizontal connection, a vertical connection, or a diagonal connection.

12. The apparatus of claim 8, wherein the one or more direct connections carry signals, the signals being signals on the one or more first lines. 13 . The apparatus of claim 8 , wherein the processor is further configured to determine the one or more second logical block tiles based on one or more of time and frequency.

14. The apparatus of claim 8, wherein the processor is further configured to determine a number of the one or more direct connections based on a design constraint.

15. The device of claim 8, wherein the processor is further configured to increase a number of the one or more direct connections to increase signal reachability.

16. A non-transitory machine-readable medium storing instructions that cause a data processing system to perform operations comprising: Determining routes for one or more first logic block tiles among a plurality of FPGA logic block tiles, wherein one or more first lines are coupled to one or more output terminals of the one or more first logic block tiles; determining a route for one or more second logic block tiles of the plurality of FPGA logic block tiles, the one or more second logic block tiles being adjacent block tiles to the one or more first logic block tiles; and directly connecting one or more outputs of the one or more first logic block tiles to one or more inputs of an output multiplexer of the one or more second logic block tiles via one or more direct connections to drive one or more second lines, the one or more second lines being coupled to one or more outputs of the one or more second logic block tiles, wherein the one or more first logic block tiles include a first logic block having one or more first output multiplexers, and the one or more second logic block tiles include a second logic block having one or more second output multiplexers, wherein the data processing system is further configured to directly connect the output ends of the one or more first output multiplexers to the input ends of the one or more second output multiplexers.

17. The non-transitory machine-readable medium of claim 16, wherein the instructions further cause the data processing system to perform operations comprising: The one or more first logic block tiles are directly connected to one or more inputs of an output multiplexer of the one or more second logic block tiles using one or more third lines.

18. The non-transitory machine-readable medium of claim 16, wherein the instructions further cause the data processing system to perform operations comprising: An output of a lookup table (LUT) of at least one of the one or more first logic block tiles is directly connected to an input of one or more inputs of an output multiplexer of the one or more second logic block tiles.

19. The non-transitory machine-readable medium of claim 16, wherein the one or more direct connections are at least one of a horizontal connection, a vertical connection, or a diagonal connection.

20. The non-transitory machine-readable medium of claim 16, wherein the one or more direct connections carry signals, the signals being signals on the one or more first lines.

21. The non-transitory machine-readable medium of claim 16, wherein the instructions further cause the data processing system to perform operations comprising: One or more second logical block tiles are determined based on one or more of time and frequency.

22. The non-transitory machine-readable medium of claim 16, wherein the instructions further cause the data processing system to perform operations comprising: A number of the one or more direct connections is determined based on design constraints.

23. The non-transitory machine-readable medium of claim 16, wherein the instructions further cause the data processing system to perform operations comprising: The number of the one or more direct connections is increased to increase signal reachability.

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