Method and System for Reducing Downtime

Abstract

Disclosed is a system and method for shortening the system management mode when an error occurs in a hardware component in a computer system. The computer system has a hardware component that may have an error. Notification of an error in one of the hardware components is received via the RAS silicon on the processing unit. The error is detected from the hardware component by a system management interrupt handler executed by the boot processor core. Error data is logged into the system error log via a system control interrupt handler executed by the processing unit. During the logging of the error data, the system management mode is avoided. This prevents the system management mode from pausing other processor cores.

Description

Technical Field

[0001] The present disclosure broadly relates to operating reliability in computer systems, and more particularly to a system that transmits error reporting during system management mode to enable a processor core to maintain operation. Background Art

[0002] Servers are widely used in high-demand applications such as web-based systems or data centers. The emergence of cloud computing usage has increased the demand for data centers. A data center houses many servers that store data and execute applications accessed by users of remotely connected computer devices. A typical data center has a physical rack structure with power and communication connections. Each rack can accommodate multiple computing servers and storage servers. Each server typically includes hardware components such as a processor, a memory device, a network interface card, a power supply, and other specialized hardware. Each server typically includes a baseboard management controller (BMC) that manages the operation of the server and conveys computing data to a central management station that manages the servers of the rack.

[0003] A typical server has a processing unit that may have multiple cores for performing computing operations. These cores are executed by an operating system to communicate with hardware components in other servers. One function of the operating system is to identify errors indicating hardware component failures. The chipset of the processing unit may also include a southbridge chip that handles input / output functions and a northbridge chip that handles memory operations. Another function of the southbridge chip and the northbridge chip is to handle different reliability-availability-serviceable (RAS) features through dedicated RAS silicon on the chip. RAS features are designed to enhance reliability and availability and to facilitate the servicing of peripheral components in a computing system. The main objectives of RAS features are: 1) to increase system uptime; 2) to reduce unexpected downtime; and 3) to maintain data integrity. For example, RAS features can detect errors on components such as add-on cards, dual in-line memory modules (DIMMs), and hard disk drives (HDDs). RAS features enable the recording of errors for future analysis and to determine whether an operator must replace a hardware component.

[0004] The system management mode (SMM) is a well-known special-purpose operating mode that provides functions for handling the entire system, such as power management or system hardware control in a computer system. SMM provides a distinct, easily isolated, and operationally transparent processor environment for the operating system or the executor and software applications. The processing unit executes the SMM firmware code in an independent address space that cannot be accessed by other operating modes of the processing unit. SMM can only be entered through a system management interrupt (SMI).

[0005] SMIs are commonly used in server platforms to handle different RAS features. Typically, SMM is executed by the bootstrap processor (BSP) of the computer system. During SMM, the bootstrap processor performs event logging to record the malfunctioning devices. Once the malfunctioning devices are identified, technicians can replace them. For example, regarding peripheral component interconnect express (PCIe) devices, the RAS error report consists of two functions: error logging and error signaling. This RAS feature covers the reporting of errors that occur on the PCIe interface itself, errors that occur on PCIe components representing the initiated transactions, and errors that occur within PCIe components and are associated with the PCIe interface. Another example is that the RAS error report can be a memory-specific error feature associated with errors from memory devices such as dual in-line memory modules (DIMMs).

[0006] However, when the computer system enters SMM, all processing cores and execution threads also enter the SMM mode until the bootstrap processor (BSP) completes its respective SMM RAS services and exits SMM. While the SMM RAS services are being executed, system services and applications are suspended. This means that the computer system cannot provide other computing services, resulting in a downtime while waiting for the bootstrap processor to exit SMM.

[0007] Figure 1Ais a block diagram of a prior art computer system 10 that can initiate RAS services for error detection and logging. The computer system 10 can include a south bridge chip 12 of a processing unit, a basic input / output system (BIOS) 14, a baseboard management controller (BMC) 16, and an operating system (OS) 18. The central processing unit (CPU) / south bridge 12 performs basic input / output functions for the computer system 10 and includes RAS silicon 20. The RAS silicon 20 monitors different hardware devices 22. In this example, the hardware devices 22 include peripheral component interconnect express (PCIe) devices, dual in-line memory modules (DIMMs), hard disk drives (HDDs), universal serial bus (USB) devices, serial peripheral interface (SPI) devices, and system management bus (SMBUS) devices.

[0008] The platform BIOS 14 includes a RAS SMI handler 24 and a RAS system control interrupt (SCI) handler 26. In this example, the RAS SMI handler 24 processes SMM interrupts. The RAS SCI handler 26 processes system control interrupts to provide notifications to the operating system 18. System management interrupts occur when the SMM is triggered. The RAS SMI handler 24 determines the source of the error and causes error data on the device to be written to the system event log (SEL) 28 in the BMC 16. The process of logging error data to the SEL 28 takes a relatively long time and occurs during the SMM. During the SMM, the processing unit (e.g., the CPU) prevents the operating system 18 from running execution threads or other operations from the processor core.

[0009] Figure 1B is Figure 1A a timing diagram of the prior art computer system 10 in which shows the issue that the SMM blocks further operation. As Figure 1AOne of the hardware devices 30 of the hardware device 22 may malfunction, resulting in an error. The RAS silicon 20 performs operation 50, receives an error notification from the hardware device 30 and invokes the SMI handler 24. Then, the RAS silicon 20 performs operation 52, generates a system management interrupt (SMI) and enters the system management mode (SMM). During the SMM, the SMI handler 24 performs operation 54, communicates with the hardware device 30 and detects and collects error-related information. The SMI handler 24 performs operation 56, stores the error information conforming to the ACPI protocol in the ACPI memory to the SCI handler 26. The SMI handler 24 performs operation 58, initiates a system control interrupt to the SCI handler 26. The SMI handler 24 performs operation 60, initiates an error log to write the error information to the system error log 28 described in the BMC 16. The SCI handler 26 performs operation 62, notifies the operating system 18 of the system control interrupt. During the execution of the SMM, the operating system 18 cannot execute any execution threads or any other processing operations.

[0010] For error detection in computing systems such as servers and reporting malfunctions of peripheral components, the RAS feature is very important. However, every time an SMI is executed, the entire server must freeze because the operating system pauses all kernels to enter the SMM, which causes downtime and thus reduces system performance. In addition, if errors are frequently asserted from devices on the server, these errors will cause a series of SMIs, thus increasing the downtime. Due to the downtime, this series of SMIs may have a great impact on system performance.

[0011] Therefore, a system is needed that can shorten the effective time of the SMM to reduce the downtime of the computer system. A system is also needed that can transfer the error log to the system control interrupt handler to shorten the SMM. A system is also needed that can transfer all RAS functions from the system management handler to the system control interrupt handler. Summary of the Invention

[0012] The term "embodiment" and like terms are intended to refer broadly to all subject matter of the present invention and the following claims. Statements containing these terms should not be construed as limiting the subject matter described herein or the meaning or scope of the following claims. The embodiments of the present disclosure covered herein are defined by the following claims rather than the summary of the invention. The summary of the invention is a high-level overview of aspects of the present disclosure and introduces some concepts that are further described in the paragraphs of the following embodiments. The summary of the invention is not intended to identify essential features of the claimed subject matter nor is it intended to be used alone to determine the scope of the claimed subject matter. The claimed subject matter should be understood by reference to the appropriate portions of the entire specification of the present invention, any or all of the drawings, and each claim.

[0013] The disclosed example is a computer system for reducing downtime, comprising: a basic input output system (BIOS) chip; a processing unit comprising a bootstrap core and silicon, the bootstrap core executing a system management interrupt handler and a system control interrupt handler stored in the BIOS chip, the silicon being for receiving error messages; a hardware component coupled to the processing unit, the hardware component sending the error message to the silicon; and a management controller comprising a system error log, the management controller being coupled to the processing unit, wherein the bootstrap core executes the system control interrupt handler to avoid the system management mode, and wherein the system control interrupt handler logs the error of the hardware component into the system event log.

[0014] In more embodiments of the example system, the management controller is a baseboard management controller (BMC). In another embodiment, the computer system is a server. In another embodiment, the boot kernel is brought into system management mode and a system management interrupt handler is executed to detect an error; and after detecting the error, the system management interrupt handler leaves the system management mode. In another embodiment, the hardware element is one of a peripheral component interconnect express (PCIe) device, a dual in-line memory module (DIMM), a hard disk drive (HDD), a universal serial bus (USB) device, a serial peripheral interface (SPI) device, and a system management bus (SMBUS) device. In another embodiment, the processing unit includes a plurality of processor cores, and the processor cores include the boot kernel. In another embodiment, the processing unit includes a south bridge chip, and the south bridge chip includes silicon, where the silicon implements reliability-availability-serviceable (RAS) features. In another embodiment, the system control interrupt handler performs error detection. In another embodiment, the system control interrupt handler is initiated by a signal from a general purpose input output (GPIO) controller. In another embodiment, the system control interrupt handler is directly initiated by silicon, and the silicon triggers a system control interrupt.

[0015] Another example disclosed is a method for reducing downtime, including: receiving notification of an error in a hardware element through silicon on a processing unit; detecting an error from the hardware element; and logging error data of the hardware element into a system error log managed by a management controller via a system control interrupt handler executed by a processor core of the processing unit.

[0016] In another embodiment of the example system, error detection is performed via a system management interrupt controller; and the computer system enters system management mode during error detection and leaves system management mode when logged error data has been logged. In another embodiment, the management controller is a baseboard management controller (BMC). In another embodiment, the computer system is a server. In another embodiment, the processor core is one of multiple processor cores that are operational to process execution threads at the same time an error log occurs. In another embodiment, the hardware element is one of a peripheral component interconnect express (PCIe) device, a dual in-line memory module (DIMM), a hard disk drive (HDD), a universal serial bus (USB) device, a serial peripheral interface (SPI) device, and a system management bus (SMBUS) device. In another embodiment, the processing unit includes a south bridge chip that includes silicon, where the silicon performs reliability-availability-serviceable (RAS) features. In another embodiment, error detection is performed via a system control interrupt handler that is executed by a processor core. In another embodiment, the system control interrupt handler is initiated by a signal from a general purpose input output (GPIO) controller. In another embodiment, the system control interrupt handler is initiated directly by silicon that triggers a system control interrupt. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present disclosure will be better understood from the following description of exemplary embodiments in conjunction with the accompanying drawings.

[0018] Figure 1A is a block diagram of a prior art computing system that initiates RAS services.

[0019] Figure 1B is a timing diagram of a prior art computing system that illustrates the issue of SMM blocking other processors from operating.

[0020] Figure 2It is a block diagram of an element of an operation system that enables certain SMM features to be executed by a system control interrupt handler.

[0021] Figure 3 is Figure 2 a timing diagram of a computer system in [reference], showing the performance of RAS features executed by an SCI handler during SMM according to an example routine.

[0022] Figure 4 is for Figure 2 a flowchart of an SCI handler interrupting and offloading RAS features in [reference].

[0023] Figure 5 is Figure 2 a flowchart of an SCI handler executing certain RAS features in [reference].

[0024] Figure 6 is a timing diagram of an example routine that is specifically executed by an SCI handler from an in-band SCI trigger in a computer system in Figure 2 [reference].

[0025] Figure 7 is a flowchart of an example routine for RAS with SCI that is only carried out with an in-band SCI trigger.

[0026] Figure 8 is a timing diagram of an example routine that executes RAS services initiated with a hardware pin.

[0027] Figure 9 is a timing diagram of an example routine for RAS with SCI that is only carried out with a GPIO pin trigger that can handle SCI.

[0028] This disclosure is capable of various modifications and alternative forms. Certain representative embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it is to be understood that the present invention is not intended to be limited to the particular forms disclosed. On the contrary, this disclosure covers all modifications, equivalents, and alternatives falling within the scope and spirit of the present invention as defined by the appended claims. Detailed Description

[0029] The present invention may be implemented in many different forms. Representative embodiments are shown in the accompanying drawings and will be described in detail herein. This disclosure is an example or illustration of the principles of the present invention and is not intended to limit the broad aspects of the present disclosure to the embodiments shown. On this basis, elements and limitations disclosed, for example, in paragraphs such as the abstract, summary of the invention, and embodiments, but not specifically recited in the claims, should not be incorporated into the claims singly, collectively, implicitly, inferentially, or otherwise. For the purposes of this detailed description, unless specifically disclaimed, the singular form includes the plural form and vice versa; and the term "comprising" means "including without limitation". In addition, approximate terms such as "about", "almost", "substantially", "approximately", and similar terms can be used herein to mean "within", "close to", "near", "within the range of 3 - 5%", or "within acceptable manufacturing tolerances", or any logical combination thereof.

[0030] This disclosure relates to a routine that enables the mechanism of the system management mode (SMM) to perform error logging, and also enables execution threads to be executed by processing cores in a computer system. The exemplary routine offloads a high - latency SMM service routine for performing error logging. The offloaded error - logging routine includes a system control interrupt (SCI) handler, communication between the basic input / output system (BIOS) and the baseboard management controller (BMC). Since the SCI only requires one execution thread to execute the Advanced Configuration and Power Interface (ACPI) protocol, the handoff of routines from the SMM can be achieved. Since the communication between the BIOS and the BMC for error logging occupies most of the time of the SMM, when the error - logging routine is offloaded to the system control interrupt (SCI) handler, the downtime of the SMM from the computer system is significantly reduced.

[0031] Since the routine unloads some or all of the RAS services from the system management SMI handler to the SCI handler, the execution of any RAS service is not impaired. This allows all RAS services to be executed without requiring a long downtime. In addition, since the execution of SMM is limited in time and scale, the boot processor cannot perform large-scale calculations, such as quickly logging errors. When error logging is performed in the SCI handler, the RAS services can be executed more efficiently.

[0032] When the RAS silicon detects any error, the computer system triggers a RAS system management interrupt (SMI). The RAS SMI handler in this example only provides services for error detection during the period of SMM. Services such as event logging with a high latency are unloaded to the SCI handler. Therefore, the SMI handler only performs error detection and stores information in the Advanced Configuration and Power Interface (ACPI) memory. After that, the example routine triggers the SCI handler to perform error logging. This allows the system to exit the system management interrupt (SMI) and SMM. After leaving the SMI, the SCI handler executes the remaining RAS services, such as error logging.

[0033] The SCI handler identifies whether the error is a RAS General Purpose Event (GPE). If there is a RAS GPE, the SCI handler parses the RAS ACPI memory to identify whether there is any valid information that needs to be logged into the BMC system error log (SEL). Once the error is logged into the SEL, the routine exits the SCI handler.

[0034] Figure 2is a block diagram of a computer system 100 that enables the RAS service to initiate error reporting using an SCI processor while also enabling execution threads and other programs to operate. In this example, the computer system 100 is a server, but the principles disclosed herein can include any computer system with an operating system that embeds the RAS service and uses the System Management Mode (SMM). The computer system 100 includes a Central Processing Unit (CPU) 110 that has a south bridge chip 112, a platform BIOS 114, a Baseboard Management Controller (BMC) 116, and an operating system 118. The ACPI memory 122 can be defined as the system memory that is part of the computer system 100. The central processing unit 100 can also include multiple processing cores 124. One of the processing cores 124 can be a bootstrap processor (BSP) that is accessed by the BIOS 114 during a start-up routine.

[0035] A bus 130 enables communication between the BMC 116 and the platform BIOS 114. The south bridge chip 112 can have a General Purpose Input Output (GPIO) controller 132 that controls GPIO inputs 134. In this example, the GPIO inputs 134 can communicate with the RAS silicon as will be explained below. Thus, the RAS silicon can convey signals to the GPIO inputs 134 or other GPIO inputs on the processor chipset.

[0036] Computer system 100 includes various hardware peripherals. In this example, the hardware peripherals include a Peripheral Component Interconnect Express (PCIe) device 140, a Dual In-line Memory Module (DIMM) 142, hard disk drives (HDDs) 144, Universal Serial Bus (USB) devices 146, Serial Peripheral Interface (SPI) devices 148, and System Management Bus (SMBUS) devices 150. The PCIe device can include expansion cards such as a Network Interface Card (NIC), a Redundant Array of Inexpensive Disks (RAID) card, a Field Programmable Gate Array (FPGA) card, a Solid State Drive (SSD) card, a Dual In-line Memory, and a Graphic Processing Unit (GPU) card. It should be understood that there can be many such devices and can include different types of devices from those described herein.

[0037] The south bridge chip 112 performs basic input / output functions for the computer system 100 and includes RAS silicon 210. The RAS silicon 210 is a logical complex that exists in the processing core and the south bridge chip 112. The RAS silicon 210 monitors the reliability, availability, and maintainability of different hardware peripherals. The platform BIOS 114 includes a RAS system management mode interrupt (SMI) handler 214 and a RAS system control interrupt (SCI) handler 216. In this example, the RAS SMI handler 214 processes system management interrupts and performs error detection. In this example, the SCI handler 216 provides notification of an interrupt entry to the operating system 118, such as a system control interrupt (SCI) or a non-maskable interrupt (NMI). In this example, the RAS SMI handler 214 is executed by the bootstrap core, and other cores are temporarily unable to enter the SMM. However, the RAS SCI handler 216 is executed by one of the processor cores 124, and the other cores can still be used by the operating system. The BMC 116 includes an internal memory that stores the system event log (SEL) 220. The SEL 220 stores the detected errors communicated from the BIOS 114.

[0038] When an SMM interrupt occurs, the RAS feature of writing error data is executed by the SCI handler 216, rather than by the RAS SMI handler 214 as in known systems. The RAS SCI handler 216 executes the RAS feature of writing error data, writing the error data from the malfunctioning device to the system event log (SEL) 220 in the BMC 116. Then, after the RAS SMI handler 214 detects an error, the system management interrupt and the SMM end. After error detection, the RAS SCI handler 216 performs error logging. Since the operating system 118 has left the SMM, the operating system 118 can run execution threads or other operations on the processing core because they were not suspended by the SMM.

[0039] Figure 3 is a timing diagram of an example routine that executes Figure 2System Management Mode (SMM) on computer system 100. In this example, a hardware device such as one of the PCIe devices 140 may malfunction, resulting in an error, namely operation 310. The RAS silicon 210 receives an error notification from the device 140 and performs operation 312 to call the SMI handler 214 with a System Management Interrupt (SMI). The SMI handler 214 performs operation 314 to communicate with the device 140 to detect and collect error-related information. The error information is stored in Figure 2 the ACPI memory 122. In this example, the RAS SCI handler 216 operates according to the ACPI protocol. The SMI handler 214 performs operation 318 to send the ACPI information on the error stored in Figure 2 the ACPI memory 122 to the RAS SCI handler 216. Then, the RAS SCI handler performs operation 316 to provide status information from the RAS silicon 210 and collect error information for error event logging to the RAS SCI handler 216. The SMI handler 214 performs operation 320 to initiate a System Control Interrupt (SCI) to the RAS SCI handler 216. The RAS SCI handler 216 starts operation 322 to perform event logging by sending the error data to the system event log described in the BMC 116. While the RAS SCI handler 216 is performing the error logging operation, the system has left the SMM and thus continues with other operations. The RAS SCI handler 216 performs operation 324 to notify the operating system 118 of the service for the error data stored in the ACPI memory 122.

[0040] Figure 4 is a flowchart 400 of an example routine that uses the RAS SCI handler 216 to process SMM interrupts to perform Figure 2RAS error logging features in computer system 100. In block 410, the RAS SMI handler 214 receives the RAS SMI. In block 412, the RAS SMI handler 214 identifies the RAS event, and the identified RAS event is the result of a hardware device error. Then, in block 414, the RAS SMI handler 214 determines whether the RAS event is found by cycling through each hardware device. In block 416, when the RAS event is found, the device with the error is identified by the routine. Then, in block 418, the routine determines whether a device with an error has been found. If a device with an error has been found, it proceeds to block 420, stores the information in the ACPI memory 122 via the ACPI protocol, and initiates the RAS SCI handler 216. Then, in block 422, the RAS SMI handler 214 completes its routine and leaves the SMM, and the remaining RAS features are transmitted to the RAS SCI handler 216. If the RAS event is not found in block 414, or if no hardware device with an error is found in block 418, it proceeds to block 422 and the system leaves the SMM.

[0041] If an error occurs in one of the hardware devices, the RAS SCI handler executes the RAS error logging feature. Figure 5 It is a flowchart 500 of the RAS error logging feature executed by the RAS SCI handler 216. In block 510, the routine starts the operation of the RAS SCI handler 216. Then, in block 512, the routine identifies the source of the system interrupt by reading the ACPI memory. Then, in block 514, the routine determines whether the RAS SCI has been triggered. In block 516, the routine validates and analyzes the RAS information received from the RAS SMI handler 214. Next, in block 518, the routine determines whether the ACPI RAS information is valid. If the information is valid, it proceeds to block 520, and the handler processes the RAS service, thus sending the error data to the SEL 220 on the BMC 116. Then, in block 522, the RAS SCI handler 216 will complete the routine. If there is no interrupt in block 512, or if the ACPI RAS information is invalid in block 518, it proceeds to block 522 and the routine will also terminate.

[0042] By Figure 2 executing all RAS services through the SCI handler 216 in, the downtime can be further reduced. Since the RAS SMI service is no longer required, the downtime of the computer system 100 is expected to be further shortened. By the procedure of executing all RAS services through the RAS SCI handler 216, there can be two different scenarios: in-band routines and out-of-band routines.

[0043] In the in-band routine, when the RAS silicon 210 detects an error, it triggers an in-band system control interrupt to signal the RAS SCI handler 216. The RAS SCI handler 216 performs all the functions originally on the RAS SMI handler 214, including error detection. Then, the RAS SCI handler 216 logs the error information into the SEL 220 in the BMC 116. After completing the error logging, the RAS SCI handler 216 exits the RAS service. In this way, all the error detection and logging features executed during the SCI do not encounter interruptions because the RAS SMI handler 214 is not called.

[0044] Alternatively, the RAS silicon 210 can generate a signal on a hardware pin, such as a signal on a GPIO pin, to signal an event. In this example, this signal is sent to the GPIO pin 134 that can handle the SCI and is received by the GPIO controller 132 on the south bridge chip 112. In this way, once the RAS silicon 210 detects an error, it can signal the RAS SCI handler 216 through the GPIO controller 132. The SCI handler 216 acts as an ACPI driver and first services the signal. The ACPI driver identifies whether a RAS General-Purpose Event (GPE) has occurred. If the GPE has occurred, the RAS SCI handler 216 processes all the RAS services.

[0045] Figure 6 It is a timing diagram of the procedure that specifically uses the RAS SCI handler 216 for the RAS service using an in-band interrupt trigger. Figure 6 It shows the interaction between the faulty hardware device 140, the RAS silicon 210, the RAS SCI handler 216, the BMC 116, and the operating system 118. As explained above, this example routine eliminates the need to call the Figure 2 RAS SMI handler in it, and thus avoids downtime from the SMM during the procedure.

[0046] Hardware components such as the PCIe card 140 may encounter an error, namely operation 610. This error creates an event from the RAS silicon 210. The RAS silicon 210 performs operation 610 and issues an in-band system control interrupt to the RAS SCI processor 216. The RAS SCI processor 216 performs operation 614 to detect and collect error information of operation 610 from the hardware component. The error information is stored in the ACPI memory. Then, the SCI processor 216 performs operation 616 to perform error logging by communicating with the BMC 116 and adding the error data to the system error log. Then, the SCI processor 216 performs operation 618 to notify the error to the operating system 118. As Figure 6 shown, during this procedure, the SMI processor 214 is not initiated. In this way, SMM is avoided, and processing can still be carried out during the period when the SCI processor 216 executes the RAS feature.

[0047] Figure 7 is a flowchart of an example routine for the RAS feature, which has a system control interrupt initiated by an in-band SCI trigger. At block 710, the RAS SCI processor 216 starts operating. At block 712, the SCI processor 216 begins to identify whether a RAS event has occurred. At block 714, the SCI processor 216 determines whether a RAS event is found in one of the hardware devices. If a RAS event is found, it proceeds to block 716, where the SCI processor 216 determines whether the hardware device with the error can be identified. At block 718, if an error is found from the hardware device, it proceeds to block 720, where the SCI processor 216 performs all available RAS services, including error detection and logging the error into the system event log described by the BMC 116. If a RAS event is not found at block 714, or if a device with an error is not found at block 718, it proceeds to block 722, where the RAS SCI processor 216 completes the routine.

[0048] Figure 8 is a timing diagram of the RAS service, which Figure 2 initiates a system control interrupt with the GPIO pin 134 that can handle SCI on the south bridge chip 112. Hardware components such as the PCIe card 140 may encounter an error, which is an event determined by the RAS silicon 210, namely operation 810. The RAS silicon 210 performs operation 812 to send a signal to the GPIO pin 134, which is received by the Figure 2 GPIO controller 132 in Figure 2The GPIO pin 134 therein sends the system control interrupt signal to the RAS SCI processor 216. The RAS SCI processor 216 detects and collects error information from the hardware component 140. The error information is stored in the ACPI memory 122. Then, the RAS SCI processor 216 performs operation 818 to perform error logging by communicating with the BMC 116 and adding the error data to the system error log. Then, the RAS SCI processor 216 performs operation 820 to notify the operating system 118 of the error. As Figure 8 shown, during this procedure, the SMI processor 214 is not initiated. In this way, SMM is avoided, and processing can still be performed during the execution of the RAS features by the RAS SCI processor 216.

[0049] Figure 9 is a flowchart 900 of a routine of RAS with SCI, where the routine proceeds only when the SCI is triggered by a GPIO pin that can handle the SCI. In block 910, the RAS SCI processor 216 starts operating. In block 912, the SCI processor 216 begins to identify the source of the system control interrupt. In block 914, the SCI processor 216 determines whether it has found that the system control interrupt is the result of a RAS event. If the RAS SCI processor 216 determines that the system control interrupt is the result of a RAS event, it proceeds to block 916, where the RAS SCI processor 216 begins to identify whether a RAS event has occurred. In block 918, the RAS SCI processor 216 determines whether it has found a RAS event. If a RAS event has been found, it proceeds to block 920, where the RAS SCI processor 216 determines whether it can identify the hardware device with an error. In block 922, if a device with an error has been found, it proceeds to block 924, where the RAS SCI processor 216 performs all available RAS services, including error detection and logging the error into the SEL 220 of the BMC 116. Then, in block 924, the RAS SCI processor 216 will complete the RAS services. If the system control interrupt is not the result of a RAS event in block 914, or if no RAS event is found in block 918, or if no device with an error is found in block 922, it proceeds to block 926, where the RAS SCI processor 216 will complete the routine.

[0050] Fourth, the flowcharts in Figures 5, 7, and 9 represent example machine-readable instructions that are used to Figure 2The RAS SCI processor 216 of the computer system 100 in [description] performs some or all of the RAS features. In this example, the machine-readable instructions include algorithms executed by (a) a processor; (b) a controller; and / or (c) one or more other suitable processing devices. The algorithms can be implemented by software stored on a tangible medium, such as flash memory, a CD-ROM, a floppy disk, a hard disk, a digital (versatile) video disk (DVD), or other memory devices. However, those of ordinary skill in the art will readily understand that all or part of the algorithms can alternatively be executed by devices other than the processor, and / or implemented by firmware or proprietary hardware in a known manner (e.g., executed by an application-specific integrated circuit [ASIC]; a programmable logic device [PLD]; a field-programmable logic device [FPLD]). For example, any or all elements of the interface can be executed by software, hardware, and / or firmware. Similarly, some or all of the machine-readable instructions represented by the flowchart can be executed manually. In addition, although the example algorithms are described with reference to the flowcharts illustrated in FIGS. 4, 5, 7, and 9, those of ordinary skill in the art will readily understand that many other methods can be used to execute the example machine-readable instructions. For example, the execution order of the blocks can be changed, and / or some of the described blocks can be changed, deleted, or combined.

[0051] As used in this application, the terms "element", "module", "system", or similar terms generally refer to a computer-related entity, which can be hardware (e.g., a circuit), a combination of hardware and software, software, or an entity related to the operation of a machine and having one or more specific functions. For example, an element can be, but is not limited to, a program executed on a processor (e.g., a digital signal processor), a processor, an object, an executable file, a thread of execution, a program, and / or a computer. As an example, an application executed on a controller, and the controller itself, can both be elements. One or more elements can reside within a program and / or a thread of execution, and an element can be confined to one computer and / or distributed between two or more computers. In addition, a "device" can take the form of specially designed hardware; general-purpose hardware made special by executing software thereon that enables the hardware to perform specific functions; software stored on a computer-readable medium; or a combination thereof.

[0052] Although various embodiments of the present invention have been described above, it should be understood that the described embodiments are presented only by way of example and not by way of limitation. Even though the present invention has been illustrated and described with reference to one or more embodiments, equivalent substitutions and modifications will occur to others skilled in the art upon reading and understanding this specification and the appended drawings. In addition, although a particular feature of the present invention may be disclosed only by one of several embodiments, such feature may be combined with one or more other features of other embodiments, and such other features may be desirable or advantageous for any given or particular application. Therefore, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Instead, the scope of the present invention should be defined by the following claims and their equivalents.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, if the terms "comprises", "has" or their variants are used in the embodiments and / or claims, such terms are intended to be included in a manner similar to the term "includes".

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and unless specifically defined herein, such terms will not be interpreted as idealized or overly formal concepts.

[0055] [Symbol Description]

[0056] 10: Computer system

[0057] 12: South bridge chip

[0058] 14: Basic Input / Output System (BIOS)

[0059] 16: Baseboard Management Controller (BMC)

[0060] 18: Operating System (OS)

[0061] 20: Reliability, Availability, and Serviceability (RAS) silicon

[0062] 22: Hardware device

[0063] 24: System Management Interrupt (SMI) handler

[0064] 26: System Control Interrupt (SCI) handler

[0065] 28: System Event Log (SEL)

[0066] 30: Hardware Device

[0067] 50 - 62: Operations

[0068] 100: Computer System

[0069] 110: Central Processing Unit (CPU)

[0070] 112: South Bridge Chip

[0071] 114: Basic Input / Output System (BIOS)

[0072] 116: Baseboard Management Controller (BMC)

[0073] 118: Operating System (OS)

[0074] 122: Advanced Configuration and Power Interface (ACPI) Memory

[0075] 124: Processing Core

[0076] 130: Bus

[0077] 132: General-Purpose Input / Output (GPIO) Controller

[0078] 134: GPIO Input

[0079] 140: Peripheral Component Interconnect Express (PCIe) Device

[0080] 142: Dual In-line Memory Module (DIMM)

[0081] 144: Hard Disk Drive (HDD)

[0082] 146: Universal Serial Bus (USB) Device

[0083] 148: Serial Peripheral Interface (SPI) Device

[0084] 150: System Management Bus (SMBUS) Device

[0085] 210: Reliability, Availability, and Serviceability (RAS) Silicon

[0086] 214: System Management Interrupt (SMI) Handler

[0087] 216: System Control Interrupt (SCI) Handler

[0088] 220: System Event Log (SEL)

[0089] 310 - 324: Operations

[0090] 400: Flowchart

[0091] 410 - 422: Blocks

[0092] 500: Flowchart

[0093] 510 - 522: Flowcharts

[0094] 610 - 618: Operations

[0095] 700: Flowchart

[0096] 710 - 722: Blocks

[0097] 810 - 820: Operations

[0098] 900: Flowchart

[0099] 910 - 926: Blocks

Claims

1. A computer system for reducing downtime, comprising: A basic input / output system chip; A processing unit having a boot kernel and silicon, the boot kernel executing a system management interrupt handler and a system control interrupt handler stored in the basic input / output system chip, the silicon for receiving error messages; Hardware components coupled to the processing unit, the hardware components sending error messages to the silicon; And A management controller containing a system error log, the management controller coupled to the processing unit, wherein the boot kernel executes the system control interrupt handler to avoid the system management mode, and wherein the system control interrupt handler logs the errors of the hardware components into the system error log; Wherein the boot kernel enters the system management mode and executes the system management interrupt handler to detect the error; And Wherein the system management interrupt handler leaves the system management mode after detecting the error.

2. The system according to claim 1, wherein the processing unit includes a south bridge chip, the south bridge chip includes the silicon, and wherein the silicon implements reliability, availability, and maintainability features.

3. The system according to claim 1, wherein the system control interrupt handler is initiated by a signal from a general-purpose input / output controller.

4. The system according to claim 1, wherein the system control interrupt handler is directly initiated by the silicon, the silicon triggering the system control interrupt.

5. A method for reducing downtime, comprising: Receiving, via silicon on a processing unit, notification of an error in a hardware component; Detecting the error from the hardware component; And Logging error data of the hardware component into a system error log managed by a management controller via a system control interrupt handler executed by a processor core of the processing unit, wherein the system control interrupt handler is executed by the processor core; Wherein the error detection is performed via a system management interrupt handler; and Wherein the computer system enters the system management mode during the error detection and leaves the system management mode when the logged error data has been logged.

6. The method according to claim 5, wherein the processing unit includes a south bridge chip, the south bridge chip includes the silicon, and wherein the silicon implements reliability, availability, and maintainability features.

7. The method according to claim 5, wherein the system control interrupt handler is initiated by a signal from a general-purpose input / output controller.

8. The method according to claim 5, wherein the system control interrupt handler is directly initiated by the silicon, the silicon triggering the system control interrupt.

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