Address allocation method and device for battery management system

Abstract

The present application proposes a method and device for allocating addresses for a battery management system, wherein the method includes: determining the address information of a target master control module in response to a first address pulse signal output by a master control module being received by the target master control module; determining the address information of other master control modules among N master control modules based on the difference between the address information of the target master control module and the first address pulse signal; each master control module outputs a second address pulse signal to a target slave control module connected to each master control module; determining the address information of a target slave control module connected to each master control module based on the second address pulse signal received by the target slave control module connected to each master control module; and determining the address information of other slave control modules among the slave control modules connected to each master control module based on the difference between the address information of the target slave control module connected to each master control module and the second address pulse signal. The present application can more efficiently allocate addresses for a battery management system.

Description

Technical Field

[0001] The present application relates to the technical field of battery management systems, and in particular to a method and device for allocating addresses for a battery management system. Background Art

[0002] With the continuous development of energy storage technology, the scale of energy storage power stations is growing towards the gigabyte level. Battery systems are composed of numerous battery modules, coordinated and controlled through a three-level architecture of master control, master control, and slave control. The large number of modular battery systems connected in series and parallel requires precise and efficient address allocation for each module to achieve refined management of the battery management system. Summary of the Invention

[0003] This application proposes a method and device for allocating addresses of a battery management system to achieve more efficient address allocation of the battery management system.

[0004] A first embodiment of the present application provides an address allocation method for a battery management system, wherein the battery management system includes: a master control module; N master control modules, wherein the master control module is sequentially connected to the N master control modules via an address signal line; each master control module is sequentially connected to at least one slave control module via an address signal line, wherein N is a positive integer; the method includes:

[0005] In response to the target main control module receiving the first address pulse signal output by the master control module, determining the address information of the target main control module; the target main control module is a main control module connected to the master control module among the N main control modules;

[0006] determining address information of other master control modules among the N master control modules according to a difference between the address information of the target master control module and the first address pulse;

[0007] Each of the master control modules outputs a second address pulse signal to a target slave control module connected to each of the master control modules; the target slave control module connected to each of the master control modules is a slave control module connected to each of the master control modules among the slave control modules sequentially connected to each of the master control modules;

[0008] determining address information of a target slave control module connected to each of the master control modules according to a second address pulse signal received by the target slave control module connected to each of the master control modules;

[0009] The address information of other slave control modules among the slave control modules connected to each of the master control modules is determined according to the address information of the target slave control module connected to each of the master control modules and the difference between the second address pulse.

[0010] The second embodiment of the present application provides an address allocation device for a battery management system, including:

[0011] a first determining module, configured to determine address information of a target main control module in response to the target main control module receiving the first address pulse signal output by the master control module; the target main control module being a main control module connected to the master control module among the N main control modules;

[0012] a second determining module, configured to determine address information of other master control modules among the N master control modules according to a difference between the address information of the target master control module and the first address pulse;

[0013] a sending module, configured to output a second address pulse signal to a target slave module connected to each master control module through each master control module; the target slave module connected to each master control module is a slave module connected to each master control module among the slave modules sequentially connected to each master control module;

[0014] a third determining module, configured to determine address information of a target slave control module connected to each of the master control modules according to a second address pulse signal received by the target slave control module connected to each of the master control modules;

[0015] The fourth determining module is configured to determine the address information of other slave control modules among the slave control modules connected to each of the master control modules according to the address information of the target slave control module connected to each of the master control modules and the difference between the second address pulses.

[0016] The technical solution provided according to the embodiments of the present application may include the following beneficial effects: the present application realizes the automatic allocation of addresses of the master control module and the slave control module of the battery management system without adding additional circuits, and is easy to implement in practical applications, thereby achieving more efficient address allocation of the battery management system.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a flow chart of an address allocation method for a battery management system provided in an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of a battery management system provided in an embodiment of the present application;

[0021] Figure 3 This is a flow chart of another method for allocating addresses for a battery management system provided in an embodiment of the present application;

[0022] Figure 4 This is a flow chart of another method for allocating addresses for a battery management system provided in an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of a battery management system provided in an embodiment of the present application;

[0024] Figure 6 This is a structural block diagram of an address allocation device for a battery management system provided in an embodiment of the present application;

[0025] Figure 7 This is a structural block diagram of another address allocation device for a battery management system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0027] The present application provides a method and apparatus for allocating addresses for a battery management system. Specifically, the method and apparatus for allocating addresses for a battery management system according to an embodiment of the present application will be described below with reference to the accompanying drawings.

[0028] Figure 1 This is a flow chart of an address allocation method for a battery management system provided by an embodiment of the present application. The battery management system may include: a master control module; N master control modules, the master control module is sequentially connected to the N master control modules via address signal lines; each master control module is sequentially connected to at least one slave control module via address signal lines, where N is a positive integer. For example, Figure 2 As shown, the battery management system may include: a master control module and N master control modules, the master control module is sequentially connected to the N master control modules via address signal lines, each master control module is sequentially connected to at least one slave control module via address signal lines, wherein the number of slave control modules sequentially connected to each master control module may be the same or different. Figure 2 The number M1 of slave control modules sequentially connected to the master control module 1 can be the same as or different from the number M2 of slave control modules sequentially connected to the master control module 2. In addition, the battery management system also includes a communication system for communication between the master control module and the N master control modules, and between each master control module and the slave control modules sequentially connected to each master control module, such as Figure 2As shown, communication between modules can be achieved through the CAN communication bus, and other communication methods can also be used, which are not limited in this application.

[0029] like Figure 1 As shown, the address allocation method of the battery management system may include the following steps.

[0030] Step 101: In response to a target main control module receiving a first address pulse signal output by a master control module, determine address information of the target main control module, which is a main control module among N main control modules connected to the master control module.

[0031] As an example, Figure 2 As shown, among the N master control modules, master control module 1 is connected to the master control module, making master control module 1 the target master control module. When the target master control module receives the first address pulse signal output by the master control module, the address information of the target master control module is determined. As one possible implementation, the number of pulses in the first address pulse signal received by the target master control module can be used as the address information of the target master control module.

[0032] It should be noted that the first address pulse signal output by the master control module to the target main control module is a preset value.

[0033] Step 102 : determining the address information of other master control modules among the N master control modules according to the address information of the target master control module and the difference between the first address pulse.

[0034] The first address pulse difference is a preset value. After the target master control module is assigned an address, the second master control module (the second master control module in the master control modules sequentially connected to the main control module, for example) is sent based on the address information of the target master control module and the first address pulse difference. Figure 2 In the illustrated embodiment, the master control module 2) sends a first address pulse signal. The second master control module determines address information based on the first address pulse signal sent by the target master control module. For example, the second master control module uses the number of pulses in the received first address pulse signal as address information. After the second master control module is assigned an address, the address information of the third master control module is determined based on the difference between the address information of the second master control module and the first address pulse signal. This process continues in this manner until the address information of the Nth master control module is determined.

[0035] In step 103 , each master control module outputs a second address pulse signal to a target slave control module connected to each master control module; wherein the target slave control module connected to each master control module is a slave control module connected to each master control module among the slave control modules sequentially connected to each master control module.

[0036] As an example, in Figure 2In the illustrated embodiment, the slave control modules such as the slave control module 11 connected to the master control module 1 , the slave control module 21 connected to the master control module 2 , and the slave control module N1 connected to the master control module N are target slave control modules.

[0037] It should be noted that the second address pulse signal output by each master control module to the target slave control module connected to each master control module is a preset value.

[0038] Step 104 : determining address information of a target slave control module connected to each master control module according to the second address pulse signal received by the target slave control module connected to each master control module.

[0039] As a possible implementation manner, the number of pulses of the second address pulse signal received by the target slave control module may be used as the address information of the target slave control module.

[0040] Step 105 : determining the address information of other slave control modules connected to each master control module according to the address information of the target slave control module connected to each master control module and the difference between the second address pulses.

[0041] It should be noted that the second address pulse difference is a preset value. After the target slave control module connected to each master control module is assigned an address, the second slave control module among the slave control modules connected to each master control module (for example, the second slave control module among the slave control modules connected to each master control module in sequence) is sent based on the address information of the target slave control module connected to each master control module and the second address pulse difference. Figure 2 In the illustrated embodiment, among the slave modules sequentially connected to the master control module 1, slave control module 12 is the second slave control module; among the slave modules sequentially connected to the master control module 2, slave control module 22 is the second slave control module). A second address pulse signal is sent to the target slave control module. The second slave control module determines its address information based on the second address pulse signal sent by the target slave control module. After the second slave control module connected to each master control module is assigned an address, the address information of the third slave control module is determined based on the difference between the address information of the second slave control module and the second address pulse signal. This process is repeated until the address information of the remaining slave control modules connected to each master control module is determined. When all the slave control modules connected to a particular master control module have been assigned address information, a slave control module configuration completion feedback message is sent to the master control module via the communication bus of the communication system. When all N master control modules in the battery management system receive the slave control module configuration completion feedback message, the configuration completion feedback message is sent to the master control module via the communication bus of the communication system, thus completing the address allocation of the battery system.

[0042] According to the address allocation method of the battery management system of the embodiment of the present application, the addresses of the master control module and the slave control module of the battery management system are automatically allocated without adding additional circuits, and it is easy to implement in practical applications, thereby achieving more efficient address allocation of the battery management system.

[0043] Figure 3 FIG. 1 is a flow chart of another method for allocating addresses of a battery management system provided in an embodiment of the present application. Figure 3 As shown, the address allocation method of the battery management system may include the following steps.

[0044] Step 301 : In response to a target main control module receiving a first address pulse signal outputted by a master control module, determining address information of a target main control module; the target main control module is a main control module among N main control modules connected to the master control module.

[0045] Step 302: Determine the address information of the second master control module according to the difference between the address information of the target master control module and the first address pulse.

[0046] It should be noted that the second main control module is the second main control module among the main control modules sequentially connected to the main control module, for example Figure 2 The main control module 2 in the embodiment shown.

[0047] In one possible implementation, the number of pulses in the first address pulse signal sent by the target master control module to the second master control module can be determined based on the difference between the address information of the target master control module and the first address pulse. Based on the number of pulses in the first address pulse signal, the target master control module sends a first address pulse signal with a corresponding number of pulses to the second master control module. The address information of the second master control module is determined based on the number of pulses in the first address pulse signal received by the second master control module.

[0048] As an example, the address information of the target master control module can be added to the first address pulse difference to obtain the number of pulses in the first address pulse signal sent by the target master control module to the second master control module. For example, assuming the address information of the target master control module is 1 and the first address pulse difference is set to 1, the number of pulses in the first address pulse signal sent by the target master control module to the second master control module is determined to be 2. Based on the number of pulses in the first address pulse signal received by the second master control module, the address information of the second master control module is determined. Optionally, the number of pulses "2" in the first address pulse signal received by the second master control module can be used as the address information of the second master control module.

[0049] Step 303 : Determine the address information of the (i+1)th master control module according to the difference between the address information of the i-th master control module and the first address pulse, where 2≤i≤N−1.

[0050] As can be seen from step 302 above, the current value i is 2, and the address information of the second master control module is determined. Based on the difference between the address information of the second master control module and the first address pulse, the address information of the third master control module is determined, and the current value i is assigned to 3. Based on the difference between the address information of the third master control module and the first address pulse, the address information of the fourth master control module is determined, and the current value i is assigned to 4. This process is repeated until i equals N-1, where 2≤i≤N-1.

[0051] In step 304, each master control module outputs a second address pulse signal to a target slave control module connected to each master control module; wherein the target slave control module connected to each master control module is a slave control module connected to each master control module among the slave control modules sequentially connected to each master control module.

[0052] Step 305 : determining address information of the target slave control module connected to each master control module according to the second address pulse signal received by the target slave control module connected to each master control module.

[0053] Step 306 : Determine the address information of the second slave control module among the slave control modules connected to each master control module according to the address information of the target slave control module connected to each master control module and the difference between the second address pulse.

[0054] It should be noted that the second slave control module among the slave control modules connected to each master control module is the second slave control module among the slave control modules sequentially connected to each master control module. Figure 2 In the illustrated embodiment, among the slave control modules sequentially connected to the master control module 1 , the slave control module 12 is the second slave control module; among the slave control modules sequentially connected to the master control module 2 , the slave control module 22 is the second slave control module.

[0055] In one possible implementation, the number of pulses of the second address pulse signal sent by the target slave module connected to each master control module to the second slave module among the slave modules connected to each master control module can be determined based on the address information of the target slave module connected to each master control module and the difference between the second address pulses. Based on the number of pulses of the second address pulse signal, the target slave module connected to each master control module sends a corresponding number of second address pulse signals to the second slave module among the slave modules connected to each master control module. The address information of the second slave module among the slave modules connected to each master control module is determined based on the number of pulses of the second address pulse signal received by the second slave module.

[0056] As an example, the address information of the target slave module connected to each master module can be added to the second address pulse difference to obtain the number of pulses of the second address pulse signal sent by the target slave module connected to each master module to the second slave module among the slave modules connected to each master module. Figure 2 Taking the illustrated embodiment as an example, assuming that the address information of the target slave module 21 connected to the master module 2 is 1 and the second address pulse difference is set to 1, the number of pulses of the second address pulse signal sent by the target slave module 21 connected to the master module 2 to the second slave module 22 among the slave modules connected to the master module 2 is determined to be 2. Based on the number of pulses of the second address pulse signal received by the second slave module 22, the address information of the second slave module 22 is determined. Alternatively, the number of pulses "2" of the second address pulse signal received by the second slave module 22 can be used as the address information of the second slave module 22.

[0057] Step 307: Determine the address information of the j+1th slave control module among the slave control modules connected to each master control module based on the difference between the address information of the jth slave control module among the slave control modules connected to each master control module and the second address pulse, where 2≤j≤M-1; M is the number of slave control modules connected to each master control module.

[0058] As can be seen from step 306 above, the current j is 2, and the address information of the second slave module connected to each master module is determined. Based on the difference between the address information of the second slave module connected to each master module and the second address pulse, the address information of the third slave module connected to each master module is determined, and the current j is assigned a value of 3. Based on the difference between the information address of the third slave module connected to each master module and the second address pulse, the address information of the fourth slave module connected to each master module is determined, and the current j is assigned a value of 4. This continues in this manner until j equals M-1, where 2≤j≤M-1; M is the number of slave modules connected to each master module.

[0059] According to the address allocation method of the battery management system of the embodiment of the present application, the address information of the N master control modules in the battery management system is determined in sequence based on the address information of the target master control module and the first address pulse difference. After the master control module determines the address information, it sends a second address pulse signal to the target slave control module connected to each master control module to determine the address information of the target slave control module connected to each master control module. Based on the address information of the target slave control module connected to each master control module and the second address pulse difference, the address information of the other slave control modules connected to each master control module in sequence is determined in sequence. The automatic address allocation of the master control module and the slave control module of the battery management system is achieved without adding additional circuits, thereby improving the accuracy of the address allocation of the battery management system.

[0060] It should be noted that when the master control module or slave control module in the battery management system is repaired, replaced, or added, the address of the master control module and / or slave control module needs to be reconfigured. In order to efficiently reconfigure the address of the master control module and / or slave control module, this application also proposes an address allocation method for a battery management system, which can reallocate the address of the master control module and / or slave control module based on different configuration requests. Figure 4 This is a flow chart of another method for allocating addresses to a battery management system provided in an embodiment of the present application. Figure 4 As shown, the address allocation method of the battery management system may include the following steps.

[0061] Step 401: In response to a target main control module receiving a first address pulse signal output by a master control module, determine the address information of the target main control module. The target main control module is a main control module connected to the master control module among the N main control modules.

[0062] Step 402 : determining the address information of other master control modules among the N master control modules according to the address information of the target master control module and the difference between the first address pulse.

[0063] In step 403, each master control module outputs a second address pulse signal to a target slave control module connected to each master control module; wherein the target slave control module connected to each master control module is a slave control module connected to each master control module among the slave control modules sequentially connected to each master control module.

[0064] Step 404 : determining address information of the target slave control module connected to each master control module according to the second address pulse signal received by the target slave control module connected to each master control module.

[0065] Step 405 : determining the address information of other slave control modules connected to each master control module according to the address information of the target slave control module connected to each master control module and the difference between the second address pulses.

[0066] Step 406 : In response to the first master control module receiving the slave control module reconfiguration request, re-allocate address information to the slave control modules sequentially connected to the first master control module.

[0067] It should be noted that when a slave control module in the battery management system is repaired or replaced, a slave control module reconfiguration request is sent to the master control module (i.e., the first master control module described in step 406) connected to the slave control module undergoing repair or replacement via the communication bus of the communication system, and address information is reassigned to the slave control modules that are sequentially connected to the first master control module. Alternatively, when a slave control module connected to a master control module is added to the battery management system, a slave control module reconfiguration request is sent to the master control module (i.e., the first master control module described in step 406) via the communication bus of the communication system, and address information is reassigned to the slave control modules that are sequentially connected to the first master control module.

[0068] As an example, in Figure 5 In the embodiment shown (wherein, Figure 5 The communication bus is not shown, only the modules and address signal lines in the battery management system are shown). Among the slave control modules connected to the master control module 2, a slave control module 2Mˊ2 is added. The first master control module 2 receives a slave control module reconfiguration request and re-assigns address information to the slave control modules 21, 22... 2Mˊ2 connected to the first master control module 2 according to the address information of the first master control module 2.

[0069] Step 407: In response to the master control module receiving a request to update the configuration of the master control module, the master control module reallocates address information to the N master control modules; or, in response to the master control module receiving a request to add a new configuration to the master control module, the master control module in the battery management system and at least one slave control module connected in sequence to each master control module are reallocated address information.

[0070] It should be noted that when a master control module in the battery management system is repaired or replaced, a master control module update configuration request is sent to the master control module via the communication bus of the communication system, and address information is reassigned to the N master control modules. When a master control module connected to the master control module is added to the battery management system, a master control module new configuration request is sent to the master control module via the communication bus of the communication system, and address information is reassigned to the master control module and at least one slave control module connected to each master control module in the battery management system.

[0071] In the embodiment of the present application, steps 401 to 405 can be implemented respectively using any of the methods in the embodiments of the present application, and the present application does not make any specific limitations on this and will not elaborate on it.

[0072] The address allocation method for a battery management system according to an embodiment of the present application automatically allocates addresses for the master and slave control modules of the battery management system without adding additional circuitry. Furthermore, when a master or slave control module in the battery management system is repaired, replaced, or added, the addresses of the master and / or slave control modules can be reallocated based on different configuration requests, providing good redundancy and improving the efficiency of reallocating the addresses of the master and / or slave control modules.

[0073] Figure 6 This is a structural block diagram of an address allocation device for a battery management system provided in an embodiment of the present application. Figure 6 As shown, the address allocation device of the battery management system may include a first determining module 601 , a second determining module 602 , a sending module 603 , a third determining module 604 and a fourth determining module 605 .

[0074] Specifically, the first determining module 601 is configured to determine the address information of a target main control module in response to the target main control module receiving the first address pulse signal output by the main control module; the target main control module is a main control module among the N main control modules connected to the main control module.

[0075] The second determining module 602 is configured to determine the address information of other master control modules among the N master control modules according to the difference between the address information of the target master control module and the first address pulse.

[0076] The sending module 603 is used to output a second address pulse signal to the target slave module connected to each master control module through each master control module; the target slave module connected to each master control module is a slave module connected to each master control module among the slave modules connected to each master control module in sequence.

[0077] The third determining module 604 is configured to determine address information of a target slave control module connected to each master control module according to the second address pulse signal received by the target slave control module connected to each master control module.

[0078] The fourth determining module 605 is configured to determine the address information of other slave control modules connected to each master control module according to the address information of the target slave control module connected to each master control module and the difference between the second address pulses.

[0079] In some embodiments of the present application, the second determination module 602 is specifically used to determine the address information of the second master control module based on the difference between the address information of the target master control module and the first address pulse; and to determine the address information of the i+1th master control module based on the difference between the address information of the i-th master control module and the first address pulse, where 2≤i≤N-1.

[0080] In some embodiments of the present application, the second determination module 602 is also used to determine the number of pulses of the first address pulse signal sent by the target master control module to the second master control module based on the address information of the target master control module and the difference between the first address pulse; wherein, the target master control module sends a first address pulse signal with a corresponding number of pulses to the second master control module based on the number of pulses of the first address pulse signal; and determines the address information of the second master control module based on the number of pulses of the first address pulse signal received by the second master control module.

[0081] In some embodiments of the present application, the second determining module 602 is further configured to use the number of pulses of the first address pulse signal received by the second master control module as the address information of the second master control module.

[0082] In some embodiments of the present application, the fourth determination module 605 is specifically used to determine the address information of the second slave control module among the slave control modules connected to each master control module based on the address information of the target slave control module connected to each master control module and the difference between the second address pulse; and determine the address information of the j+1th slave control module among the slave control modules connected to each master control module based on the address information of the jth slave control module among the slave control modules connected to each master control module and the difference between the second address pulse, where 2≤j≤M-1; M is the number of slave control modules connected to each master control module.

[0083] In some embodiments of the present application, the fourth determination module 605 is also used to determine the number of pulses of the second address pulse signal sent by the target slave control module connected to each master control module to the second slave control module among the slave control modules connected to each master control module based on the address information of the target slave control module connected to each master control module and the difference between the second address pulses; wherein, the target slave control module connected to each master control module sends the second address pulse signal with a corresponding number of pulses to the second slave control module among the slave control modules connected to each of the master control modules based on the number of pulses of the second address pulse signal; and determine the address information of the second slave control module among the slave control modules connected to each master control module based on the number of pulses of the second address pulse signal received by the second slave control module among the slave control modules connected to each master control module.

[0084] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0085] According to the address allocation device of the battery management system of the embodiment of the present application, the addresses of the master control module and the slave control module of the battery management system are automatically allocated without adding additional circuits, and it is easy to implement in practical applications, thereby achieving more efficient address allocation of the battery management system.

[0086] Figure 7 This is a structural block diagram of another address allocation device for a battery management system provided in an embodiment of the present application. Figure 6 On the basis of Figure 7 As shown, the address allocation device of the battery management system further includes a fifth determination module 706 and a sixth determination module 707 .

[0087] Specifically, the fifth determining module 706 is configured to re-allocate address information to the slave control modules sequentially connected to the first master control module in response to the first master control module receiving the slave control module reconfiguration request.

[0088] The sixth determination module 707 is used to reallocate address information to N master control modules in response to the master control module receiving a master control module configuration update request; or, in response to the master control module receiving a master control module new configuration request, reallocate address information to the master control module in the battery management system and at least one slave control module connected in sequence to each master control module.

[0089] in, Figure 7 701-705 and Figure 6 601-605 have the same function and structure.

[0090] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0091] The address allocation device for a battery management system according to an embodiment of the present application automatically allocates addresses for the master and slave control modules of the battery management system without adding additional circuitry. Furthermore, when a master or slave control module in the battery management system is repaired, replaced, or added, the addresses of the master and / or slave control modules can be reallocated based on different configuration requests. This provides good redundancy and improves the efficiency of reallocating addresses for the master and / or slave control modules.

[0092] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0093] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0094] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0095] The logic and / or steps represented in the flowchart or otherwise described herein may be considered, for example, as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device).

[0096] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0097] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0098] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for allocating addresses for a battery management system, characterized in that: The battery management system includes: a master control module; N master control modules, wherein the master control module is sequentially connected to the N master control modules via address signal lines; each master control module is sequentially connected to at least one slave control module via address signal lines, wherein N is a positive integer; and the method includes the following steps: In response to the target main control module receiving the first address pulse signal output by the master control module, determining the address information of the target main control module; the target main control module is a main control module connected to the master control module among the N main control modules; determining address information of other master control modules among the N master control modules according to a difference between the address information of the target master control module and the first address pulse; Each of the master control modules outputs a second address pulse signal to a target slave control module connected to each of the master control modules; the target slave control module connected to each of the master control modules is a slave control module connected to each of the master control modules among the slave control modules sequentially connected to each of the master control modules; determining address information of a target slave control module connected to each of the master control modules according to a second address pulse signal received by the target slave control module connected to each of the master control modules; The address information of other slave control modules among the slave control modules connected to each of the master control modules is determined according to the address information of the target slave control module connected to each of the master control modules and the difference between the second address pulse.

2. The method according to claim 1, wherein The determining, based on the difference between the address information of the target master control module and the first address pulse, address information of other master control modules among the N master control modules includes: Determining the address information of the second main control module according to the difference between the address information of the target main control module and the first address pulse; The address information of the (i+1)th main control module is determined according to the difference between the address information of the (i)th main control module and the first address pulse, wherein 2≤i≤N-1.

3. The method according to claim 2, wherein Determining the address information of the second main control module according to the difference between the address information of the target main control module and the first address pulse includes: determining, based on the difference between the address information of the target master control module and the first address pulse, the number of pulses of the first address pulse signal sent by the target master control module to the second master control module; wherein, based on the number of pulses of the first address pulse signal, the target master control module sends a first address pulse signal with a corresponding number of pulses to the second master control module; The address information of the second main control module is determined according to the number of pulses of the first address pulse signal received by the second main control module.

4. The method according to claim 3, wherein The determining the address information of the second main control module according to the number of pulses of the first address pulse signal received by the second main control module includes: The number of pulses of the first address pulse signal received by the second main control module is used as the address information of the second main control module.

5. The method according to claim 1, wherein The determining, based on the address information of the target slave module connected to each of the master control modules and the difference between the second address pulse, address information of other slave control modules among the slave control modules connected to each of the master control modules includes: determining the address information of a second slave control module among the slave control modules connected to each of the master control modules according to the difference between the address information of the target slave control module connected to each of the master control modules and the second address pulse; According to the address information of the jth slave control module among the slave control modules connected to each of the master control modules and the difference between the second address pulse, the address information of the j+1th slave control module among the slave control modules connected to each of the master control modules is determined, where 2≤j≤M-1; M is the number of slave control modules connected to each of the master control modules.

6. The method according to claim 5, wherein The determining, based on the address information of the target slave module connected to each of the master control modules and the difference between the second address pulse, the address information of the second slave control module among the slave control modules connected to each of the master control modules comprises: determining the number of pulses of the second address pulse signal sent by the target slave control module connected to each of the master control modules to the second slave control module among the slave control modules connected to each of the master control modules based on the address information of the target slave control module connected to each of the master control modules and the difference between the second address pulses; wherein, based on the number of pulses of the second address pulse signal, the target slave control module connected to each of the master control modules sends the second address pulse signal with a corresponding number of pulses to the second slave control module among the slave control modules connected to each of the master control modules; The address information of the second slave control module among the slave control modules connected to each of the master control modules is determined according to the number of pulses of the second address pulse signal received by the second slave control module among the slave control modules connected to each of the master control modules.

7. The method according to claim 1, wherein: Also includes: In response to the first master control module receiving the slave control module reconfiguration request, the first master control module re-allocates address information for the slave control modules sequentially connected to the first master control module.

8. The method according to claim 7, wherein: Also includes: In response to the master control module receiving the master control module configuration update request, re-allocating address information for the N master control modules; Or, in response to the master control module receiving a new configuration request from a master control module, the master control module in the battery management system and at least one slave control module sequentially connected to each of the master control modules are reassigned address information.

9. An address allocation device for a battery management system, characterized in that: The battery management system includes: a master control module; N master control modules, wherein the master control module is sequentially connected to the N master control modules via address signal lines; each master control module is sequentially connected to at least one slave control module via address signal lines, wherein N is a positive integer; and the device includes: a first determining module, configured to determine address information of a target main control module in response to the target main control module receiving the first address pulse signal output by the master control module; the target main control module being a main control module connected to the master control module among the N main control modules; a second determining module, configured to determine address information of other master control modules among the N master control modules according to a difference between the address information of the target master control module and the first address pulse; a sending module, configured to output a second address pulse signal to a target slave module connected to each master control module through each master control module; the target slave module connected to each master control module is a slave module connected to each master control module among the slave modules sequentially connected to each master control module; a third determining module, configured to determine address information of a target slave control module connected to each of the master control modules according to a second address pulse signal received by the target slave control module connected to each of the master control modules; The fourth determining module is configured to determine the address information of other slave control modules among the slave control modules connected to each of the master control modules according to the address information of the target slave control module connected to each of the master control modules and the difference between the second address pulses.

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