A simulation verification method and system

Abstract

Embodiments of the present application disclose a simulation verification method and related equipment, which are used for reducing the workload of chip simulation verification. The method comprises the following steps: defining a part of storage space of a system chip end as a target interaction space in advance; wherein, the function module comprises a plurality of use cases, one of which completes the input of excitation by cyclically executing the following three steps: step one, a verification platform end assigns values to the target interaction space, the target interaction space comprising a read-write identification bit, a read-write address, read-write data and a read-write completion identification bit; step two, the system chip end queries the read-write identification bit in the target interaction space, and completes the read-write operation in the system chip end according to the identification bit, to generate a read-write completion identification; and step three, the verification platform end waits for the read-write completion identification in the target interaction space, and then jumps to step one.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of chip simulation, and in particular, to a chip simulation verification method and system. BACKGROUND

[0002] System on Chip (SOC) is also called System on a Chip. The definition of SOC is to integrate central processing unit (CPU), analog intellectual property (IP) core, digital IP core and memory into a single chip to form a system on chip. With the development of applications, the performance of SOC is getting stronger and stronger, and the scale is getting larger and larger, which greatly improves the complexity of SOC design. In SOC design, simulation and verification become the most complex and time-consuming part of the SOC design process.

[0003] Currently, there are mainly two kinds of system verification methods for SOC. One is to develop test excitation directly on the SOC, which requires higher verification personnel, and it is difficult to realize random excitation with constraints, so as to realize automatic comparison of data. The other is to replace the CPU in the SOC with a bus function model (BFM), which facilitates the development of test excitation with constraints for verification personnel. However, in the test excitation verification link of pre-simulation or post-simulation, due to the post-simulation of the netlist, the random test excitation of pre-simulation cannot be used, and the test excitation needs to be written again, which is a large amount of work. SUMMARY

[0004] Embodiments of the present application provide a simulation verification method and system for reducing the workload of chip simulation verification.

[0005] The first aspect of the embodiments of the present application provides a simulation verification method, comprising:

[0006] Predefining a part of the storage space of the system chip end as a target interaction space;

[0007] The function module includes a plurality of use cases, wherein one use case completes the excitation input by cyclically executing the following three steps:

[0008] Step one, the verification platform end assigns values to the target interaction space, and the target interaction space includes read-write identification bits, read-write addresses, read-write data and read-write completion identification bits;

[0009] Step two, the system chip end queries the read-write identification bits in the target interaction space, and according to the identification bits, completes the read-write operation in the system chip end to generate read-write completion identification;

[0010] Step three, the verification platform end waits for the read-write completion identifier in the target interaction space, and jumps to step one.

[0011] The embodiment of the application provides a simulation verification method, and the system chip end and the verification platform end perform corresponding read-write operations by assigning values to the interaction space, so that the simulation verification method of mutual coordination between the software of the system chip end and the verification platform end is realized.

[0012] The second aspect of the embodiment of the application provides a simulation verification method, comprising:

[0013] A part of the storage space of the system chip end is defined as a target interaction space in advance;

[0014] The function module comprises a plurality of use cases, and one use case completes the excitation input by cyclically executing the following three steps:

[0015] Step one, the verification platform end assigns values to the target interaction space, and the target interaction space comprises a read-write identifier bit, a read-write address, read-write data and a read-write completion identifier bit;

[0016] Step two, the system chip end queries the read-write identifier bit in the target interaction space, and completes read-write operations in the system chip end according to the identifier bit, to generate a read-write completion identifier;

[0017] Step three, the verification platform end waits for the read-write completion identifier in the target interaction space, and jumps to step one.

[0018] Optionally, the target interaction space comprises a first space, a second space, a third space and a fourth space; the first space is used for storing data read-write identifiers; the second space is used for storing read-write data addresses; the third space is used for storing read-write data; and the fourth space is used for storing read-write completion identifiers.

[0019] Optionally,

[0020] The step two comprises:

[0021] The system chip end queries the read-write identifier bit in the target interaction space;

[0022] If the read-write identifier bit is read, the system chip end acquires target data corresponding to the address bit according to the address bit in the second space, writes the target data into the third space, and sets the read completion identifier stored in the fourth space as completed;

[0023] Optionally,

[0024] The step two comprises:

[0025] The system chip end queries the read-write identification bit in the target interaction space;

[0026] If the read-write identification bit is write, the system chip end writes the data of the third space into the address corresponding to the second space, and sets the write completion identification stored in the fourth space as completed;

[0027] Optionally,

[0028] The step one comprises:

[0029] If for a use case, when the use case is pre-simulation, the verification platform end performs pre-simulation assignment on the target interaction space by designing an excitation program.

[0030] Optionally,

[0031] The step one further comprises:

[0032] If for the use case, when the use case is post-simulation, the path relationship between the pre-simulation and the post-simulation is found according to the target interaction space;

[0033] The verification platform end performs post-simulation assignment on the target interaction space according to the path relationship of the post-simulation; wherein the post-simulation assignment is the same as the pre-simulation assignment.

[0034] Optionally, when the excitation input of one use case of the functional module is completed, the method further comprises:

[0035] Step four: the verification platform end generates output data according to the use case;

[0036] The verification platform end collects the output data from the output interface of the functional module of the system chip end through an interface module.

[0037] Optionally, the method further comprises:

[0038] When performing excitation input on one use case, the verification platform end simultaneously performs the following steps:

[0039] The verification platform end designs a reference model for the functional module, and sends an excitation program of the same use case to the reference model of the functional module, so that the reference model calculates a reference result according to the excitation program.

[0040] Optionally, the method further comprises:

[0041] Step five: a comparator of the verification platform end receives the output data of the functional module collected by a collector of the verification platform end, and receives the reference result generated by the verification platform end;

[0042] The verification platform end compares the reference result with the output data, and outputs a comparison result to complete simulation verification of one use case of the function module.

[0043] Embodiments of the present application provide a simulation verification method. A verification platform end assigns each address in an interactive space of a system chip end, so that the system chip end performs corresponding read / write operations according to the assignment information of each address, so that the system chip end completes corresponding pre / post simulation. Then, the final simulation result of the system chip end is compared with the simulation result of the verification platform end, so that final simulation verification is realized.

[0044] Embodiments of the present application provide a simulation verification system, including:

[0045] A definition unit is configured to predefine a part of a storage space of a system chip end as a target interactive space.

[0046] An assignment unit is configured to assign the target interactive space, and the target interactive space includes a read / write identification bit, a read / write address, read / write data, and a read / write completion identification bit.

[0047] A query and execution unit is configured to query the read / write identification bit in the target interactive space, complete read / write operations in the system chip end according to the identification bit, and generate a read / write completion identification.

[0048] A jump unit is configured to jump to the assignment unit after waiting for the read / write completion identification in the target interactive space.

[0049] The simulation verification system provided in the third aspect of the embodiments of the present application is used to execute the method provided in the first aspect.

[0050] From the above technical solutions, it can be seen that the embodiments of the present application have the following advantages:

[0051] Embodiments of the present application provide a simulation verification method. By developing data read / write operation instructions on a verification platform, the system chip performs corresponding data read / write operations, so that the verification personnel only need to develop test stimuli on the verification platform, reducing the difficulty of developing test stimuli. At the same time, since the test stimuli do not need to consider whether the system chip is pre-simulated or post-simulated, the pre / post simulation of the netlist can share a set of test stimuli, reducing the workload of the verification personnel. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only represent some embodiments described in the present application, and other drawings can be obtained by those skilled in the art based on these drawings.

[0053] Figure 1 An architecture schematic diagram of the simulation verification disclosed by the embodiments of the present application;

[0054] Figure 2 An interaction schematic diagram of the simulation verification disclosed by the embodiments of the present application;

[0055] Figure 3 A flow schematic diagram of the simulation verification method disclosed by the embodiments of the present application;

[0056] Figure 4 A structure schematic diagram of the simulation verification system disclosed by the embodiments of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments only represent some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0058] SOC is also called system on chip (SOC). The definition of SOC is to integrate central processing unit (CPU), analog IP core, digital IP core and memory into a single chip to form a system on chip. With the development of applications, the performance of SOC is getting stronger and stronger, and the scale is getting larger and larger, which greatly improves the complexity of SOC design. In the SOC design, simulation and verification become the most complex and time-consuming part in the SOC design process.

[0059] Currently, there are two main methods for system verification of SOC. One is to develop test excitation directly in C language, which requires higher verification personnel and is difficult to realize random test excitation with constraints and automatic comparison of data. The other is to replace the CPU in SOC with BFM, which facilitates the verification personnel to develop test excitation with constraints by using System Verilog. However, when it comes to netlist verification simulation in the back end, since the entire design has been synthesized into a netlist by the back-end synthesis tool, the CPU cannot be replaced by the BFM model. Therefore, the C language test excitation needs to be developed for the netlist simulation in the back end. Thus, the random test excitation in the front simulation cannot be reused, and the C program needs to be written again, which is a large amount of work.

[0060] It can be understood that System Verilog combines concepts from Verilog, VHDL, C++, as well as verification platform languages and assertion languages, that is, it combines hardware description languages (HDL) with modern high-level verification languages (HVL). It is quite attractive to verification engineers who are engaged in the verification of today's highly complex designs.

[0061] It can also be understood that the BFM has actions that need to be triggered actively and actions that are passively accepted. The actively triggered actions are written as tasks, which are convenient to call in the test case.

[0062] In the embodiments of the present application, the constrained random stimulus mainly describes a program stimulus with constraints. It can also be understood that when writing a test stimulus in C language, multiple C-Code needs to be written due to the program characteristics of C language, that is, a corresponding C program needs to be written for each module, and it is troublesome to write multiple C languages. At the same time, the randomness under the same module is not good, and the automatic comparison of data results is not good. It can also be understood that when writing a stimulus in SV language, because C language cannot directly execute the data in the SV program, a virtual CPU needs to be written in SV language to simulate the BFM timing, so as to replace the CPU with BFM to call the data of SV. Such a method is good in randomness and easy to do automatic comparison, which is not difficult to understand, and is based on the characteristics of SV language, which belongs to a hardware description language. However, when simulating and verifying in the back end, the use case written in the front end verification using SV language cannot be used in the back end simulation because the back end simulation is aimed at netlist data and the position of the CPU cannot be found, so it is difficult to replace.

[0063] Therefore, the embodiments of the present application provide a simulation verification method and system, that is, the program developed by C language and the program developed by SV language share a part of storage space, and the SV language modifies the content of the shared storage space through the C language. Even when simulating and verifying in the back end, the shared storage space can be found out. The front end or back end verification is mainly realized by the C language program, but the stimulus data is written by the SV language. Therefore, the present application combines the advantages of C and SV languages, and a set of stimuli can be used in front-end and back-end verification, greatly reducing the programming workload.

[0064] Please refer to Figure 1 , Figure 1An architecture schematic diagram of simulation verification disclosed in the embodiment of the present application comprises a verification platform end 101 and a system chip end 102. The verification platform end 101 is connected with the system chip end 102.

[0065] The verification platform end 101 is a verification platform development framework taking a System Verilog library as a main body. Verification engineers can construct a functional verification environment with a standardized hierarchical structure and interface by using reusable components thereof. In other words, the verification platform end 101 is developed by using a universal verification methodology (UVM) and SV.

[0066] The verification platform end 101 can be constructed by using a verification platform development framework taking a System Verilog library as a main body. Figure 1 As can be seen, the verification platform end 101 further comprises a module interface 1011, a module collector 1012, a module reference model 1013 and a module comparator 1014.

[0067] The module interface 1011 is mainly used as a connection interface of the verification platform end 101 and the system chip end 102. The module interface 1011 is mainly used for a channel for transmitting and receiving data. It can be understood that the module interface 1011 can also have other functions, for example, when a simulation circuit is verified, a telecommunication signal or an analog signal can be converted into analog information or a telecommunication signal. However, finally, data or signals need to be transmitted and received through the module interface 1011.

[0068] The module collector 1012 is a system module responsible for collecting various data or signals output by the system chip end 102. In the embodiment, the collector 1012 is mainly responsible for collecting simulation data of pre-simulation or post-simulation output by the system chip end 102. After the collector 1012 collects the output result of the system chip end 102, the output result is transmitted to the module comparator 1014.

[0069] The module reference model 1013 is a system module for calculating a reference result according to an excitation program. It receives excitation data generated by the verification platform end 101, verifies the excitation data by using a language of a higher level than SV language, and obtains a final calculation result. It can be understood that the language environment used by the reference model 1013 is not limited in the embodiment. After the reference model calculates the result of the excitation data, the final reference result is transmitted to the module comparator 1014.

[0070] The comparator 1014 of each module is a system module for automatically comparing data. In the embodiment of the present application, the comparator 1014 automatically compares the reference result with the result of the actual design under test. Specifically, comparison of two or more data items to determine whether they are equal or to determine the size relationship and arrangement order between them is called comparison, and a circuit or device capable of performing such comparison is called a comparator. In the embodiment, the comparator 1014 compares the consistency of the two results, which generally includes data, timing, etc.

[0071] The system chip end 102 is a design under test SOC in the embodiment, which includes a central processing unit CPU 1021, a C-Code memory 1022, and a plurality of memories 1023. The memory 1023 is only one of the memories. In the embodiment, the memory 1023 is only a part of the storage space of the system chip end 102, which serves as an interaction space between the verification platform end 101 and the system chip end 102. It can be understood that each memory runs the program of a different module in the SOC, and the CPU 1021 controls the program running in each memory through the BUS bus. The C-Code 1022 is a program execution space in the embodiment of the present application, which is used to execute the corresponding C software code. For the convenience of understanding, the description of the C-Code 1022 hereinafter is described as a program execution space, which will not be described hereinafter.

[0072] The memory 1023 is a part of the storage space of the system chip end 102, which mainly includes four addresses, namely RW_FLG, RW_ADDR, RW_DATA, and RW_DONE. Each address performs a corresponding program action according to the corresponding program. The CPU 1021 always queries the running situation and result of the memory 1023. However, it should be noted that the memory 1023 cannot be used as the data and program space for the CPU 1021 to run software.

[0073] It should also be understood that the bus (Bus) is a common communication trunk for transmitting information between various functional components of a computer. It is a transmission line bundle composed of wires. According to the type of information transmitted by the computer, the bus of the computer can be divided into a data bus, an address bus, and a control bus, which are used to transmit data, data addresses, and control signals, respectively. The bus is an internal structure, which is a common channel for the CPU, memory, input, and output devices to transfer information. The components of the host are connected through the bus, and the external devices are connected to the bus through the corresponding interface circuit, thereby forming a computer hardware system. In a computer system, the common path for transmitting information between components is called a bus, and a microcomputer is connected to each functional component in a bus structure.

[0074] Therefore, it can be seen that the verification platform end 101 controls the memory 1023 in the system chip end 102 through the backdoor to control the system chip end 102.

[0075] Please refer to Figure 2 , Figure 2 An interaction schematic diagram of simulation verification disclosed by the embodiment of the application. The interaction schematic diagram mainly includes three modules. CPU, interaction space and SV / UVM verification platform.

[0076] Among them, the CPU and the interaction space are on the to-be-tested design SOC, that is, the system chip end described in the embodiment of the application, and the SV / UVM verification platform is the verification platform end described in the embodiment of the application.

[0077] The interaction space mainly includes four addresses, wherein address 1 is defined as a data read-write identifier (RW_FLG), address 2 is defined as a read-write data address (RW_ADDR), address 3 is defined as read-write data (RW_DATA), and address 4 is defined as a read-write completion identifier (RW_DONE). The CPU operates according to the corresponding addresses through the corresponding C software code. It should be noted that the data read-write identifier or the read-write completion identifier is the data read-write identifier or the read-write completion identifier described in the foregoing part. For the convenience of description, the identifier will be replaced by the identifier in the following, that is, the data read-write identifier or the read-write completion identifier is replaced by the data read-write identifier or the read-write completion identifier, and the following will not be described in detail.

[0078] The SV / UVM verification platform can directly operate the interaction space through the backdoor, encapsulate the operation into two read-write tasks by compiling the SV language, so that the addresses of the interaction space perform the corresponding read-write tasks.

[0079] Please refer to Figure 3 , Figure 3 A flowchart of a simulation verification method disclosed by the embodiment of the application. According to the simulation verification method disclosed by the embodiment of the application, the workload of the verification personnel can be effectively reduced, the verification platform and the test excitation are facilitated to maintain; the random excitation and the automatic comparison of the results are more convenient to realize; the random test excitation does not need to be developed by C language at all, which effectively reduces the requirement for verification; the netlist post-simulation and the pre-simulation can share a set of random test excitation, thereby reducing the repeated development work.

[0080] Specifically, steps 301-307 are included.

[0081] 301、Define a part of the storage space of the system chip end as a target interaction space.

[0082] Before the SOC is simulated and verified, that is, before the SOC software and hardware are cooperatively verified, the storage space of the CPU needs to be defined first, because the CPU needs to run programs and process data, and the storage space needs to be used at the same time. The C software code runs on the CPU, but the C language program cannot run the SV language, therefore, a part of the storage space on the CPU needs to be defined so that the SV language can run on the SOC. It should be noted that in the embodiment, the system chip end is the SOC, and the SOC is described for the convenience of description, and the SOC will not be described again hereinafter.

[0083] Specifically, a part of the storage space of the CPU is defined as a software and hardware interaction space, and it should be noted that this space cannot be used as the data and program space of the software running on the CPU. Among them, the SOC defines address 1 as a data read-write flag (RW_FLG), address 2 as a read-write data address (RW_ADDR), address 3 as read-write data (RW_DATA), and address 4 as a read-write completion flag (RW_DONE). Specifically, the data read-write flag includes a data read flag and a data write flag; the read-write data address includes a read data address and a write data address; the read-write data includes read data and write data; and the read-write completion flag includes a read completion flag and a write completion flag.

[0084] After the storage space of the CPU is defined, the corresponding C software code needs to be compiled. Specifically, the specific steps of the C software code to be executed are as follows:

[0085] The CPU always queries the data read-write flag of address 1, and when the data read-write flag of address 1 is a read flag, the data read from the read data address of address 2 is stored on address 3, and then the read completion flag of address 4 is set to 1. This step is the step of reading the program, that is, the read operation.

[0086] If the data read-write flag on address 1 is a write flag, the data to be written on address 3 is written to the address corresponding to address 2, and then the write completion flag is set to 1. This step is the step of writing the program, that is, the write operation.

[0087] It is not difficult to understand that the data read-write flag needs to be defined by oneself, for example, 'h55 can be defined as a read flag and 'haa can be defined as a write flag. As long as one can distinguish the read and write flags, it is OK.

[0088] It can also be understood that the "1" in the read completion flag 1 or the write completion flag 1 means that the corresponding read-write operation is completed, and the corresponding read-write program is completed. For the convenience of description, the meaning of "1" will not be described hereinafter.

[0089] When the C software code running in the interactive space is compiled, the compiled tool is used to compile a bin file, and then the bin file is converted into a hex file. The hex file is loaded into the CPU execution program space through the backdoor at the verification platform end, so that the CPU performs the corresponding read-write operation in the interactive space according to the program.

[0090] It can be understood that the hex file format is a file format that can be burned into a single-chip microcomputer and executed by the single-chip microcomputer. There are many ways to generate a hex file, and a C program or an assembly program can be compiled into a hex file through different compilers. In the embodiment, the hex file is generated by a C program through a compiling tool (such as keil).

[0091] It can also be understood that loading the hex file into the CPU execution program space through the backdoor at the verification platform end is to import the hex file into the memory storage space. Here, the backdoor refers to importing the file into the memory storage space, that is, the execution program space, through the $readmemh system function.

[0092] 302. The verification platform end assigns values to the target interactive space.

[0093] The verification platform end assigns values to the target interactive space, and the target interactive space includes read-write identification bits, read-write addresses, read-write data, and read-write completion identification bits.

[0094] Specifically, at the verification platform end, the software and hardware interactive space can be directly operated through the backdoor, that is, the operation mode is encapsulated into two read-write tasks. In other words, the memory storage space is directly operated by using the SV program, that is, the memory is directly assigned values at a specific address, and the read-write tasks are encapsulated.

[0095] It should be understood that if a specific test stimulus is compiled in the SV program as a pre-simulation test stimulus, the verification platform end performs pre-simulation assignment to the interactive space by designing a stimulus program. If a specific test stimulus is compiled in the SV program as a post-simulation test stimulus, the system chip end finds the pre-simulation and post-simulation path relationship according to the interactive space, wherein in the embodiment, the path relationship is the value of address 2. Then, the verification platform end performs post-simulation assignment to the interactive space according to the path relationship; in the embodiment, the post-simulation assignment and the pre-simulation assignment can be the same. It should also be understood that the post-simulation assignment and the pre-simulation assignment can also be different, but the embodiment can perform simulation verification through the same assignment.

[0096] Since in the embodiment, the assignments of the pre-simulation and the post-simulation are the same, only the corresponding programs are different, thus in the embodiment, the verification platform end assigns the target interactive space, specifically, one embodiment is as follows:

[0097] When it is a read task, for the address addr, reading data: first, assign the address of the read-write data of the address 2 as addr, and then assign the data read-write identifier of the address 1 as 0x55 (read identifier), which is the read task.

[0098] When it is a write task, for the address addr, writing data data: first, assign the address of the read-write data of the address 2 as addr, and then assign the data read-write identifier of the address 3 as data, and then assign the data read-write identifier of the address 1 as 0xAA (write identifier), which is the write task.

[0099] It can be understood that the assignments of the address 1, the address 2, and the address 3 can also be other values, and the specific values described in the embodiment are only one specific embodiment, and it also needs to be understood that the assignment steps corresponding to the address 1 or the address 2 or the address 3 can not be in sequence, for example, for the write task, the address 1 can be assigned first, then the address 2, and finally the address 3; or the address 2 can be assigned first, then the address 1, and finally the address 3. For the convenience of description, the sequence of the assignment steps will not be described in detail hereinafter.

[0100] After the address of the interactive space is assigned, the CPU will obtain the data corresponding to the address, and then write the data corresponding to the address into the execution program space through the BUS bus, so that the execution program space simulates according to the data corresponding to the address. For the convenience of description, this will not be described hereinafter, but it needs to be pointed out that the data of the interactive space address and the data of the execution program space address correspond to each other, that is, the data written into the interactive space will also be obtained by the execution program space, but the data will be simulated in the execution program space, and finally the simulation result will be transmitted to the interactive space by the CPU, so that the interactive space also obtains the simulation result.

[0101] 303、The system chip end queries the read-write identifier bit in the target interactive space, and completes the read-write operation in the system chip end according to the identifier bit to generate a read-write completion identifier.

[0102] The CPU in the system chip end is always querying the data read-write identifier of the address 1 in the interactive space, and completes the read-write operation in the system chip end according to the identifier bit to generate a read-write completion identifier.

[0103] Specifically, when the data read-write identifier of the address is assigned as a read identifier, the CPU reads the data at the address 2, stores the read data at the address 3, and sets the read completion identifier of the address 4 to 1. It should be noted that according to step 302, the address 1 and the address 2 have been assigned by the verification platform.

[0104] When the data read-write identifier of the address is assigned as a write identifier, the CPU writes the data to be written at the address 3 to the address corresponding to the write data of the address 2, and then sets the write completion identifier to 1. It should be noted that according to step 302, the address 1, the address 2, and the address 3 have been assigned by the verification platform.

[0105] It should be understood that when the read completion identifier or the write completion identifier is set to "1", it means that the read operation or the write operation is completed.

[0106] Correspondingly, when the write step is performed, since the interactive space does not run the program, after the verification platform assigns values to the address 1, the address 2, and the address 3, the execution program space obtains the values of the address 1, the address 2, and the address 3, and then runs the corresponding program step according to the corresponding program instruction, that is, the write program step described in step 301.

[0107] When the read step is performed, since the interactive space does not run the program, after the verification platform assigns values to the address 1 and the address 2, the execution program space obtains the values of the address 1 and the address 2, and then runs the corresponding program step according to the corresponding program instruction, that is, the read program step described in step 301.

[0108] 304, the verification platform waits for the read-write completion identifier in the target interactive space. If it is a loop, step 302 is performed; or, step 305 is performed.

[0109] The verification platform queries the read-write completion identifier in the interactive space through the backdoor, and if there is still an incentive input, step 302 can be continued, or step 305 can be performed. In this embodiment, the incentive input can be understood as the assignment of the verification platform to the interactive space.

[0110] The verification platform queries the read-write completion identifier in the interactive space through the backdoor all the time. Specifically, when the verification platform queries that the read completion identifier in the interactive space is completed, the read data stored at the address 3 is obtained. If the verification platform still inputs the incentive to the interactive space, step 302 can be performed, and if the verification platform no longer inputs the incentive to the interactive space, step 305 is performed.

[0111] When the verification platform end queries the write completion identifier in the interaction space and finds that the write completion identifier has been completed, if the verification platform end still inputs the excitation to the interaction space, step 302 is executed, and if the verification platform end no longer inputs the excitation to the interaction space, step 305 is executed.

[0112] Because the CPU is always in a loop to query the read-write identifier, when the read-write identifier is queried, the CPU completes the corresponding read-write operation.

[0113] 305、The system chip end generates output data according to the use case, and the verification platform end collects the output data from the output interface of the functional module of the system chip end through the interface module.

[0114] In step 302, after the write task is performed, because the address 1, the address 2 and the address 3 have been assigned by the verification platform end, when the CPU queries the read-write identifier bit of the interaction space and finds that the read-write identifier bit is a write identifier, the CPU translates the operation into a write operation, writes the corresponding operation instruction to the BUS bus, and then the BUS bus writes the corresponding operation instruction and the assignment of the corresponding address to the execution program space, so that the execution program space performs simulation verification, thereby generating a simulation result.

[0115] Correspondingly, in step 302, after the read task is performed, because the address 1 and the address 2 have been assigned by the verification platform end, when the CPU queries the read-write identifier bit of the interaction space and finds that the read-write identifier bit is a read identifier, the CPU translates the operation into a read operation, writes the corresponding operation instruction to the BUS bus, and then the BUS bus writes the corresponding operation instruction and the assignment of the corresponding address to the corresponding register of the system chip end, and after the completion, writes the read data to the address 3 of the interaction space.

[0116] Therefore, the verification platform end can read the data on the address 3, and specifically, the use case in this embodiment can be understood as an excitation input data.

[0117] Specifically, the verification platform end collects the output data, i.e. the simulation result data, from the functional module of the system chip end through the interface module.

[0118] It can be understood that, at the verification platform end, the read-write task encapsulated in step 302 can be directly called by using System Verilog, so that it is convenient for the verification personnel to develop a random constraint excitation. The random excitation with constraints can operate the software and hardware interaction storage space in the SOC through the read-write task. The CPU is always polling the read-write identifier in the software and hardware interaction storage space, and converts the corresponding read-write operation of the random excitation into a CPU sent to the BUS bus, so as to realize the real software operation through the backdoor operation. Some modules in the SOC also need to input data from the interface, so the test excitation can also send excitation data to the SOC module to be tested through the interface module. The embodiment does not limit the way in which the SOC receives the excitation data, and will not be described again hereinafter.

[0119] It also needs to be understood that, in the embodiment, the random constraint excitation is a random variable with constraints.

[0120] 307、The verification platform end designs a reference model for a functional module, and sends an excitation program of the same use case to the reference model, so that the reference model calculates a reference result according to the excitation program.

[0121] The verification platform end designs a reference model for a functional module, and sends an excitation program of the same use case to the reference model, so that the reference model calculates a reference result according to the excitation program. It needs to be understood that the running language of the reference model is a higher-level language compared with the SV language, so the excitation program can be simulated and verified accordingly.

[0122] Correspondingly, after designing the excitation program at the verification platform end, the excitation program is also output to the interaction space in the system chip end through the backdoor. Specifically, the output mode mainly encapsulates the read-write task into two read-write tasks, so as to assign the corresponding address of the interaction space. When the system chip end queries the corresponding read-write identifier, the read-write operation is performed, so that the system chip end outputs the simulation result after simulation according to the excitation program to the comparator at the verification platform end.

[0123] It is not difficult to understand that step 307 mainly includes two actions, one is to output the excitation program to the interaction space on the system chip end, that is, step 307 can be performed after step 301; the other is to output the reference result to the comparator at the verification platform end for comparison, that is, step 307 only needs to be performed before step 306. However, it needs to be explained that, because steps 302-304 are looped, step 307 can not have a sequence relationship with steps 302-304. Step 307 can be executed first, and then steps 302-304 can be executed, or steps 302-304 can be continued simultaneously. The sequence of the steps is not limited here.

[0124] 306, the verification platform compares the reference result with the output data, and outputs a comparison result.

[0125] When the reference model calculates the reference result, the reference result is sent to the comparator. Meanwhile, each module collects the calculation result of the design SOC to be tested through the respective port, and sends the result to the comparator. The comparator automatically compares the reference result with the result of the design to be tested. In this way, the same set of C software code can be used for pre-netlist simulation and post-netlist simulation. Moreover, because the development and verification of the stimulus are based on System Verilog, the verification platform and the constraint-based random stimulus can be reused in post-simulation, which greatly reduces the workload of verification and facilitates the maintenance in the later stage.

[0126] It should be understood that, although each step in the flowchart involved in each embodiment as described above is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0127] If the scheme involves sensitive information (such as user information, enterprise information), it should be explained that the collection, use and processing of sensitive information need to comply with relevant national and regional laws, regulations and standards, and need to be carried out with the permission or consent of the corresponding subject (such as users or enterprises, etc.).

[0128] As can be seen, through the simulation verification method proposed in this embodiment, the post-netlist simulation and the pre-netlist simulation share a set of random test stimulus and test platform, greatly reducing the verification workload; the verification personnel do not need to develop C program stimulus alone, but only need to develop constraint-based random stimulus and data automatic comparison, which can fully utilize the random test stimulus to make the verification converge faster. Through a large number of constraint-based random stimulus, the verification is more sufficient and complete. Compared with simply writing C program test stimulus, this method converts the operation of hardware into CPU software operation, which can realize more flexible random stimulus using System Verilog verification language, and also facilitates the automatic comparison of data.

[0129] The simulation verification method in the embodiment of the present application is described above, and the structure of a simulation verification system in the embodiment of the present application is described below. Please refer to Figure 4 The structure of a simulation verification system comprises:

[0130] A definition unit 401 is configured to define a part of storage space at a system chip end as a target interaction space in advance.

[0131] An assignment unit 402 is configured to assign the target interaction space, and the target interaction space comprises a read-write identification bit, a read-write address, read-write data and a read-write completion identification bit.

[0132] A query and execution unit 403 is configured to query the read-write identification bit in the target interaction space, complete a read-write operation at the system chip end according to the identification bit, and generate a read-write completion identification.

[0133] A jump unit 404 is configured to jump to the assignment unit after waiting for the read-write completion identification in the target interaction space.

[0134] The embodiment provides a simulation verification system, each address in the interaction space is assigned, so that the system executes corresponding read-write operations according to the assignment information of each address, and the system completes corresponding pre-simulation and post-simulation. Then the system performs data comparison on the final simulation result, so as to realize final simulation verification.

[0135] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0136] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0137] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0138] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically independently, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0139] When the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a magnetic disk or an optical disk, and various media that can store program codes.

Claims

1. A method of simulation verification, the method comprising: The method comprises: Predefining a part of the storage space of the system chip end as a target interaction space; The functional module comprises a plurality of use cases, and one use case completes the excitation input by cyclically executing the following three steps: Step one, verifying that the platform end assigns values to the target interaction space, which includes read-write identification bits, read-write addresses, read-write data, and read-write completion identification bits; Step two, the system chip end queries the read-write identification bits in the target interaction space, and according to the identification bits, completes the read-write operation at the system chip end to generate read-write completion identification; Step three, the verification platform end waits for the read-write completion identification in the target interaction space, and then jumps to step one; The target interaction space includes a first space, a second space, a third space, and a fourth space; the first space is used to store data read-write identification; the second space is used to store read-write data addresses, the third space is used to store read-write data, and the fourth space is used to store read-write completion identification; The step one comprises: If for a use case, when the use case is pre-simulation, the verification platform end assigns values to the target interaction space by designing an excitation program; The step one further comprises: If for the use case, when the use case is post-simulation, find the path relationship between the pre-simulation and the post-simulation according to the target interaction space; the path relationship is the value of the storage read-write data address; The verification platform end assigns values to the target interaction space according to the path relationship of the post-simulation; wherein the post-simulation assignment and the pre-simulation assignment are the same.

2. The method of claim 1, wherein The step two comprises: The system chip end queries the read-write identification bits in the target interaction space; If the read-write identification bit is read, the system chip end acquires the target data corresponding to the address bit according to the address bit in the second space, writes the target data into the third space, and sets the read completion identification stored in the fourth space as completed.

3. The method of claim 1, wherein The step two comprises: The system chip end queries the read-write identification bits in the target interaction space; If the read-write identification bit is write, the system chip end writes the data of the third space into the address corresponding to the second space, and sets the write completion identification stored in the fourth space as completed.

4. The method of claim 1, wherein, When the excitation input of one use case of the functional module is completed, the method further comprises: Step four: the system chip end generates output data according to the use case; The verification platform end collects the output data from the output interface of the functional module of the system chip end through an interface module.

5. The method of claim 4, wherein, The method further comprises: When performing excitation input on one use case, the verification platform end simultaneously executes the following steps: The verification platform end designs a reference model for the functional module, and sends the excitation program of the same use case to the reference model of the functional module, so that the reference model calculates a reference result according to the excitation program.

6. The method of claim 4, wherein, The method further comprises: Step five: the comparator of the verification platform end receives the output data of the functional module collected by the collector of the verification platform end, and receives the reference result generated by the verification platform end; The verification platform end compares the reference result with the output data, and outputs the comparison result, so as to complete the simulation verification of one use case of the functional module.

7. An emulation verification system, comprising: The system comprises: A definition unit is configured to predefine a part of storage space of a system chip end as a target interaction space; An assignment unit is configured to assign the target interaction space, which includes read-write identification bits, read-write addresses, read-write data, and read-write completion identification bits; A query and execution unit is configured to query the read-write identification bits in the target interaction space, complete read-write operations on the system chip end according to the identification bits, and generate read-write completion identification; A jump unit is configured to wait for the read-write completion identification in the target interaction space, and then jump to the assignment unit; The target interaction space includes a first space, a second space, a third space, and a fourth space; the first space is configured to store data read-write identification; the second space is configured to store read-write data addresses; the third space is configured to store read-write data; and the fourth space is configured to store read-write completion identification; The assignment unit is further configured to, for one use case, when the use case is pre-simulation, assign the target interaction space by a verification platform end through a designed excitation program. The assignment unit is further configured to, for the use case, when the use case is post-simulation, find the path relationship between the pre-simulation and the post-simulation according to the target interaction space. The verification platform end assigns the target interaction space according to the path relationship of the post-simulation; wherein the post-simulation assignment is the same as the pre-simulation assignment.

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