Dynamic Information Processing Unit Based on Neural Network

Abstract

A dynamic information processing unit based on a neural network, the dynamic information processing unit includes a switch element and a dynamic memristor, wherein the dynamic memristor is electrically connected to the switch element, and the output signal of the switch element includes a timing dynamic signal introduced by the dynamic memristor. The dynamic information processing unit has logic information processing capabilities and timing information processing capabilities, and can process complex spatiotemporal information; and the dynamic information processing unit has the advantages of simple circuit structure, low power consumption, strong architecture scalability, and easy compatibility with standard CMOS processes.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a dynamic information processing unit based on a neural network. Background Art

[0002] With the rapid development of information technology, people hope that information processing systems will have faster computing speeds and lower operating energy consumption. However, the storage unit and computing unit of the traditional von Neumann information processing system are separated, and the large amount of data movement between the storage unit and the computing unit makes it difficult for the von Neumann information processing system to break through the shackles of the "storage wall".

[0003] In biological neural networks, computing units and storage units are fused. Due to the participation of abundant ions and protein molecules, biological neural networks have complex electrochemical dynamic processes inside, and there are also a large number of neurons and synapses in biological neural networks. The dynamic information processing mechanism of neurons and synapses gives biological neural networks very powerful parallel information processing capabilities.

[0004] The computing architecture based on integrated storage and computing simulates the information processing method of biological neural networks and is considered to be one of the most effective ways to break the limitation of the "storage wall". At present, the basic information processing unit of the integrated storage and computing computing architecture is the transistor. Although the information processing system based on transistors has good logical operation advantages, it lacks spatiotemporal information processing capabilities. Therefore, in order to realize the spatiotemporal information processing function, a complex hardware architecture is often required, which leads to huge power consumption of the system, which is difficult to compare with biological neural networks. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a dynamic information processing unit, including a switch element and a dynamic memristor, wherein the dynamic memristor is electrically connected to the switch element, and an output signal of the switch element includes a timing dynamic signal introduced by the dynamic memristor.

[0006] For example, in the dynamic information processing unit provided in at least one embodiment of the present disclosure, the dynamic memristor includes a first electrode layer, a dielectric layer, and a second electrode layer.

[0007] For example, in the dynamic information processing unit provided in at least one embodiment of the present disclosure, the switching element includes a transistor, and the switching element includes a source, a drain, and a gate.

[0008] For example, in the dynamic information processing unit provided in at least one embodiment of the present disclosure, the first end of the dynamic memristor is connected to the first voltage end, and the second end of the dynamic memristor is electrically connected to the source or the drain of the switching element.

[0009] For example, in the dynamic information processing unit provided in at least one embodiment of the present disclosure, the first end of the dynamic memristor is connected to the first voltage end, and the second end of the dynamic memristor is electrically connected to the gate of the switching element.

[0010] For example, the dynamic information processing unit provided by at least one embodiment of the present disclosure also includes a first resistor, wherein the first resistor is connected in series with the dynamic memristor, the first end of the first resistor is electrically connected to the switching element, and the first end of the first resistor is also connected or not connected to the dynamic memristor.

[0011] For example, the dynamic information processing unit provided by at least one embodiment of the present disclosure further includes a first memristor, wherein a first end of the first memristor is electrically connected to the switch element.

[0012] For example, in the dynamic information processing unit provided in at least one embodiment of the present disclosure, the first memristor and the dynamic memristor are connected in series with each other and connected as a whole to one connection end of the switching element; or the first memristor and the dynamic memristor are respectively connected to different connection ends of the switching element.

[0013] For example, in the dynamic information processing unit provided in at least one embodiment of the present disclosure, the first memristor includes a non-volatile resistive switching device.

[0014] At least one embodiment of the present disclosure further provides a memristor array, comprising the dynamic information processing unit described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0016] Figure 1A is a schematic diagram of a biological neuron unit;

[0017] Figure 1B A schematic diagram of a neuron's information processing model;

[0018] Figure 2A A schematic diagram of the structure of a dynamic memristor provided in one embodiment of the present disclosure;

[0019] Figure 2B A schematic diagram of the structure of another dynamic memristor provided by an embodiment of the present disclosure;

[0020] Figure 3A A schematic diagram of a voltage-current curve of a dynamic memristor provided in an embodiment of the present disclosure;

[0021] Figure 3B A schematic diagram of a memory characteristic curve of a dynamic memristor provided in an embodiment of the present disclosure;

[0022] Figure 3C A schematic diagram of the output current of a dynamic memristor under voltage pulses of different amplitudes provided by an embodiment of the present disclosure;

[0023] Figure 3D A schematic diagram of an output current-voltage pulse amplitude curve of a dynamic memristor provided in an embodiment of the present disclosure;

[0024] Figure 3E A schematic diagram of the output current of a dynamic memristor under different voltage pulse widths provided by an embodiment of the present disclosure;

[0025] Figure 3F A schematic diagram of an output current-voltage pulse width curve of a dynamic memristor provided in an embodiment of the present disclosure;

[0026] Figure 3G A schematic diagram of the output current of a dynamic memristor at different voltage pulse intervals provided by an embodiment of the present disclosure;

[0027] Figure 3H A schematic diagram of an output current-voltage pulse interval curve of a dynamic memristor provided in an embodiment of the present disclosure;

[0028] Figure 4A A structural diagram of a dynamic information processing unit provided in one embodiment of the present disclosure;

[0029] Figure 4B A schematic diagram of the structure of another dynamic information processing unit provided by an embodiment of the present disclosure;

[0030] Figure 4C A structural diagram of another dynamic information processing unit provided in an embodiment of the present disclosure;

[0031] Figure 5 A structural diagram of another dynamic information processing unit provided in an embodiment of the present disclosure;

[0032] Fig. 6A A schematic diagram of the structure of a dynamic information processing unit with a 1TIR structure provided in one embodiment of the present disclosure;

[0033] Figure 6B A structural schematic diagram of another 1TIR structure dynamic information processing unit provided by an embodiment of the present disclosure;

[0034] Figure 6C A structural schematic diagram of a dynamic information processing unit of another 1TIR structure provided in an embodiment of the present disclosure;

[0035] Fig.6D A schematic diagram of the structure of a dynamic information processing unit with a 2T2R structure provided in one embodiment of the present disclosure;

[0036] Fig. 7A A schematic diagram of a memristor array provided in accordance with an embodiment of the present disclosure; and

[0037] Figure 7B A schematic diagram of another memristor array provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of well-known functions and well-known components may be omitted.

[0041] The brain of an organism mainly relies on neurons and synapses that transmit information between neurons to achieve information transmission and processing. Neurons are the basic units of the brain's nervous system for processing information. They can be used to receive, integrate, filter, store and transmit information, so that various functional activities of a person can be carried out regularly to adapt to changes in the internal and external environment. In addition, biological neural networks also have abundant protein molecules and ions such as calcium, sodium, potassium, magnesium and chlorine. The electrochemical dynamic processes of these abundant ions between neurons give biological neural networks powerful information processing capabilities. Parallel processing architecture and rich microscopic internal dynamic processes are one of the key factors that enable biological neural networks to process extremely complex spatiotemporal information with extremely low energy consumption.

[0042] Figure 1A shows a biological neuron unit, Figure 1B Shown is a neuron's information processing model.

[0043] Neurons are the basic components of neural networks, which can transmit, filter and integrate information. Figure 1A As shown, in a neuron, a signal transmitted by a neuron passes through the axon and first reaches the axon terminal, causing the vesicles in the axon terminal to change and release neurotransmitters. The neurotransmitters enter the dendrites of another neuron through the synaptic gap. The receptors on the dendrites can accept neurotransmitters to change the permeability of the cell body's membrane to ions, causing the concentration of ions inside and outside the cell membrane to change, and then causing the potential inside and outside the cell body to change. Thus, information is transmitted from one neuron to another neuron. In the process of information transmission, some axons can form multiple branches at the axon terminal, and the potential action from the main branch of the axon can continue to be transmitted on each branch at the same time, and finally reach different target neurons, so that the axon can achieve communication between multiple neurons. On the other hand, in the neural network structure, the branches of the axon terminals of different neurons can reach the dendrites of the same neuron and form a large number of synapses. The neurotransmitters released by synapses from different sources can all have an effect on the changes in the membrane potential of the cell body of the same neuron. Thus, neurons can integrate input information from different sources. On the other hand, in neurons, the release of neurotransmitters in synapses and the changes in the membrane potential of the cell body are continuous. When the membrane potential is higher than a certain threshold, the input information is transmitted by the axon; when the membrane potential is lower than the threshold, the input information cannot be transmitted. Thus, neurons realize the function of filtering information.

[0044] A neuron is an information processing unit with multiple inputs and a single output. Its information processing is nonlinear. According to the functions and characteristics of neurons, it can be abstracted into a simple mathematical model. Figure 1B As shown, x0, x1, x2, ..., x nis the signal transmitted by the axons of the previous neurons, w0, w1, w2, ..., w n is the transmission efficiency of synapse 01, x0, x1, x2, …, x n After synapse 01, the neuron input signals P0, P1, P2, ..., P n , the input signal enters the dendrite 02; then, the dendrite 02 and the cell body 03 process the input signal and obtain the output signal Y, which is finally transmitted to the axon 04, and the axon 04 can continue to transmit the output signal Y to other neurons.

[0045] When a neuron receives information from other neurons, the dendrite 02 has the function of a threshold function, which can be expressed as the following formula:

[0046]

[0047] When the value of the input signal is greater than the threshold value θ, the value of the channel is 1, so the voltage-gated ion channel in the dendrite 02 is opened, and the input signal can be transmitted to the cell body 03; when the value of the input signal is less than the threshold value θ, the value of the channel is 0, so the voltage-gated ion channel in the dendrite 02 is closed, and the input signal is attenuated during the transmission process of the dendrite 02, and thus cannot be transmitted to the cell body 03. After the cell body 03 receives the input signal transmitted from the dendrite 02, its membrane potential changes gradually and continuously over time. When the change in membrane potential exceeds a certain threshold, the cell body 03 generates a sudden rise pulse signal, which is the output signal of the neuron. Then, this pulse signal is transmitted along the axon to other neurons, thereby completing the information transmission of the neuron.

[0048] In the process of information transmission between neurons, synapses play a vital role. In particular, the synaptic plasticity of neurons is considered to be the key to brain learning and memory. Synaptic plasticity refers to the phenomenon that the connection strength between synapses can be adjusted and changed. This change in connection strength can be divided into short-term synaptic plasticity and long-term synaptic plasticity according to the maintenance time. If the maintenance time is from milliseconds to minutes, it is called short-term synaptic plasticity. If the maintenance time is from hours to days, it is called long-term synaptic plasticity. The main manifestations of long-term synaptic plasticity are long-term potentiation and long-term depression. Figure 1B In the information processing unit shown in the figure, the enhancement or inhibition of synaptic plasticity can be measured by the synaptic transmission efficiency w0, w1, w2, ..., w n It is used to indicate an increase or decrease in .

[0049] Inspired by biological neural networks, the integrated computing architecture integrates computing units and storage units, thereby increasing the speed of information processing and reducing the power consumption of information processing. At present, the basic information processing unit of the integrated computing architecture is still the transistor. The transistor can control the conductive channel of electrons or holes between the source and the drain by the voltage applied to the gate, thereby realizing the opening and closing of the circuit. The transistor can also encode the input signal as "0" and "1". This is because there is a channel between the source and the drain of the transistor. When no voltage is applied to the gate of the transistor, effective charges cannot be accumulated in the channel, and the source and the drain are not conductive. At this time, the transistor is in the off state, which can be represented as "0"; when a voltage is applied to the gate of the transistor, a large amount of charge is accumulated in the channel, so that a conductive channel is formed between the source and the drain. At this time, the transistor is in the on state, which can be represented as "1". Therefore, the information processing system based on transistors has great advantages in processing deterministic logical operations. Integrated circuits based on transistors have become the cornerstone of all current information processing systems.

[0050] However, transistor-based information processing units often require very complex circuit structures when simulating biological neural networks to realize complex spatiotemporal information processing. Because the physical basis of transistor operation is the opening and closing of electronic channels, it is difficult to realize the function of efficient processing of complex spatiotemporal information by basic units in biological neural networks by relying solely on a single transistor or a combination of a limited number of transistors. Existing neural network acceleration chips based on silicon-based transistors usually have very complex hardware architectures, which makes them consume huge power and difficult to compete with biological neural networks.

[0051] Therefore, if you want to realize a computing system with low power consumption and complex information processing functions, you need to introduce new devices with timing information processing functions into the existing basic information processing units. Dynamic memristors are a new type of information processing device with rich dynamic electrical characteristics. Unlike ordinary memristors, dynamic memristors can achieve the function of complex timing signal processing by regulating the dynamic changes of microscopic ions inside them through electric fields. Introducing dynamic memristors into basic information units can effectively combine the logical information processing capabilities of transistors and the timing information processing capabilities of dynamic memristors, enhance the basic unit's processing capabilities for complex spatiotemporal information, thereby simplifying the system architecture and reducing system power consumption.

[0052] At least one embodiment of the present disclosure provides a dynamic information processing unit. The dynamic information processing unit includes: a switch element and a dynamic memristor, wherein the dynamic memristor is electrically connected to the switch element, and the output signal of the switch element includes a timing dynamic signal introduced by the dynamic memristor. The dynamic information processing unit can simulate the learning and memory functions of synapses in neurons.

[0053] Figure 2A A schematic diagram of the structure of a dynamic memristor provided for at least one embodiment of the present disclosure. For example, the dynamic memristor 100 provided for one embodiment of the present disclosure includes a stacked first electrode layer 110, a first dielectric layer 120, and a second electrode layer 130, wherein the first dielectric layer 120 is disposed between the first electrode layer 110 and the second electrode layer 130.

[0054] For example, the materials of the first electrode layer 110 and the second electrode layer 130 are both conductive materials, such as metal materials or non-metallic conductive materials. Metallic materials may be, for example, aluminum (Al), nickel (Ni), titanium (Ti), copper (Cu), aluminum (Al) or tungsten (W), and metal composite materials. Non-metallic conductive materials may be, for example, polymer conductive materials, semiconductor conductive materials, composite conductive materials, thin film conductive materials, or other conductive materials that can act as electrodes, such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO), polysilicon, and the like.

[0055] For example, the materials of the first electrode layer 110 and the second electrode layer 130 may be the same or different. It is worth mentioning that when the materials of the first electrode layer 110 and the second electrode layer 130 are different, the resistance of the dynamic memristor has a good slow change characteristic under an applied voltage.

[0056] For example, the material of the first dielectric layer 120 may be a material having ion migration capability, and the resistance value of the dynamic memristor changes with the dynamic migration process of ions in the first dielectric layer 120 , such as a material capable of realizing internal migration of oxygen ions.

[0057] For example, the material of the first dielectric layer 120 may be a transition metal oxide, such as titanium oxide (TiOx), etc. For example, the material of the first dielectric layer 120 may also be an organic substance having ion migration capability or a thin film material having an electrolyte function, etc.

[0058] Another dynamic memristor provided by at least one embodiment of the present disclosure further includes a second dielectric layer. Figure 2B As shown, the dynamic memristor 200 includes a stacked first electrode layer 210, a first dielectric layer 220, a second dielectric layer 230, and a second electrode layer 240. The structure and material composition of the other layers except the second dielectric layer 230 are similar to those of FIG. Figure 2A The description is consistent with that in , and will not be repeated here.

[0059] For example, the first dielectric layer 220 and the second dielectric layer 230 are disposed between the first electrode layer 210 and the second electrode layer 240 . The second dielectric layer 230 serves as an ion reserve pool of the first dielectric layer 220 , providing a buffer storage area for ion migration in the first dielectric layer 220 .

[0060] For example, the material of the second dielectric layer 230 can be any material that can accommodate ions. For example, the second dielectric layer 230 can be the same material as the first electrode layer 210 or the second electrode layer 240. For example, the material of the second dielectric layer 230 can also be a transition metal oxide of the same quality as the first dielectric layer 220.

[0061] The dynamic memristor provided by at least one embodiment of the present disclosure has a simple sandwich structure, which is conducive to being integrated at the port of a switching element such as a transistor in a series manner. In addition, the preparation method of the dynamic memristor is simple and compatible with the back-end CMOS preparation process, and it is easy to prepare the dynamic memristor at the port of a transistor.

[0062] Figure 3A-3H Several electrical characteristic curves of a dynamic memristor are shown, and the figures respectively show the variation curves of the output current when the dynamic memristor responds to different voltage signals. The embodiments of the present disclosure are not limited to the electrical characteristic curves shown.

[0063] like Figure 3A As shown, when a voltage signal that changes linearly from 0V to 4V relative to time (in milliseconds (ms)) is applied to both ends of the dynamic memristor, the current of the dynamic memristor exhibits a nonlinear response. For example, when the applied voltage signal is less than the response threshold voltage of the dynamic memristor, the current response of the dynamic memristor is almost 0, that is, the input signal below the threshold voltage of the dynamic memristor can be filtered out, and the dynamic memristor is in the "OFF" state. For example, when the applied voltage signal is greater than the threshold voltage of the dynamic memristor, the current of the dynamic memristor increases sharply with the linear application of the voltage signal, that is, the input signal higher than the threshold voltage of the dynamic memristor can cause the current of the dynamic memristor to accumulate nonlinearly, and the dynamic memristor is in the "ON" state. For example, in an embodiment of the present disclosure, as Figure 3A As shown, the threshold voltage of the dynamic memristor is about 2V. After applying a linear voltage signal from 0V to 4V, the output current of the dynamic memristor increases nonlinearly from 0μA to 20μA.

[0064] Dynamic memristors also have certain memory properties. Figure 3B 2 shows the current response of the dynamic memristor when a pulse voltage signal is applied to the dynamic memristor. For example, in at least one embodiment of the present disclosure, Figure 3BAs shown, the amplitude of the first pulse voltage signal applied to the dynamic memristor is about 2V, and the action time is less than 0.1ms. The dynamic memristor produces a weak current response as the voltage action time increases. For example, the amplitude of the second pulse voltage signal applied to the dynamic memristor is about 3V, which is greater than the response threshold voltage of the dynamic memristor. The dynamic memristor enters the "ON" state, and the output current of the dynamic memristor increases sharply. After the voltage signal continues to act for less than 0.1ms, the current of the dynamic memristor increases to about 60μA. It is worth mentioning that after applying a turn-on voltage greater than the threshold voltage of the dynamic memristor, a temporary current-induced response will be generated on the subsequent state of the memristor. For example, Figure 3B As shown, after the dynamic memristor is turned on and a third pulse voltage is applied again that is the same as the first pulse voltage, the output current of the dynamic memristor responds faster and is larger than the output current under the action of the first pulse voltage. When the fourth pulse voltage is applied, the output current of the dynamic memristor also shows a similar response, which indicates that the dynamic memristor has the function of remembering the previous state, especially the function of remembering the previously turned-on "ON" state.

[0065] Figure 3C The output current response curve of the dynamic memristor under voltage pulses of different amplitudes is shown. Figure 3C As shown, when a 2.0V pulse voltage is applied to the dynamic memristor five times in succession, the output current of the dynamic memristor gradually accumulates and increases. For pulse voltages of other different amplitudes (2.1V-2.5V), the output current of the dynamic memristor also shows the same change trend under the action of the accumulated voltage pulses. This electrical characteristic of the dynamic memristor is also applicable to pulse voltages of other amplitudes, which will not be repeated here.

[0066] For example, Figure 3C As shown in FIG. 1 , a voltage signal with the same pulse width and pulse interval but different amplitudes is applied to the dynamic memristor. The output current of the dynamic memristor accumulates nonlinearly with the increase of the voltage pulse amplitude. The test results of the dynamic memristor are fitted, and the relationship curve between the output current and the voltage pulse amplitude of the dynamic memristor is obtained as shown in FIG. Figure 3D As shown, and satisfies the following formula:

[0067] I∝α·exp(β·qV / KT)

[0068] Where I is the output response current, V is the applied voltage, q is the electron charge, K is the Boltzmann constant, T is the temperature, and α and β are fitting parameters, which are related to the size, material, and applied pulse conditions of the dynamic memristor device.

[0069] Figure 3E The output current response curve of the dynamic memristor under voltage signals with different pulse widths is shown in FIG. Figure 3E As shown, the amplitude and pulse interval of the applied voltage signal are kept unchanged, and the pulse width t of the voltage signal is changed. pw , for example, the pulse width t of the applied voltage signal pw The output current of the dynamic memristor increases slowly with the increase of the pulse width of the voltage signal from 200μs to 1ms with a step size of 100μs. The test results of the output current of the dynamic memristor under voltage signals with different pulse widths are fitted, and the relationship curve between the output current of the dynamic memristor and the voltage pulse width is obtained as shown in the figure. Figure 3F As shown, and satisfies the following formula:

[0070] I∝I e -δ·exp(-t pw / τ)

[0071] Where, I is the output response current, t pw is the pulse width of the applied voltage, τ is the time constant associated with ion migration under the applied electric field and chemical potential gradient, I e and δ are fitting parameters, which are related to the size, material and applied pulse conditions of the dynamic memristor device.

[0072] Figure 3G The output current response curve of the dynamic memristor under voltage signals with different pulse intervals is shown in FIG. Figure 3G As shown, the amplitude and pulse width of the applied voltage signal are kept unchanged, and the pulse interval of the voltage signal is changed. For example, the pulse interval of the applied voltage signal is increased from 200μs to 1ms. Figure 3G As can be seen from the graph, the smaller the interval between applied voltage pulses, the higher the degree to which the output current of the dynamic memristor can be accumulated. For example, under a pulse voltage with a pulse interval of 200μs, the output current of the dynamic memristor accumulates as the number of voltage pulses increases. After applying five voltage pulses in succession, the output current value of the dynamic memristor is the highest under a pulse interval of 200μs. The test results of the dynamic memristor output current under voltage signals with different pulse intervals are fitted, and the relationship curve between the output current of the dynamic memristor and the voltage pulse interval is obtained as shown in the figure. Figure 3H As shown, and satisfies the following formula:

[0073] I∝γ·exp(-t i / t0)

[0074] Where, I is the output response current, t i is the pulse interval of the applied voltage, t0 is the time constant associated with ion migration under the applied electric field and chemical potential gradient, and γ is a fitting parameter, which is related to the size, material and applied pulse conditions of the dynamic memristor device.

[0075] As shown in the examples above, the rich input-output characteristics of the dynamic memristor give it powerful timing information processing capabilities. Therefore, introducing dynamic memristors into the current basic information processing units can enable the information processing units to have both the logic information processing functions of transistors and the timing information processing functions of dynamic memristors, thereby simplifying the system architecture and reducing the system area and power consumption.

[0076] At least one embodiment of the present disclosure provides a dynamic information processing unit having a dynamic logic calculation function. Figure 4A A structural schematic diagram of a dynamic information processing unit provided for one embodiment of the present disclosure, the dynamic information processing unit includes an electrically connected dynamic memristor 10 and a switch element 20, the input signal of the switch element 20 is provided by the dynamic memristor 10 (or processed by the dynamic memristor 10), and the output signal of the switch element 20 includes a timing dynamic signal (component) introduced by the dynamic memristor 10.

[0077] For example, the switch element 20 includes a transistor. For example, the transistor may be a bipolar transistor, a thin film transistor, a field effect transistor (e.g., a MOS field effect transistor), or other switching devices with the same characteristics. For example, the transistor may be an N-type transistor or a P-type transistor. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure. The embodiments of the present disclosure do not limit the type of transistor used.

[0078] For example, Figure 4A As shown, the first end of the dynamic memristor 10 is connected to a signal source (e.g., an input voltage end), and the second end of the dynamic memristor 10 is electrically connected to the switch element 20, for example, the two are directly electrically connected. For example, the second end of the dynamic memristor 10 is connected to the source or drain of the switch element 20, so that the level of the source or drain of the switch element 20 is regulated by the dynamic memristor 10; the switch element 20 is in a cut-off state, an amplified state, or a saturated state based on the voltage of the control signal applied to its gate, and controls the conduction state between the source and the drain.

[0079] For example, the dynamic memristor 10 receives an input voltage signal from an input voltage terminal, and outputs a current signal containing timing information to the switch element 20 according to the input voltage signal. i With the input voltage signal V i Satisfaction Figures 3A-3H The dynamic information processing unit has a simple structure, low power consumption, and has both logic information processing capability and timing information processing capability, and can process complex spatiotemporal information.

[0080] Figure 4BA schematic diagram of the structure of another dynamic information processing unit provided in an embodiment of the present disclosure, Figure 4B Examples and Figure 4A The comparison also includes a resistor 30. Figure 4B As shown, the first end of the dynamic memristor 10 is connected to a signal source (e.g., an input voltage end), the second end of the dynamic memristor 10 is electrically connected to the switching element 20, for example, the two are directly connected, and the second end of the dynamic memristor 10 is also electrically connected to a resistor 30 (e.g., the example of a "first resistor" in the present disclosure), so the resistor 30 is also electrically connected to the switching element 20, for example, the two are directly connected.

[0081] For example, the second end of the dynamic memristor 10 is connected to the gate of the switch element 20, and the dynamic memristor 10 is connected in series with the first end of the resistor 30, and the second end of the resistor 30 is connected to other devices or means, such as grounding. For example, in the illustrated example, the resistor 30 plays a voltage dividing role in the dynamic information processing unit, thereby regulating the gate voltage of the switch element 20 together with the dynamic memristor 10. For example, the resistance of the resistor 30 is R, the current flowing through the resistor 30 is I, and the gate voltage V1 of the switch element 20 is equal to the product of the resistance of the resistor 30 and the current flowing through the resistor 30, that is, V1=I×R, so the gate voltage V1 can be used to adjust the degree of opening of the switch element 20. For example, the current I flowing through the resistor 30 is dynamically regulated by the dynamic memristor 10, and the gate voltage of the switch element 20 includes the voltage V1 of the dynamic memristor 10 to the input voltage V i Processed timing information.

[0082] The dynamic information processing unit in at least one embodiment of the present disclosure may also include multiple dynamic memristors. For example, the multiple dynamic memristors included in the dynamic information processing unit may have the same or different electrical characteristics. For example, the multiple dynamic memristors included in the dynamic information processing unit may be connected to each other in parallel or in series, or the multiple dynamic memristors may not be connected to each other. For example, the multiple dynamic memristors included in the dynamic information unit may be connected to one signal source or to multiple signal sources.

[0083] For example, Figure 4CA dynamic information processing unit including a plurality of dynamic memristors 10 is shown. For example, the first ends of the plurality of dynamic memristors 10 are respectively connected to a plurality of signal sources (e.g., input voltage terminals V0, V1, ..., Vn). For example, the plurality of dynamic memristors 10 are connected to the gate of the switching element 20 through the second ends in parallel, and are connected to the first end of the voltage divider resistor 30. For example, the plurality of dynamic memristors 10 may have the same performance, but receive different input signals V0, V1, ..., Vn from the input voltage terminal. For example, the sum of the output currents of the plurality of dynamic memristors 10 is used as an input signal of the switching element 20, and the input signal contains complex timing information. For example, the switching element 20 is jointly regulated by the performance of each of the plurality of dynamic memristors 10 and the input signals of the plurality of signal sources.

[0084] In addition to including a plurality of dynamic memristors 10, Figure 4C The other structures and functions of the dynamic information processing unit shown are the same as those Figure 4B The embodiments shown are the same, and the details can be found in the above description, which will not be repeated here.

[0085] The switch element in the dynamic information processing unit in at least one embodiment of the present disclosure has a logic information processing function, and the switch element can be set according to actual needs. For example, in addition to the switch element composed of a single transistor in the above embodiment, which can realize the "logical true" and "logical false" functions, the switch element in at least one embodiment of the present disclosure can also include one or more transistors, such as a logic gate circuit composed of transistors, including but not limited to an AND gate, an OR gate, a NOT gate, etc.

[0086] For example, Figure 5 As shown, at least one embodiment of the present disclosure further provides a structural schematic diagram of another dynamic information processing unit, which includes a NOT gate circuit composed of two switch elements 20, and a dynamic memristor 10 connected to the input end of the switch element. For example, the dynamic information processing unit may also include a resistor 30, and the resistor 30 may be connected in series with the dynamic memristor 10 between the input voltage end and the ground.

[0087] Figure 4A-4C as well as Figure 5The basic structure of the dynamic information processing unit provided by at least one embodiment of the present disclosure is shown, and the basic structure includes at least one dynamic memristor and at least one switch element. After a certain input voltage signal is applied to the dynamic memristor, the dynamic memristor enters the "ON" state, and the switch element regulated by the dynamic memristor can realize different functions as the output current of the dynamic memristor changes. When the input voltage signal applied to the dynamic memristor is removed, the switch element will slowly close as the output current of the dynamic memristor decays. Due to the memory characteristics of the dynamic memristor and the nonlinear accumulation characteristics of the output current, the repeated application of voltage signals of different amplitudes or pulse widths to the dynamic memristor can increase the output current of the dynamic memristor, which is consistent with the process of repeatedly stimulating the presynaptic neuron to increase the postsynaptic current. Therefore, the dynamic information processing unit with such a structure can improve the transmission efficiency of the synapse, thereby realizing the short-term learning function of the synapse.

[0088] In addition to the basic structure of the dynamic information processing unit described in the above embodiment, the dynamic information processing unit may include other devices, such as capacitors, inductors, etc., in addition to the above resistors, or may include other types of storage devices, such as memristors. For example, the memristor may be a non-volatile memristor. The non-volatile memristor may be implemented as a resistive memory device, etc.

[0089] Resistive memory is a non-volatile device whose conductance state can be adjusted by applying external stimuli. It can be used as a storage unit or a computing unit. For example, when the resistive memory is used as a storage unit, different conductance states (or resistance states, resistance and conductance are inversely proportional to each other) of the resistive memory can be used to store different data information. When the resistive memory is used as a computing unit, for example, an input voltage can be applied to the resistive memory, and the array composed of the resistive memory can complete the multiplication and accumulation calculation in parallel. For example, the conductance value of the resistive memory can be used as a multiplier in the multiplication calculation of two numbers. Resistive memory has good application prospects in the fields of artificial intelligence, neural networks, and memory, and is a very promising device for realizing biological neural networks.

[0090] The following will take non-volatile resistive memory as an example. Figure 6A-6D Some specific but non-limiting examples illustrate a dynamic information processing unit proposed in at least one embodiment of the present disclosure.

[0091] Fig. 6A A dynamic information processing unit with a 1TIR structure is provided in one embodiment of the present disclosure. Figure 4ACompared with the embodiment shown in the figure, in addition to the dynamic memristor 10 and the switch element 20, a non-volatile memristor 40 is also included. The non-volatile memristor 40 is connected to the switch element 20, for example, the two are directly connected. Fig. 6A As shown, the first end of the dynamic memristor 10 is connected to the input voltage end, and the second end of the dynamic memristor 10 is connected to the first end of the non-volatile memristor 40, for example, the two are directly connected; the second end of the non-volatile memristor 40 is connected to the source or drain of the switching element 20, that is, the dynamic memristor 10 and the non-volatile memristor 40 are connected in series with each other and are connected as a whole to the source or drain of the switching element, so the input signal of the source or drain of the switching element 20 is also regulated by the dynamic memristor 10 and the non-volatile memristor 40.

[0092] At least one embodiment of the present disclosure also provides a structural diagram of another 1TIR structure dynamic information processing unit, such as Figure 6B As shown, the dynamic processing unit includes a dynamic memristor 10, a switch element 20 and a non-volatile memristor 40. Fig. 6A The difference from the illustrated embodiment is that in this embodiment, the second end of the dynamic memristor 10 is directly connected to the source or drain of the switch element 20, and the non-volatile memristor 40 is correspondingly connected to the drain or source of the switch element 20, that is, the dynamic memristor 10 and the non-volatile memristor 40 can be respectively connected to different connection ends of the switch element.

[0093] Figure 6C The dynamic information processing unit shown is Figure 4B Compared with the embodiment shown in FIG. 1 , the embodiment further includes a non-volatile memristor 40 connected to the source or drain end of the switch element 20. The other structures and functions of the dynamic information processing unit are similar to those of FIG. 1 . Figure 4B The dynamic information processing unit shown is the same, and the details can be referred to the above description, which will not be repeated here.

[0094] At least one embodiment of the present disclosure further provides a dynamic information processing unit having a 2T2R structure, that is, a dynamic information processing unit having two transistors 20 and two non-volatile memristors 40. For example, Fig.6D As shown, two non-volatile memristors 40 are respectively connected to two switch elements 20, and the gates of the two switch elements 20 are connected and connected to the second end of the dynamic memristor 10. For example, the gates of the two switch elements 20 may also be unconnected, so as to be respectively connected to the two dynamic memristors 10 to respectively receive the timing information output from the dynamic memristors. For example, the dynamic information processing unit of the 2T2R structure may also adopt the following method: Figure 4A In the structure shown, the dynamic memristor 10 can be connected to the source or drain of the two switch elements 20 .

[0095] Figure 6A-6D In addition to at least one dynamic memristor and at least one switch element, the dynamic information processing unit in the illustrated embodiment also includes a non-volatile memristor. The dynamic information processing unit of this structure can simulate the conversion process of synaptic memory from short-term memory to long-term memory. For example, after a certain input voltage signal is applied to the dynamic memristor through the first signal source, the dynamic memristor enters the "ON" state, and the gate voltage of the switch element is regulated by the output current of the dynamic memristor, so that the switch element is in an on or off state. When the switch element is in the on state, an input signal, such as a set voltage signal or a reset voltage signal, is applied to the non-volatile memristor through the second signal source, and the non-volatile memristor is in a low resistance state or a high resistance state accordingly. When the input voltage signal applied to the dynamic memristor is removed, the switch element will slowly close as the output current of the dynamic memristor decays. At this time, the non-volatile memristor can still maintain the current resistance state. Unless the voltage signal is applied again, the non-volatile memristor will not change the current memory state, thereby simulating the realization of the long-term memory function of the synapse.

[0096] The dynamic information processing unit in any of the above embodiments of the present disclosure has a simple structure and strong scalability, and can be easily integrated into a memristor array to simulate the learning and memory functions of biological neurons, thereby realizing a low-energy, high-performance dynamic information processing system.

[0097] At least one embodiment of the present disclosure further provides a memristor array, which includes the dynamic information processing unit in any of the above embodiments.

[0098] For example, a memristor array provided by at least one embodiment of the present disclosure includes at least one dynamic information processing unit and a plurality of memristor units arranged in an array, each memristor unit including a switch element and one or more memristors.

[0099] For example, Fig. 7A A memristor array with dynamic timing information processing and logic computing capabilities is shown. BL1, BL2, ..., BL n 1, 2, ..., Nth column, respectively, and the memristor 40 in the memristor unit circuit of each column is connected to the bit line corresponding to the column; SL1, SL2, ..., SL m ( Fig. 7A Only SL1 is shown in the figure to represent the source lines of the first row, the second row ... the Mth row, respectively. The source of the switch element 20 in each row of the memristor unit circuit is connected to the source line corresponding to the row. The control electrodes (gates of transistors) of the switch elements 20 in each row of the memristor unit circuit are connected together and connected to the dynamic memristor 10. For example, Fig. 7A As shown, the first terminal of the dynamic memristor 10 is connected to the first input voltage terminal Vi The second end of the dynamic memristor 10 is connected to the control electrodes of the plurality of switch elements 20. For example, the memristor array may include a plurality of dynamic memristors 10, and the plurality of dynamic memristors 10 are respectively connected to the control electrodes of one or more switch elements 20 in each row of the memristor array. For example, the memristor array may also include a plurality of resistors 30, and the plurality of resistors 30 may be respectively connected to the plurality of dynamic memristors 10, or the plurality of resistors 30 may also be connected to some of the memristors in the plurality of dynamic memristors 10 or not connected.

[0100] At least one embodiment of the present disclosure also provides another structure of a memristor array, such as Figure 7B As shown, each column of bit lines in the memristor array includes at least one dynamic memristor 10 and at least one switch element 20, and also includes a plurality of non-volatile memristors 40. For example, a first end of the dynamic memristor 10 on each column of bit lines is connected to the bit line input end, a second end of the dynamic memristor 10 is connected to a first end of the non-volatile memristor 40, and a second end of the non-volatile memristor 40 is connected to a source of the switch element 30.

[0101] For example, at least one bit line or source line in the memristor array provided by at least one embodiment of the present disclosure includes a dynamic memristor 10. For example, the dynamic memristor 10 and the non-volatile memristor 40 can be connected according to Figure 6B The structure of the embodiment shown is respectively connected to the source or drain of the switch element 20. In summary, the dynamic information processing unit in the embodiment of the present disclosure can be set in the memristor array in various feasible ways according to the needs of the actual circuit, thereby enriching the functions of the integrated memory computing architecture and improving the processing capability of the integrated memory computing architecture for complex spatiotemporal information. The basic structure of the dynamic information processing unit and the memristor array are integrated to realize the function of simulating the learning and memory of biological neural networks, thereby improving the bionic ability of artificial neural networks, effectively simplifying the system circuit, and reducing system power consumption.

[0102] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0103] There are a few points to note about this disclosure:

[0104] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0105] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0106] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0107] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A dynamic information processing unit, comprising a switch element, a dynamic memristor and a non-volatile resistive switching device, wherein: The dynamic memristor is electrically connected to the switch element, and the output signal of the switch element includes a timing dynamic signal introduced by the dynamic memristor. Wherein, the first end of the non-volatile resistive switching device is electrically connected to the switch element; The non-volatile resistive device and the dynamic memristor are connected in series and integrally connected to one connection end of the switch element, or the non-volatile resistive device and the dynamic memristor are respectively connected to different connection ends of the switch element.

2. The dynamic information processing unit according to claim 1, wherein: The dynamic memristor includes a first electrode layer, a dielectric layer and a second electrode layer.

3. The dynamic information processing unit according to claim 1, wherein: The switching element includes a transistor, and the switching element includes a source, a drain, and a gate.

4. The dynamic information processing unit according to claim 3, wherein: The first end of the dynamic memristor is connected to the first voltage end, and the second end of the dynamic memristor is electrically connected to the source or the drain of the switch element.

5. The dynamic information processing unit according to claim 3, wherein: The first end of the dynamic memristor is connected to the first voltage end, and the second end of the dynamic memristor is electrically connected to the gate of the switch element.

6. The dynamic information processing unit according to any one of claims 1 to 5, further comprising a first resistor, wherein: The first resistor is connected in series with the dynamic memristor, a first end of the first resistor is electrically connected to the switch element, and the first end of the first resistor is also connected to or not connected to the dynamic memristor.

7. A memristor array, comprising one or more dynamic information processing units according to any one of claims 1-6.

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