Method of operating a memory device

Abstract

The present invention discloses an operation method of a memory device. The operation method comprises: during a pre-conduction period, a redundant word line voltage rises to a first redundant word line voltage; during a reading period, the redundant word line voltage rises from the first redundant word line voltage to a second redundant word line voltage; and at the end of the reading period, the redundant word line voltage is reduced; wherein the first redundant word line voltage is lower than the second redundant word line voltage.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology and relates to an operation method of a memory device, and in particular to a reading operation method of a memory device. Background Art

[0002] For a three-dimensional (3D) memory device, after many read cycles (eg, after 100K read cycles), some dummy word lines (DWLs) may encounter a read disturbance problem, especially for the dummy word lines of unselected sub-blocks.

[0003] After analysis, it is known that when the string select line (SSL) or the global select line (GSL) is turned off during the pre-turn-on period, if the pass voltage (Vpass) of the unselected word line is lower than the threshold of the string select line or the global select line, a down-coupling effect will occur. This will cause a large channel potential difference between the redundant word line and the string select line, or between the redundant word line and the global select line, and a high vertical electronic field in the redundant word line. This makes hot carrier injection more likely to occur, thereby causing read disturbance. Summary of the invention

[0004] According to an embodiment of the present disclosure, a method for operating a memory device is provided, comprising: during a pre-conduction period, a redundant word line voltage is increased to a first redundant word line voltage; during a read period, the redundant word line voltage is increased from the first redundant word line voltage to a second redundant word line voltage; and at the end of the read period, the redundant word line voltage is reduced; wherein the first redundant word line voltage is lower than the second redundant word line voltage.

[0005] According to another embodiment of the present disclosure, a method for operating a memory device is provided, comprising: during a pre-conduction period, a redundant word line voltage rises to a first redundant word line voltage, and at the end of the pre-conduction period, the redundant word line voltage drops; the redundant word line voltage rises to a second redundant word line voltage; and at the end of a read period, the redundant word line voltage drops, wherein the first redundant word line voltage is lower than the second redundant word line voltage; and a rising edge of the redundant word line voltage rising to the second redundant word line voltage is earlier than a rising edge of a selected word line voltage.

[0006] According to another embodiment of the present disclosure, a method for operating a memory device is proposed, including: during a pre-conduction period, a string selection line voltage of at least one unselected sub-block rises to a first string selection line voltage; at the end of the pre-conduction period, the string selection line voltage of the at least one unselected sub-block drops from the first string selection line voltage to a second string selection line voltage, the first string selection line voltage being higher than the second string selection line voltage; and the string selection line voltage of the at least one unselected sub-block drops from the second string selection line voltage.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a functional block diagram of a memory device according to an embodiment of the present disclosure.

[0009] Figure 2 A three-dimensional (3D) circuit diagram of a memory array according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A waveform diagram showing a read operation of the memory device according to the first embodiment of the present disclosure is shown.

[0011] Figure 4 A comparison diagram of the horizontal electric field and the vertical electric field between the prior art and the first embodiment of the present disclosure is shown.

[0012] Figure 5 A curve diagram showing the relationship between the threshold voltage change and the number of read times in the prior art and the first embodiment of the present disclosure.

[0013] Figure 6 A waveform diagram showing a read operation of a memory device according to a second embodiment of the present disclosure is shown.

[0014] Figure 7 A comparison diagram of the horizontal electric field and the vertical electric field is shown between the prior art and the second embodiment of the present disclosure.

[0015] Figure 8 A curve diagram showing the relationship between the threshold voltage change and the number of read times in the prior art and the second embodiment of the present disclosure.

[0016] Fig. 9 A waveform diagram showing a read operation of a memory device according to a third embodiment of the present disclosure is shown.

[0017] Fig.10 A comparison diagram of the horizontal electric field and the vertical electric field is shown between the prior art and the third embodiment of the present disclosure.

[0018] Fig.11A curve diagram showing the relationship between the threshold voltage change and the number of read times in the prior art and the third embodiment of the present disclosure.

[0019]

Explanation of symbols

[0020] 100: Memory device

[0021] 110: Controller

[0022] 120: Memory array

[0023] SSL0_0~SSL2_3: string selection line

[0024] DWLT1, DWLT0, DWLB1, DWLT1: Redundant word lines

[0025] WL0~WLN-1: word line

[0026] BL0~BL3: bit lines

[0027] GSL0~GSL3: overall selection line

[0028] VBL: bit line voltage

[0029] VSWL: selected word line voltage

[0030] VUWL: Unselected word line voltage

[0031] VDWL: Redundant word line voltage

[0032] VSSL: string selection line voltage

[0033] VGSL: Overall selection of line voltage

[0034] VDWL1: First redundant word line voltage

[0035] VDWL2: Second redundant word line voltage

[0036] T31~T36: Timing

[0037] BL: Bit Line

[0038] SSL0~SSL2: string selection line

[0039] GSL: Global Selection Line

[0040] L31~L34, L41~L44: Curve

[0041] VDWL1A: First redundant word line voltage

[0042] VDWL2A: Second redundant word line voltage

[0043] T61~T67: Timing

[0044] L71~L78: Curve

[0045] VSSL1: First string selection line voltage

[0046] VSSL2: Second string selection line voltage

[0047] T91~T97: Timing

[0048] L101~L108: Curve DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0050] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, technicians in this technical field may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0051] Please refer to Figure 1 , which illustrates a functional block diagram of a memory device according to an embodiment of the present disclosure. The memory device 100 includes a controller 110 and a memory array 120. The controller 110 is coupled to the memory array 120. The controller 110 controls operations of the memory array 120, such as read operations.

[0052] Figure 2 A three-dimensional (3D) circuit diagram of a memory array 120 according to an embodiment of the present disclosure is shown. The memory array 120 includes: a plurality of string selection lines (SSL) (SSL0_0 to SSL2_3), a plurality of dummy word lines (DWLT1, DWLT0, DWLB1, DWLB0), a plurality of word lines (WL0 to WLN-1, N is a positive integer), a plurality of bit lines (BL0 to BL3), a plurality of global selection lines (GSL0 to GSL3), and a plurality of memory cells. It should be understood that Figure 2 This is just an example, and the embodiments of the present disclosure are not limited thereto.

[0053] Generally speaking, the memory array 120 includes a plurality of memory blocks. Each memory block includes, for example but not limited to, four sub-blocks. Figure 2Specifically, the sub-blocks SB0 ˜ SB3 can be independently selected by the string selection lines SSL0_0 ˜ SSL2_3 and the global selection lines GSL0 ˜ GSL3 , respectively.

[0054] Generally speaking, the bias conditions of the word lines at the border may be less consistent than the bias conditions of the word lines at the center. In one possible embodiment of the present disclosure, in order to make the bias conditions of the word lines WL0 to WLN-1 consistent, redundant word lines (DWLT1, DWLT0, DWLB1, DWLB0) are set on both sides of the word lines WL0 to WLN-1. Figure 2 For example, redundant word lines DWLB1 and DWLB0 are arranged outside word line WL0, and redundant word lines DWLT1 and DWLT0 are arranged outside word line WLN-1. That is, redundant word lines DWLB1 and DWLB0 are located between word line WL0 and overall selection lines GSL0-GSL3, and redundant word lines DWLT1 and DWLT0 are located between word line WLN-1 and string selection lines SSL0_0-SSL2_3. Thus, the bias conditions of word lines WL0-WLN-1 can be consistent. Memory cells connected to general word lines WL0-WLN-1 can be used for data access; in contrast, dummy cells connected to redundant word lines DWLT1, DWLT0, DWLB1, and DWLB0 are not used for data access.

[0055] Furthermore, in the disclosed embodiment, the voltage applied to the redundant word line is independent of the voltage applied to the word lines WL0 ˜WLN- 1 , and the details will be described below.

[0056] But it should be understood that Figure 2 In the figure, the number and position of redundant word lines are used for illustration only, and the present disclosure is not limited thereto.

[0057] Figure 3 The waveform diagram of the read operation of the memory device of the first embodiment of the present disclosure is shown. VBL represents the bit line voltage applied to the bit lines BL0~BL3; VSWL represents the selected word line voltage applied to the selected word lines of the word lines WL0~WLN-1; VUWL represents the unselected word line voltage applied to the unselected word lines of the word lines WL0~WLN-1; VDWL represents the redundant word line voltage applied to the redundant word lines DWLT1, DWLT0, DWLB1, DWLB0; VSSL represents the string selection line voltage applied to the string selection lines SSL0_0~SSL2_3; and VGSL represents the overall selection line voltage applied to the overall selection lines GSL0~GSL3.

[0058] In the first embodiment of the present disclosure, during the pre-conduction period, the bit line voltage VBL is at a low voltage (for example but not limited to, 0V), and during the read period, the bit line voltage VBL transitions to a high voltage (T33), and at the end of the read period (T36), the bit line voltage VBL transitions to a low voltage.

[0059] In the first embodiment of the present disclosure, during the pre-conduction period, the selected word line voltage VSWL rises at timing T31 and falls at timing T32; during the reading period, the selected word line voltage VSWL has two levels of voltage, the first level voltage rises at timing T34, and the second level voltage rises at timing T35, and at the end of the reading period, the selected word line voltage VSWL transitions to a low voltage.

[0060] In the first embodiment of the present disclosure, during the pre-turn-on period, the unselected word line voltage VUWL rises at the timing T31 ; at the end of the read period, the unselected word line voltage VUWL transitions to a low voltage.

[0061] In the first embodiment of the present disclosure, during the pre-conduction period, the redundant word line voltage VDWL rises to the first redundant word line voltage VDWL1 at the timing T31; during the reading period, the redundant word line voltage VDWL rises from the first redundant word line voltage VDWL1 to the second redundant word line voltage VDWL2 at the timing T33; at the end of the reading period, the redundant word line voltage VDWL transitions to a low voltage. The first redundant word line voltage VDWL1 is lower than the second redundant word line voltage VDWL2.

[0062] In the first embodiment of the present disclosure, during the pre-turn-on period, the redundant word line voltage VDWL rises to the first redundant word line voltage VDWL1, which can reduce the vertical electric field of the redundant word line during the pre-turn-on period.

[0063] In the first embodiment of the present disclosure, during the read period, the redundant word line voltage VDWL rises from the first redundant word line voltage VDWL1 to the second redundant word line voltage VDWL2, which can effectively turn on the memory cell string to obtain a higher memory cell string read current.

[0064] In the first embodiment of the present disclosure, the first redundant word line voltage VDWL1 and the second redundant word line voltage VDWL2 may be applied to all redundant word lines (eg, DWLT1, DWLT0, DWLB1, DWLB0).

[0065] Alternatively, in the first embodiment of the present disclosure, different first redundant word line voltages VDWL1 and different second redundant word line voltages VDWL2 are applied to the redundant word lines (eg, DWLT1, DWLT0, DWLB1, DWLB0).

[0066] Alternatively, in the first embodiment of the present disclosure, the first redundant word line voltage VDWL1 and the second redundant word line voltage VDWL2 are applied to at least one adjacent redundant word line (such as DWLT1 and DWLB0) of these redundant word lines, wherein at least one adjacent redundant word line is defined as a redundant word line adjacent to at least one selection line (such as the string selection line SSL0 and the global word line GSL).

[0067] In the first embodiment of the present disclosure, the value of the first redundant word line voltage VDWL1 is, for example but not limited to, greater than the threshold voltage of the memory cell of the redundant word line, and may be between 2V and 5V.

[0068] In the first embodiment of the present disclosure, the value of the second redundant word line voltage VDWL2 is related to the pass voltage (Vpass). For example, the value of the second redundant word line voltage VDWL2 is, for example but not limited to, a sufficiently high pass voltage (Vpass), which may be between 6V and 9V.

[0069] In the first embodiment of the present disclosure, during the pre-conduction period, the string selection line voltage VSSL of the selected sub-block (indicated by curve L31) and the string selection line voltage VSSL of the unselected sub-block (indicated by curve L32) rise at timing T31. Moreover, at the end of the pre-conduction period, the string selection line voltage VSSL of the unselected sub-block (indicated by curve L32) drops at timing T32. At the end of the read period, the string selection line voltage VSSL of the selected sub-block (indicated by curve L31) drops. During the read period, the string selection line voltage VSSL of the unselected sub-block (indicated by curve L32) continues to maintain a low voltage.

[0070] In the first embodiment of the present disclosure, during the pre-conduction period, the overall selection line voltage VGSL (indicated by curve L33) of the selected sub-block and the overall selection line voltage VGSL (indicated by curve L34) of the unselected sub-block rise at timing T31. Moreover, at the end of the pre-conduction period, the overall selection line voltage VGSL (indicated by curve L34) of the unselected sub-block drops at timing T32. At the end of the read period, the overall selection line voltage VGSL (indicated by curve L33) of the selected sub-block drops. During the read period, the overall selection line voltage VGSL (indicated by curve L34) of the unselected sub-block continues to maintain a low voltage.

[0071] Figure 4A comparison diagram of the horizontal electric field and the vertical electric field between the prior art and the first embodiment of the present disclosure is shown, wherein the horizontal axis represents the coordinate position, corresponding to the structural diagram above. Curve L41 represents the horizontal electric field curve between the channel and ONO (oxide-nitride-oxide) at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the first embodiment of the present disclosure is not applied) at the end of the pre-conduction period. Curve L42 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 at the end of the pre-conduction period in the prior art memory device (the read operation of the first embodiment of the present disclosure is not applied). Curve L43 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the first embodiment of the present disclosure at the end of the pre-conduction period. Curve L44 represents a vertical electric field curve between ONO and the gate at the string selection lines SSL2 , SSL1 , SSL0 and the redundant word line DWLT1 in the memory device according to the first embodiment of the present disclosure at the end of the pre-turn-on period.

[0072] Comparing the curve L42 with the curve L44 , it can be seen that the read operation of the first embodiment of the present disclosure can effectively reduce the vertical electric field, thereby reducing the read disturbance.

[0073] Figure 5 A curve diagram showing the relationship between the threshold voltage change amount and the number of read times in the prior art and the first embodiment of the present disclosure. Figure 5 It can be seen that the first embodiment of the present disclosure can reduce the threshold voltage variation, thereby reducing the read disturbance.

[0074] Figure 6 A waveform diagram showing a read operation of a memory device according to a second embodiment of the present disclosure is shown.

[0075] In the second embodiment of the present disclosure, during the pre-on period, the bit line voltage VBL is at a low voltage, and during the read period, the bit line voltage VBL transitions to a high voltage (T64), and at the end of the read period (T67), the bit line voltage VBL transitions to a low voltage.

[0076] In the second embodiment of the present disclosure, during the pre-conduction period, the selected word line voltage VSWL rises at timing T61 and drops at timing T62; during the reading period, the selected word line voltage VSWL has two levels of voltage, the first level voltage rises at timing T65, and the second level voltage rises at timing T66, and at the end of the reading period, the selected word line voltage VSWL transitions to a low voltage.

[0077] In the second embodiment of the present disclosure, during the pre-conduction period, the unselected word line voltage VUWL rises at the timing T61; at the end of the read period, the unselected word line voltage VUWL transitions to a low voltage.

[0078] In the second embodiment of the present disclosure, during the pre-conduction period, the redundant word line voltage VDWL rises to the first redundant word line voltage VDWL1A at the timing T61 and falls at the timing T62; the redundant word line voltage VDWL rises to the second redundant word line voltage VDWL2A at the timing T63; at the end of the read period, the redundant word line voltage VDWL transitions to a low voltage. The first redundant word line voltage VDWL1A is lower than the second redundant word line voltage VDWL2A.

[0079] In the second embodiment of the present disclosure, the rising edge (ie, timing T63 ) of the redundant word line voltage VDWL rising to the second redundant word line voltage VDWL2A is at least earlier than the rising edge (timing T65 ) of the first level voltage of the selected word line voltage VSWL.

[0080] In the second embodiment of the present disclosure, during the pre-conduction period, the redundant word line voltage VDWL drops to a low voltage at the end of the pre-conduction period (timing T62), which can reduce the voltage difference between the selection line (string selection line SSL2 or global selection line GSL) and the adjacent redundant word line (DWLT1 or DWLB0). In addition, the voltage difference between the redundant word line DWLT0 and the word line WLN-1 is also small because the redundant word line DWLT0 is at a low voltage.

[0081] In the second embodiment of the present disclosure, when the redundant word line voltage VDWL rises to the second redundant word line voltage VDWL2A at timing T63, the downward coupling effect of the selection lines (string selection line SSL2 and global selection line GSL) has been alleviated, so the read disturbance can also be alleviated.

[0082] In the second embodiment of the present disclosure, the first redundant word line voltage VDWL1A and the second redundant word line voltage VDWL2A may be applied to all redundant word lines (eg, DWLT1, DWLT0, DWLB1, DWLB0).

[0083] Alternatively, in the second embodiment of the present disclosure, different first redundant word line voltages VDWL1A and different second redundant word line voltages VDWL2A are applied to the redundant word lines (eg, DWLT1, DWLT0, DWLB1, DWLB0).

[0084] Alternatively, in the second embodiment of the present disclosure, the first redundant word line voltage VDWL1A and the second redundant word line voltage VDWL2A are applied to at least one adjacent redundant word line (such as DWLT1 and DWLB0) of these redundant word lines, wherein at least one adjacent redundant word line is defined as being adjacent to at least one selection line (such as the string selection line SSL0 and the global word line GSL).

[0085] In the second embodiment of the present disclosure, the value of the first redundant word line voltage VDWL1A is, for example but not limited to, greater than the threshold voltage of the memory cell of the redundant word line, and may be between 2V and 5V.

[0086] In the second embodiment of the present disclosure, the value of the second redundant word line voltage VDWL2A is related to the pass voltage (Vpass). For example, the value of the second redundant word line voltage VDWL2A is, for example but not limited to, a sufficiently high pass voltage (Vpass), which may be between 6V and 9V.

[0087] In the second embodiment of the present disclosure, during the pre-conduction period, the string selection line voltage VSSL of the selected sub-block (indicated by curve L61) and the string selection line voltage VSSL of the unselected sub-block (indicated by curve L62) rise at timing T61. Moreover, at the end of the pre-conduction period, the string selection line voltage VSSL of the unselected sub-block (indicated by curve L62) drops at timing T62. At the end of the read period, the string selection line voltage VSSL of the selected sub-block (indicated by curve L61) drops. During the read period, the string selection line voltage VSSL of the unselected sub-block (indicated by curve L62) continues to maintain a low voltage.

[0088] In the second embodiment of the present disclosure, during the pre-conduction period, the overall selection line voltage VGSL (indicated by curve L63) of the selected sub-block and the overall selection line voltage VGSL (indicated by curve L64) of the unselected sub-block rise at timing T61. Moreover, at the end of the pre-conduction period, the overall selection line voltage VGSL (indicated by curve L64) of the unselected sub-block drops at timing T62. At the end of the read period, the overall selection line voltage VGSL (indicated by curve L63) of the selected sub-block drops. During the read period, the overall selection line voltage VGSL (indicated by curve L64) of the unselected sub-block continues to maintain a low voltage.

[0089] Figure 7A comparison diagram of the horizontal electric field and the vertical electric field between the prior art and the second embodiment of the present disclosure is shown. Curve L71 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the second embodiment of the present disclosure is not applied) at the end of the pre-conduction period; Curve L72 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 at the timing T63 in the prior art memory device (the read operation of the second embodiment of the present disclosure is not applied). Curve L73 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the second embodiment of the present disclosure is not applied) at the end of the pre-conduction period; Curve L74 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the second embodiment of the present disclosure is not applied) at the timing T63. Curve L75 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the second embodiment of the present disclosure at the end of the pre-conduction period; Curve L76 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the second embodiment of the present disclosure at the timing T63. Curve L77 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the second embodiment of the present disclosure at the end of the pre-conduction period; Curve L78 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the second embodiment of the present disclosure at timing T63.

[0090] Comparing curves L71 and L75, it can be seen that the read operation of the second embodiment of the present disclosure can effectively reduce the voltage difference between the string selection line SSL0 and the redundant word line DWLT1. Comparing curves L73 and L77, it can be seen that the read operation of the second embodiment of the present disclosure can effectively reduce the vertical electric field of the redundant word line DWLT1.

[0091] At the timing T63 , it can be seen from the curve L76 that the downward coupling effect has been alleviated, so the embodiment of the present disclosure can reduce the read disturbance.

[0092] Figure 8 A curve diagram showing the relationship between the threshold voltage change amount and the number of read times in the prior art and the second embodiment of the present disclosure. Figure 8 It can be seen that the second embodiment of the present disclosure can reduce the threshold voltage variation, thereby reducing the read disturbance.

[0093] Fig. 9 A waveform diagram showing a read operation of a memory device according to a third embodiment of the present disclosure is shown.

[0094] In the third embodiment of the present disclosure, during the pre-conduction period, the bit line voltage VBL is at a low voltage, and during the read period, the bit line voltage VBL transitions to a high voltage (T94), and at the end of the read period (T97), the bit line voltage VBL transitions to a low voltage.

[0095] In the third embodiment of the present disclosure, during the pre-conduction period, the selected word line voltage VSWL rises at timing T91 and drops at timing T92; during the reading period, the selected word line voltage VSWL has two levels of voltage, the first level voltage rises at timing T95, and the second level voltage rises at timing T96, and at the end of the reading period, the selected word line voltage VSWL transitions to a low voltage.

[0096] In the third embodiment of the present disclosure, during the pre-conduction period, the unselected word line voltage VUWL rises at the timing T91; at the end of the read period, the unselected word line voltage VUWL transitions to a low voltage.

[0097] In the third embodiment of the present disclosure, during the pre-turn-on period, the redundant word line voltage VDWL rises at the timing T91; at the end of the read period, the redundant word line voltage VDWL transitions to a low voltage.

[0098] In the third embodiment of the present disclosure, during the pre-conduction period, the string selection line voltage VSSL of the unselected sub-block rises to the first string selection line voltage VSSL1 at timing T91. Moreover, at the end of the pre-conduction period, the string selection line voltage VSSL of the unselected sub-block drops at timing T92, and the drop is divided into two stages. Specifically, the string selection line voltage VSSL of the unselected sub-block drops from the first string selection line voltage VSSL1 to the second string selection line voltage VSSL2 at timing T92, wherein the first string selection line voltage VSSL1 is higher than the second string selection line voltage VSSL2. The string selection line voltage VSSL of the unselected sub-block drops from the second string selection line voltage VSSL2 to a low voltage at timing T93. In the third embodiment of the present disclosure, the waveform of the string selection line voltage VSSL of the selected sub-block may be the same as or similar to Figure 6 The waveform of the string selection line voltage VSSL of the selected sub-block is not repeated here.

[0099] In the third embodiment of the present disclosure, the same string selection line voltage VSSL may be applied to the string selection lines SSL2 ˜ SSL0 . Fig. 9 shown.

[0100] In the third embodiment of the present disclosure, the value of the first string selection line voltage VSSL1 is, for example but not limited to, higher than the threshold voltage of the memory cells on the string selection lines SSL2 to SSL0. For example, if the threshold voltage of the memory cells on the string selection lines SSL2 to SSL0 is 3V, then the value of the first string selection line voltage VSSL1 may be between 5V and 8V.

[0101] In the third embodiment of the present disclosure, the value of the second string selection line voltage VSSL2 is, for example but not limited to, slightly lower than the threshold voltage of the memory cells on the string selection lines SSL2 to SSL0. For example, the value of the second string selection line voltage VSSL2 may be about half of the threshold voltage of the memory cells on the string selection lines SSL2 to SSL0. For example, if the threshold voltage of the memory cells on the string selection lines SSL2 to SSL0 is 3V, then the value of the second string selection line voltage VSSL2 may be between 1V and 2V or between 2V and 3V.

[0102] In the third embodiment of the present disclosure, during the pre-conduction period, the overall selection line voltage VGSL of the unselected sub-block rises at the timing T91. Moreover, at the end of the pre-conduction period, the overall selection line voltage VGSL of the unselected sub-block drops to a low voltage. In the third embodiment of the present disclosure, the waveform of the overall selection line voltage VGSL of the selected sub-block may be the same as or similar to Figure 6 The waveform of the overall selection line voltage VGSL of the selected sub-block is not repeated here.

[0103] Fig.10A comparison diagram of the horizontal electric field and the vertical electric field between the prior art and the third embodiment of the present disclosure is shown. Curve L101 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the third embodiment of the present disclosure is not applied) at the end of the pre-conduction period; Curve L102 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 at the timing T93 in the prior art memory device (the read operation of the third embodiment of the present disclosure is not applied). Curve L103 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the third embodiment of the present disclosure is not applied) at the end of the pre-conduction period; Curve L104 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the prior art memory device (the read operation of the third embodiment of the present disclosure is not applied) at the timing T93. Curve L105 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the third embodiment of the present disclosure at the end of the pre-conduction period; Curve L106 represents the horizontal electric field curve between the channel and ONO at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the third embodiment of the present disclosure at the timing T93. Curve L107 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the third embodiment of the present disclosure at the end of the pre-conduction period; Curve L108 represents the vertical electric field curve between ONO and the gate at the string selection lines SSL2, SSL1, SSL0 and the redundant word line DWLT1 in the memory device of the third embodiment of the present disclosure at timing T93.

[0104] Comparing curves L101 and L105, it can be seen that the read operation of the third embodiment of the present disclosure can effectively reduce the downward coupling effect of string selection lines SSL0-SSL2. Similarly, comparing curves L103 and L107, it can be seen that the read operation of the third embodiment of the present disclosure can effectively reduce the downward coupling effect of string selection lines SSL0-SSL2.

[0105] Even though the horizontal electric fields of the curves L106 and L101 are similar, the reading operation of the third embodiment of the present disclosure can effectively reduce the effective stress time. Therefore, the reading operation of the third embodiment of the present disclosure can effectively reduce the read disturbance.

[0106] Fig.11 A curve diagram showing the relationship between the threshold voltage change amount and the number of read times in the prior art and the third embodiment of the present disclosure. Fig.11 It can be seen that the third embodiment of the present disclosure can reduce the threshold voltage variation, thereby reducing the read disturbance.

[0107] The first to third embodiments described above can be implemented independently or in combination. That is, the first and third embodiments can be implemented in combination; or, the second and third embodiments can be implemented in combination. All of these are within the spirit of the present disclosure.

[0108] It can be seen from the above description that the above embodiments of the present disclosure can effectively alleviate abnormal read disturbance of redundant word lines.

[0109] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

[0110] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for operating a memory device, comprising: During a pre-conduction period, a redundant word line voltage rises to a first redundant word line voltage; During a read period, the redundancy word line voltage rises from the first redundancy word line voltage to a second redundancy word line voltage, wherein the first redundancy word line voltage is lower than the second redundancy word line voltage; as well as At the end of the read period, lowering the redundant word line voltage; During the pre-conduction period, a string selection line voltage of at least one unselected sub-block rises to a first string selection line voltage; at the end of the pre-conduction period, the string selection line voltage of the at least one unselected sub-block drops from the first string selection line voltage to a second string selection line voltage, and the first string selection line voltage is higher than the second string selection line voltage; the string selection line voltage of the at least one unselected sub-block drops from the second string selection line voltage.

2. The method for operating a memory device according to claim 1, wherein: The first redundant word line voltage and the second redundant word line voltage are applied to all redundant word lines of the memory device, and the redundant word lines are located adjacent to a plurality of word lines of the memory device; or Different first redundant word line voltages and different second redundant word line voltages are applied to the redundant word lines; or The first redundant word line voltage and the second redundant word line voltage are applied to at least one adjacent redundant word line of the redundant word lines, and the at least one adjacent redundant word line is adjacent to at least one selection line.

3. The method for operating a memory device according to claim 1, wherein: The first redundant word line voltage is greater than a threshold voltage of a plurality of memory cells of a plurality of redundant word lines of the memory device, and The second redundant word line voltage is related to a pass voltage.

4. A method for operating a memory device, comprising: During a pre-conduction period, a redundant word line voltage rises to a first redundant word line voltage, and at the end of the pre-conduction period, the redundant word line voltage drops; The redundant word line voltage rises to a second redundant word line voltage; as well as At the end of a read period, the redundant word line voltage drops. in, The first redundant word line voltage is lower than the second redundant word line voltage; as well as A rising edge of the redundant word line voltage rising to the second redundant word line voltage is earlier than a rising edge of a selected word line voltage.

5. The method for operating a memory device according to claim 4, wherein: The first redundant word line voltage and the second redundant word line voltage are applied to all redundant word lines of the memory device, and the redundant word lines are located adjacent to a plurality of word lines of the memory device; or Different first redundant word line voltages and different second redundant word line voltages are applied to the redundant word lines; or The first redundant word line voltage and the second redundant word line voltage are applied to at least one adjacent redundant word line of the redundant word lines, and the at least one adjacent redundant word line is adjacent to at least one selection line.

6. The method for operating a memory device according to claim 4, wherein: The first redundant word line voltage is greater than a threshold voltage of a plurality of memory cells of a plurality of redundant word lines of the memory device, and The second redundant word line voltage is related to a pass voltage.

7. The method for operating a memory device according to claim 4, wherein: During the pre-conduction period, a string selection line voltage of at least one unselected sub-block rises to a first string selection line voltage; At the end of the pre-conduction period, the string selection line voltage of the at least one unselected sub-block drops from the first string selection line voltage to a second string selection line voltage, the first string selection line voltage being higher than the second string selection line voltage; and The string selection line voltage of the at least one unselected sub-block drops from the second string selection line voltage.

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