Memory cell array for multi-programmable non-volatile memory

Abstract

The present invention is a memory cell array of a multi-programmable non-volatile memory. In the memory cell of the present invention, a bidirectional path is designed so that electrons are injected into and exit from the floating gate through the same gate end oxide layer, so that the memory cell has higher data retention reliability and endurance reliability. In addition, the present invention further designs a core device transistor in the memory cell and applies it to a read operation to reduce the read voltage of the memory cell.

Description

Technical Field

[0001] The present invention relates to a memory cell array of a non-volatile memory, and in particular to a memory cell array of a multi-time programmable (MTP) non-volatile memory and a memory cell in the memory cell array. Background Art

[0002] Please refer to Figure 1A , Figure 1B and Figure 1C , which shows a top view of a memory cell of a conventional MTP non-volatile memory, an equivalent circuit and a bias table for various operations. This memory cell is disclosed in U.S. Pat. No. 8,355,282.

[0003] like Figure 1A As shown, N-type well regions NW1, NW2 and P-type well region PW are formed on a semiconductor substrate. Then, three gate structures 471, 400, and 472 are formed using a polysilicon layer. Among them, the gate structure 400 covers the N-type well regions NW1, NW2 and P-type well region PW at the same time. The gate structures 471 and 472 cover the P-type well region PW and are located on two sides of the gate structure 400. In addition, the gate structure 400 serves as a floating gate (FG).

[0004] Next, n-doped regions 461, 462, 463, and 464 are formed in the P-type well region PW. The n-doped region 461 is located at one side of the gate structure 471, the n-doped region 462 is located between the gate structure 471 and the gate structure 400, the n-doped region 463 is located between the gate structure 400 and the gate structure 472, and the n-doped region 464 is located at one side of the gate structure 472.

[0005] Furthermore, p-doped regions 421, 422, 481, 482 are formed in the N-type well regions NW1 and NW2. The p-doped regions 421, 422 are formed in the N-type well region NW2 and are respectively located on two sides of the gate structure 400. The p-doped regions 481, 482 are formed in the N-type well region NW1 and are respectively located on two sides of the gate structure 400.

[0006] In addition, in the memory cell 40, the gate structure 471 is connected to the word line WL, the gate structure 472 is connected to the selection gate terminal line SG, the p-doped regions 421 and 422 are connected to the control line CL, the p-doped regions 481 and 482 are connected to the erase line EL, the n-doped region 461 is connected to the source line SL, and the n-doped region 464 is connected to the bit line BL.

[0007] like Figure 1B As shown, n-doped region 461, gate structure 471 and n-doped region 462 form transistor 530. N-doped region 462, gate structure 400 and n-doped region 463 form floating gate transistor 510. N-doped region 463, gate structure 472 and n-doped region 464 form transistor 540. Gate structure 400 and p-doped regions 421 and 422 can be considered as a transistor and connected to form a capacitor 500. Gate structure 400 and p-doped regions 481 and 482 can be considered as another transistor and connected to form a capacitor 520.

[0008] Therefore, in the equivalent circuit of the memory cell 40, the gate terminal of the transistor 530 is connected to the word line WL, the first terminal of the transistor 530 is connected to the source line SL, and the second terminal of the transistor 530 is connected to the first terminal of the floating gate transistor 510. The gate terminal of the transistor 540 is connected to the select gate terminal line SG, the first terminal of the transistor 540 is connected to the bit line BL, and the second terminal of the transistor 540 is connected to the second terminal of the floating gate transistor 510. The body terminals of the transistors 530, 540, and the floating gate transistor 510 are connected to the P-type well region PW. The first terminal of the capacitor 500 is connected to the floating gate of the floating gate transistor 510, and the second terminal of the capacitor 500 is connected to the control line CL. The first terminal of the capacitor 520 is connected to the floating gate of the floating gate transistor 510, and the second terminal of the capacitor 520 is connected to the erase line EL.

[0009] like Figure 1C As shown, after providing an appropriate bias voltage to the known memory cell 40 , a program operation, a program inhibit operation, an erase operation, and a read operation can be performed on the memory cell 40 .

[0010] During the programming operation (PGM), the control line CL and the erase line EL receive a voltage range of 5V to 20V. The select gate line SG receives a voltage range of 1V to 5V. The word line WL, source line SL, bit line BL and P-type well area PW receive a ground voltage (0V). Figure 1BAs shown, the floating gate transistor 510 undergoes FN electron tunneling injection, and an electron injection path P is generated between the channel of the floating gate transistor 510 and the floating gate. th1 That is, electrons are injected from the channel of the floating gate transistor 510 through the gate oxide layer into the floating gate, so that the electrons are stored in the floating gate and the programming operation is completed.

[0011] Compared with the programming operation (PGM), during the programming inhibition operation (PGM inhibit), only the voltage received by the bit line BL is different. During the programming inhibition operation (PGM inhibit), the voltage received by the bit line BL ranges from 1V to 7V. At this time, the floating gate transistor 510 does not undergo the FN electron tunneling injection effect, and no electron injection path P is generated between the channel of the floating gate transistor 510 and the floating gate. th1 That is, electrons cannot be injected from the floating gate transistor 510 channel into the floating gate, so that the floating gate does not store electrons.

[0012] During the erase operation (ERS), the erase line EL receives an erase voltage in the range of 5V to 20V. The control line CL, source line SL, bit line BL and P-type well region PW receive a ground voltage (0V). The word line WL and select gate terminal line SG receive a voltage in the range of 0V to 5V. Figure 1B As shown, the capacitor 520 undergoes FN electron tunneling ejection effect, and an electron ejection path P is generated between the floating gate and the erase line EL. th2 That is, electrons exit from the floating gate through the gate oxide layer of the capacitor 5202 to the erase line EL, and the erase operation is completed.

[0013] During the read operation (READ), the control line CL, the word line WL and the select gate end line SG receive a voltage range of 1V to 5V. The erase line EL receives a voltage range of 0V to 5V. The source line SL and the P-type well region PW receive a ground voltage (0V). The bit line BL receives a read voltage, and the voltage range of the read voltage is 1V to 5V. At this time, the memory cell 40 generates a read current (read current) flowing from the bit line BL to the source line SL. For example, assuming that the floating gate does not store electrons, the floating gate transistor 510 is turned on, and the memory cell 40 generates a larger read current. Conversely, assuming that the floating gate stores electrons, the floating gate transistor 510 is almost turned off, and the memory cell 40 generates a smaller read current. In other words, during the read operation, the storage state of the memory cell 40 can be determined according to the size of the read current.

[0014] From the above description, it can be seen that the conventional memory cell 40 utilizes the electron injection path P in the floating gate transistor 510 during the programming operation (PGM). th1 The conventional memory cell 40 utilizes the electron exit path P in the capacitor 520 during the erase operation (ERS). th2 The use of two unidirectional paths to inject and remove electrons respectively results in lower data retention reliability of the conventional memory cell 40 .

[0015] During the programming operation (PGM) of the conventional memory cell 40, electrons are injected into the floating gate through the gate oxide layer of the floating gate transistor 510. During the reading operation (READ) of the conventional memory cell 40, the floating gate transistor 510 is used to generate a read current. Since the conventional memory cell 40 requires the floating gate transistor 510 in both the programming operation (PGM) and the reading operation (READ), the endurance reliability of the floating gate transistor 510 is reduced.

[0016] As is known to all, in the process of integrated circuits, transistors classified as I / O devices can withstand higher voltage stress, but their operating voltage is higher. Transistors classified as core devices have lower operating voltages and therefore cannot withstand high voltage stress.

[0017] Taking the known memory cell 40 as an example, when the transistor 540 is in normal operation, the voltage stress (voltage difference) between the selection gate terminal line SG and the bit line BL to the P-type well region PW may reach 7 V. Similarly, the voltage stress (voltage difference) between the word line WL of the transistor 530 and the P-type well region PW may reach 5 V. In other words, both the transistor 530 and the transistor 540 are input / output devices that need to withstand higher voltage stress, so the read voltage of the known memory cell 40 will be higher during the read operation. Summary of the invention

[0018] The present invention provides a memory cell array of a multi-programmable non-volatile memory. In the memory cell of the present invention, a bidirectional path is designed so that electrons are injected into and exit from the floating gate through the same gate end oxide layer, so that the memory cell has higher data retention reliability and endurance reliability. In addition, the present invention further designs a core device transistor in the memory cell and applies it to a read operation to reduce the read voltage of the memory cell.

[0019] The present invention relates to a memory cell array of a multi-programmable non-volatile memory, the memory cell array comprising a first memory cell, the first memory cell comprising: a first well region and a second well region; a first gate structure covering the first well region and the second well region; a second gate structure covering the first well region; a third gate structure covering the second well region; a first doped region located in the first well region, on a first side of the first gate structure; a second doped region located in the first well region, between a second side of the first gate structure and a first side of the second gate structure; a third doped region located in the first well region, on a second side of the second gate structure; a fourth doped region located in the second well region, on the first side of the first gate structure; a fifth doped region located in the second well region, between the second side of the first gate structure and a first side of the third gate structure; a sixth doped region located in the second well region, on a second side of the third gate structure ; a first metal connection line connected to the first doped region; a second metal connection line connected to the second gate structure; a third metal connection line connected to the third gate structure; a fourth metal connection line connected to the first well region; a fifth metal connection line connected to the third doped region, and the fifth metal connection line is connected to the fourth metal connection line; a sixth metal connection line connected to the second well region; a seventh metal connection line connected to the sixth doped region, and the seventh metal connection line is connected to the sixth metal connection line; wherein the first well region, the first doped region, the second doped region and the first gate structure form a first transistor; the first well region, the second doped region, the third doped region and the second gate structure form a second transistor; the second well region, the fourth doped region, the fifth doped region and the first gate structure form a third transistor; and the second well region, the fifth doped region, the sixth doped region and the third gate structure form a fourth transistor.

[0020] The present invention relates to a memory cell array of a multi-programmable non-volatile memory, the memory cell array comprising a first memory cell, the first memory cell comprising: a first well region and a second well region; a first gate structure covering the first well region and the second well region; a second gate structure covering the first well region; a third gate structure covering the second well region; a fourth gate structure covering the second well region; a first doped region located in the first well region and on a first side of the first gate structure; a second doped region located in the first well region and on a second side of the first gate structure and on a a first side of the second gate structure; a third doped region located in the first well region and on a second side of the second gate structure; a fourth doped region located in the second well region and on a first side of the fourth gate structure; a fifth doped region located in the second well region and between a second side of the fourth gate structure and the first side of the first gate structure; a sixth doped region located in the second well region and between the second side of the first gate structure and a first side of the third gate structure; a seventh doped region located in the second well region and on a second side of the third gate structure; a first metal connecting line , connected to the first doped region; a second metal connection line, connected to the second gate structure; a third metal connection line, connected to the third gate structure; a fourth metal connection line, connected to the first well region; a fifth metal connection line, connected to the third doped region, and the fifth metal connection line is connected to the fourth metal connection line; a sixth metal connection line, connected to the second well region; a seventh metal connection line, connected to the seventh doped region; an eighth metal connection line, connected to the fourth doped region, and the eighth metal connection line is connected to the sixth metal connection line; and a ninth metal connection line , connected to the fourth gate structure; wherein the first well region, the first doped region, the second doped region and the first gate structure form a first transistor; the first well region, the second doped region, the third doped region and the second gate structure form a second transistor; the second well region, the fifth doped region, the sixth doped region and the first gate structure form a third transistor; the second well region, the fourth doped region, the fifth doped region and the third gate structure form a fourth transistor; and the second well region, the sixth doped region, the seventh doped region and the fourth gate structure form a fifth transistor.

[0021] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A , Figure 1B and Figure 1C A top view of a memory cell of a known MTP non-volatile memory, an equivalent circuit, and a bias table for various operations;

[0023] FIG. 2A to FIG. 2D The manufacturing process of the MTP non-volatile memory of the first embodiment of the present invention;

[0024] Figure 2E is an equivalent circuit diagram of the MTP non-volatile memory of the first embodiment of the present invention;

[0025] Figure 3A A bias table for various operations of the memory cell of the MTP non-volatile memory according to the first embodiment of the present invention;

[0026] FIG. 3B to FIG. 3E Schematic diagram of bias voltage for various operations of memory cells;

[0027] FIG. 4A to FIG. 4C A schematic diagram of bias voltage when the memory cell array of the first embodiment performs various operations;

[0028] Figure 5A and Figure 5B A top view and an equivalent circuit diagram of an MTP non-volatile memory according to a second embodiment of the present invention;

[0029] Fig. 6A A bias table for various operations of the memory cell of the MTP non-volatile memory according to the second embodiment of the present invention;

[0030] FIG. 6B to FIG. 6E schematic diagrams of biasing the memory cell for various operations; and

[0031] FIG. 7A to FIG. 7C FIG. 1 is a schematic diagram of bias voltage when the memory cell array of the second embodiment performs various operations.

[0032]

Explanation of symbols

[0033] 40: Memory Cell

[0034] 200, 600: memory cell array

[0035] 212, 214, 216, 222, 224, 226, 232, 234, 236, 242, 244, 246, 400, 471, 472: Gate structure

[0036] 251, 252, 253, 254, 255, 256, 257, 261, 262, 263, 264, 265, 271, 272, 273: n-doped regions

[0037] 274, 275, 461, 462, 463, 464, 612, 614, 622, 624, 632, 634, 642, 644: n-doped regions

[0038] 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294: Metal connecting wire

[0039] 295, 296, 616, 618, 626, 628, 636, 638, 646, 648: Metal connecting wire

[0040] 422, 421, 481, 482: p-doped regions

[0041] 500, 520: Capacitor

[0042] 510, 530, 540: transistors

[0043] 610, 620, 630, 640: Gate structure DETAILED DESCRIPTION

[0044] Please refer to FIG. 2A to FIG. 2D , which illustrates the manufacturing process of the MTP non-volatile memory of the first embodiment of the present invention. The MTP non-volatile memory includes 4 memory cells, forming a 2x2 memory cell array. Of course, the MTP non-volatile memory of the present invention is not limited to a 2x2 memory cell array, and can also form an mxn memory cell array, where m and n are positive integers.

[0045] like Figure 2A As shown, a deep N-well (DNW) is formed on a semiconductor substrate. Then, three isolated P-wells PW1, PW2, and PW3 are formed in the deep N-well DNW. Of course, the deep N-well DNW can also be replaced by an N-type buried layer (NBL).

[0046] like Figure 2BAs shown, a plurality of gate structures 212, 214, 216, 222, 224, 226, 232, 234, 236, 242, 244, 246 are formed. Among them, the gate structures 212 and 222 cover the P-type well regions PW1 and PW2 at the same time, the gate structures 232 and 242 cover the P-type well regions PW1 and PW3 at the same time, the gate structures 214, 224, 234, 244 cover the P-type well region PW1, the gate structures 216 and 226 cover the P-type well region PW2, and the gate structures 236 and 246 cover the P-type well region PW3. Furthermore, the above-mentioned gate structures all include a gate oxide layer and a polysilicon gate layer, the gate oxide layer covers the surface of the semiconductor substrate, and the polysilicon gate layer covers the gate oxide layer.

[0047] It is worth noting that the gate structures 212, 222, 232, 242 are in a convex shape, and the wider parts of the gate structures 212, 222, 232, 242 cover the P-type well region PW1, the narrower parts of the gate structures 212, 222 cover the P-type well region PW2, and the narrower parts of the gate structures 232, 242 cover the P-type well region PW3.

[0048] Next, a doping process is performed to form n-doped regions 251-257, 261-265, 271-275 in the P-type well regions PW1, PW2, and PW3. In the P-type well region PW1, the n-doped region 251 is located on the left side of the gate structures 212 and 232, the n-doped region 252 is located between the right side of the gate structure 212 and the left side of the gate structure 214, the n-doped region 253 is located between the right side of the gate structure 214 and the left side of the gate structure 224, the n-doped region 254 is located between the right side of the gate structure 224 and the left side of the gate structure 222, the n-doped region 256 is located between the right side of the gate structure 232 and the left side of the gate structure 234, the n-doped region 253 is located between the right side of the gate structure 234 and the left side of the gate structure 244, the n-doped region 257 is located between the right side of the gate structure 244 and the left side of the gate structure 242, and the n-doped region 255 is located on the right side of the gate structures 222 and 242. In the P-type well region PW2, the n-doped region 261 is located on the left side of the gate structure 212, the n-doped region 262 is located between the right side of the gate structure 212 and the left side of the gate structure 216, the n-doped region 263 is located between the right side of the gate structure 216 and the left side of the gate structure 226, the n-doped region 264 is located between the right side of the gate structure 226 and the left side of the gate structure 222, and the n-doped region 265 is located on the right side of the gate structure 222. In the P-type well region PW3, the n-doped region 271 is located on the left side of the gate structure 232, the n-doped region 272 is located between the right side of the gate structure 232 and the left side of the gate structure 236, the n-doped region 273 is located between the right side of the gate structure 236 and the left side of the gate structure 246, the n-doped region 274 is located between the right side of the gate structure 246 and the left side of the gate structure 242, and the n-doped region 275 is located on the right side of the gate structure 242. In addition, the left side of the above-mentioned gate structure can be regarded as the first side, and the right side of the gate structure can be regarded as the second side.

[0049] like Figure 2DAs shown, a wiring process is performed to form a plurality of metal contact lines 281 to 296. Among them, the metal contact line 281 is connected to the n-doped region 251 as the bit line BL1. The metal contact line 282 is connected to the n-doped region 255 as the bit line BL2. The metal contact line 283 is connected to the gate structure 214, the metal contact line 284 is connected to the gate structure 224, and the metal contact lines 283 and 284 are connected to each other as the word line WL1. The metal contact line 285 is connected to the gate structure 234, the metal contact line 286 is connected to the gate structure 244, and the metal contact lines 285 and 286 are connected to each other as the word line WL2. The metal contact line 287 is connected to the n-doped region 253, the metal contact line 288 is connected to the P-type well region PW1, and the metal contact lines 287 and 288 are connected to each other as the P-type well region connection (P-well line) PWL1. Metal connection line 289 is connected to n-doped region 263, metal connection line 290 is connected to P-type well region PW2, and metal connection lines 289 and 290 are connected to each other as P-type well region connection line PWL2. Metal connection line 291 is connected to n-doped region 273, metal connection line 292 is connected to P-type well region PW3, and metal connection lines 291 and 292 are connected to each other as P-type well region connection line PWL3. Metal connection line 293 is connected to gate structure 216, metal connection line 294 is connected to gate structure 236, and metal connection lines 293 and 294 are connected to each other as control line CL1. Metal connection line 295 is connected to gate structure 256, metal connection line 296 is connected to gate structure 246, and metal connection lines 295 and 296 are connected to each other as control line CL2.

[0050] Please refer to Figure 2E , which is an equivalent circuit diagram of the MTP non-volatile memory of the first embodiment of the present invention. The MTP non-volatile memory includes four memory cells c11-c22, which together form a 2x2 memory cell array 200, connected to bit lines BL1-BL2, word lines WL1-WL2, control lines CL1-CL2, and P-type well area lines PWL1-PWL3. Since the structure and connection relationship of each memory cell c11-c22 are similar, the following describes the memory cell c11 and Figure 2D The relationship between them is shown in the figure, and other memory cells will not be described in detail.

[0051] The memory cell c11 includes four transistors M1 to M4. Among them, the P-type well region PW1, the n-doped region 251, the n-doped region 252 and the gate structure 212 form the transistor M1. The P-type well region PW1, the n-doped region 252, the n-doped region 253 and the gate structure 214 form the transistor M2. The P-type well region PW2, the n-doped region 261, the n-doped region 262 and the gate structure 212 form the transistor M3. The P-type well region PW2, the n-doped region 262, the n-doped region 263 and the gate structure 216 form the transistor M4. In other words, the transistors M1 and M2 are formed in the P-type well region PW1, and the transistors M3 and M4 are formed in the P-type well region PW2.

[0052] In addition, in the memory cell c11, since the gate structure 212 is in a convex shape, the channel length of the transistor M1 is longer than the channel length of the transistor M3. In other words, under the same channel width, the active area of ​​the transistor M1 is larger than the active area of ​​the transistor M3. Similarly, the other memory cells c12, c21, and c22 also have similar features.

[0053] The transistor M1 is a floating gate transistor. The first drain / source terminal of the transistor M1 is connected to the bit line BL1, the body terminal of the transistor M1 is connected to the P-type well area connection PWL1, and the gate terminal of the transistor M1 is a floating gate Gf. The first drain / source terminal of the transistor M2 is connected to the second drain / source terminal of the transistor M1, the second drain / source terminal of the transistor M2 and the body terminal of the transistor M2 are connected to the P-type well area connection PWL1, and the gate terminal of the transistor M2 is connected to the word line WL1. The first drain / source terminal of the transistor M3 is floating, the body terminal of the transistor M3 is connected to the P-type well area connection PWL2, and the gate terminal of the transistor M3 is connected to the floating gate Gf. The first drain / source terminal of the transistor M4 is connected to the second drain / source terminal of the transistor M2, the second drain / source terminal of the transistor M4 and the body terminal of the transistor M4 are connected to the P-type well area connection PWL2, and the gate terminal of the transistor M4 is connected to the control line CL1.

[0054] Please refer to Figure 3A , which shows a bias table of various operations of the memory cell of the MTP non-volatile memory according to the first embodiment of the present invention. FIG. 3B to FIG. 3E Schematic diagram of bias voltage for various operations of a memory cell. The following description is made by taking the memory cell c11 as an example.

[0055] Please refer to Figure 3A and Figure 3B During the programming operation (PGM), the word line WL1, the bit line BL1, the P-type well area connection PWL1 and the deep N-type well area DNW (not shown) of the memory cell c11 receive the ground voltage Vss. In addition, the P-type well area connection PWL2 receives the negative programming voltage -Vpp, and the control line CL1 receives the negative control voltage -Vctrl1. According to the first embodiment of the present invention, the negative programming voltage -Vpp is less than the negative control voltage -Vctrl1, and the negative control voltage -Vctrl1 is less than the ground voltage Vss. For example, the negative programming voltage -Vpp is -10V, the negative control voltage -Vctrl1 is -5V, and the ground voltage Vss is 0V.

[0056] During the programming operation (PGM), transistors M1 and M2 are turned off. In addition, transistor M3 is turned on, and the negative programming voltage -Vpp is transmitted from the fourth transistor M4 to the second drain / source terminal of the third transistor M3, and a voltage difference of Vpp is generated between the second drain / source terminal and the gate terminal (floating gate Gf) of the third transistor M3. Therefore, the third transistor M3 undergoes FN electron tunneling injection effect (Fowler-Nordheim (FN) electron tunneling injection), and an electron injection path P is generated between the second drain / source terminal of the third transistor M3 and the gate terminal (i.e., floating gate Gf) of the third transistor M3. th1 That is, electrons are injected from the second drain / source terminal of the third transistor M3 through the gate oxide layer of the third transistor M3 into the floating gate Gf, and the programming operation (PGM) is completed.

[0057] Please refer to Figure 3A and Figure 3C When the programming operation is inhibited (PGM inhibit), the word line WL1, bit line BL1, P-type well connection PWL1 and deep N-type well DNW (not shown) of the memory cell c11 receive the ground voltage Vss. In addition, the P-type well connection PWL2 and the control line CL1 receive the negative programming -Vpp.

[0058] When the programming operation is inhibited (PGM inhibit), the transistors M1 and M2 are turned off. In addition, the transistor M4 is turned off so that the second drain / source terminal of the third transistor M3 is floating. Therefore, no electron injection path P can be generated between the second drain / source terminal of the third transistor M3 and the gate terminal of the third transistor M3. th1In other words, the FN electron tunneling injection effect (Fowler-Nordheim (FN) electron tunneling injection) does not occur, and electrons cannot be injected into the floating gate Gf.

[0059] Please refer to Figure 3A and Figure 3D , during the erase operation (ERS), the word line WL1, the bit line BL1 and the P-type well area connection PWL1 of the memory cell c11 receive the ground voltage Vss. In addition, the deep N-type well area DNW (not shown) and the P-type well area connection PWL2 receive the erase voltage Vee, and the control line CL1 receives the control voltage Vctrl2. According to the first embodiment of the present invention, the erase voltage Vee is greater than the control voltage Vctrl2, and the control voltage Vctrl2 is greater than the ground voltage Vss. For example, the erase voltage Vee is 10V, the control voltage Vctrl2 is 5V, and the ground voltage Vss is 0V.

[0060] During the erase operation (ERS), transistors M1 and M2 are turned off. In addition, transistor M3 is turned off, and the erase voltage Vee is transmitted from the P-type well connection PWL2 to the body terminal of the third transistor M3, and a voltage difference of Vee is generated between the body terminal and the gate terminal (floating gate Gf) of the third transistor M3. Therefore, the third transistor M3 undergoes FN electron tunneling ejection effect (Fowler-Nordheim (FN) electron tunneling ejection), and an electron exit path P is generated between the body terminal of the third transistor M3 and the gate terminal (i.e., floating gate Gf) of the third transistor M3. th2 That is, the electrons are withdrawn from the floating gate Gf through the gate oxide layer of the third transistor M3 to the body terminal of the third transistor M3, and the erase operation (ERS) is completed.

[0061] Please refer to Figure 3A and Figure 3E In the read operation (READ), the word line WL1 and the bit line BL1 of the memory cell c11 receive the read voltage Vr. In addition, the P-type well area connection line PWL1, the P-type well area connection line PWL2, the control line CL1 and the deep N-type well area DNW (not shown) receive the ground voltage Vss. According to the first embodiment of the present invention, the read voltage Vr is greater than the ground voltage Vss. For example, the read voltage Vr is 0.7V and the ground voltage Vss is 0V.

[0062] During the read operation (READ), transistors M3 and M4 are turned off. In addition, transistor M2 is turned on and generates a read current Ir, which flows from the bit line BL1 through transistor M1 to transistor M2. In other words, during the read operation, the storage state of the memory cell c11 can be determined based on the current on the bit line BL. For example, a sense amplifier (not shown) is connected to the bit line BL1. When electrons are stored on the floating gate Gf, the read current Ir is small, and the sense amplifier determines that the memory cell c11 is in the first storage state. On the contrary, when no electrons are stored on the floating gate Gf, the read current Ir is large, and the sense amplifier determines that the memory cell c11 is in the second storage state.

[0063] From the above description, it can be seen that the memory cell c11 of the first embodiment of the present invention utilizes the electron injection path P in the transistor M3 in both the programming operation (PGM) and the erasing operation (ERS). th1 With the electron exit path P th2 Electrons are injected into and removed from the floating gate Gf. That is, during the programming (PGM) operation and the erasing (ERS) operation, electrons tunnel through the gate oxide layer of the transistor M3. That is, the present invention uses a bidirectional path to inject and remove electrons respectively, so that the data retention reliability of the memory cell c11 is higher.

[0064] Furthermore, in the memory cell c11 of the first embodiment of the present invention, electrons do not tunnel through the gate oxide layer of the transistor M1 (floating gate transistor) during the programming operation (PGM) and the erasing operation (ERS). In other words, the gate oxide layer of the transistor M1 (floating gate transistor) will not be damaged, and the transistor M1 only generates a read current Ir during the read operation (READ). Therefore, the endurance reliability of the transistor M1 (floating gate transistor) can be greatly improved.

[0065] In addition, during the operation of the memory cell c11 in the first embodiment, the voltage stress on the transistor M2 is very low, about 0.7 V. That is, the transistor M2 can be a core device transistor with a relatively low operating voltage. Therefore, the read voltage of the memory cell c11 can be reduced.

[0066] use Figure 3A The bias table can be used to perform various operations on the memory cell array of the MTP non-volatile memory. FIG. 4A to FIG. 4C , which is a schematic diagram of bias voltage when the memory cell array of the first embodiment performs various operations.

[0067] like Figure 4A As shown, word line WL1, word line WL2, bit line BL1, bit line BL2, P-type well area connection PWL1 and deep N-type well area DNW (not shown) receive ground voltage Vss. In addition, P-type well area connection PWL2 and control line CL2 receive negative programming voltage -Vpp, and P-type well area connection PWL3 and control line CL1 receive negative control voltage -Vctrl1.

[0068] In the memory cell array 200, a row of memory cells c21 and c22 connected to the P-type well line PWL3 is an unselected row. That is, the memory cells c21 and c22 in the unselected row will not be programmed. Furthermore, a row of memory cells c11 and c12 connected to the P-type well line PWL2 is a selected row. The memory cell c11 in the selected row is a selected memory cell, and the other memory cells c22 are unselected memory cells. The selected memory cell c11 will perform a programming operation (PGM), and the unselected memory cell c12 will perform a programming inhibition operation (PGMinhibit). In addition, the voltage (-Vctrl1) applied to the P-type well line PWL3 is between the voltage (Vss) applied to the P-type well line PWL1 and the voltage (-Vpp) applied to the P-type well line PWL2 to achieve the operation of the selected row and the unselected row.

[0069] like Figure 4B As shown, word line WL1, word line WL2, bit line BL1, bit line BL2, P-type well area connection PWL1 and P-type well area connection PWL3 receive ground voltage Vss. In addition, P-type well area connection PWL2 and deep N-type well area DNW (not shown) receive erase voltage Vee. Control line CL1 and control line CL2 receive control voltage Vctrl2.

[0070] In the memory cell array 200, a row of memory cells c21 and c22 connected to the P-type well line PWL3 is an unselected row. That is, the memory cells c21 and c22 in the unselected row will not be erased. Furthermore, a row of memory cells c11 and c12 connected to the P-type well line PWL2 is a selected row. All memory cells c11 and c12 in the selected row will undergo an erase operation (ERS).

[0071] like Figure 4CAs shown, word line WL2, bit line BL2, P-type well line PWL1, P-type well line PWL2, P-type well line PWL3, control line CL1, control line CL2 and deep N-type well DNW (not shown) receive ground voltage Vss. In addition, word line WL1 and bit line BL1 receive read voltage Vr.

[0072] In the memory cell array 200, a row of memory cells c21 and c22 connected by word line WL2 is an unselected row. That is, the memory cells c21 and c22 in the unselected row will not be read. Furthermore, a row of memory cells c11 and c12 connected by word line WL1 is a selected row. The memory cell c11 in the selected row is a selected memory cell, and the other memory cells c12 are unselected memory cells. The selected memory cell c11 will perform a read operation (READ), and the unselected memory cell c12 will not perform a read operation.

[0073] Please refer to Figure 5A and Figure 5B , which depicts a top view and an equivalent circuit diagram of the MTP non-volatile memory of the second embodiment of the present invention. The MTP non-volatile memory includes 4 memory cells, forming a 2x2 memory cell array. Of course, the MTP non-volatile memory of the present invention is not limited to a 2x2 memory cell array, and can also form an mxn memory cell array, where m and n are positive integers.

[0074] like Figure 5A As shown, the memory cell array of the second embodiment is modified Figure 2D The structure of n-doped regions 261, 265, 271, 275. That is, compared to Figure 2D The first embodiment of the invention is different in that Figure 5A The second embodiment adds gate structures 610, 620, 630, 640, n-doped regions 612, 614, 622, 624, 632, 634, 642, 644, and metal connecting lines 616, 618, 626, 628, 636, 638, 646, 648. Only the structures of the differences are described below, and the rest are not repeated.

[0075] like Figure 5AAs shown, the gate structures 610 and 620 are covered in the P-type well region PW2, and the gate structures 630 and 640 are covered in the P-type well region PW3. In the P-type well region PW2, the n-doped region 612 is located on the left side of the gate structure 610, the n-doped region 614 is located between the right side of the gate structure 610 and the left side of the gate structure 212, the n-doped region 624 is located between the right side of the gate structure 222 and the left side of the gate structure 620, and the n-doped region 622 is located on the right side of the gate structure 620. In the P-type well region PW3, the n-doped region 632 is located on the left side of the gate structure 630, the n-doped region 634 is located between the right side of the gate structure 630 and the left side of the gate structure 232, the n-doped region 644 is located between the right side of the gate structure 242 and the left side of the gate structure 640, and the n-doped region 642 is located on the right side of the gate structure 640.

[0076] Furthermore, the metal connection line 618 is connected to the n-doped region 612, the metal connection line 628 is connected to the n-doped region 622, and the metal connection lines 618 and 628 are connected to each other as an inhibit line IL1. The metal connection line 638 is connected to the n-doped region 632, the metal connection line 648 is connected to the n-doped region 642, and the metal connection lines 638 and 648 are connected to each other as an inhibit line IL2. The metal connection line 616 is connected to the gate structure 610, the metal connection line 636 is connected to the gate structure 630, and the metal connection lines 616 and 636 are connected to each other as a select line SeL1. The metal connection line 626 is connected to the gate structure 620, the metal connection line 646 is connected to the gate structure 640, and the metal connection lines 626 and 646 are connected to each other as a select line SeL2.

[0077] like Figure 5B As shown, the MTP non-volatile memory includes 4 memory cells c11-c22, forming a 2x2 memory cell array, connected to bit lines BL1-BL2, word lines WL1-WL2, selection lines SeL1-SeL2, inhibition lines IL1-IL2, control lines CL1-CL2, and P-type well area lines PWL1-PWL3. Since the structure and connection relationship of each memory cell c11-c22 are similar, only the memory cell c11 is introduced below, and the others are not repeated.

[0078] The memory cell c11 includes five transistors M1 to M5. Among them, the P-type well region PW1, the n-doped region 251, the n-doped region 252 and the gate structure 212 form the transistor M1. The P-type well region PW1, the n-doped region 252, the n-doped region 253 and the gate structure 214 form the transistor M2. The P-type well region PW2, the n-doped region 614, the n-doped region 262 and the gate structure 212 form the transistor M3. The P-type well region PW2, the n-doped region 262, the n-doped region 263 and the gate structure 216 form the transistor M4. The P-type well region PW2, the n-doped region 612, the n-doped region 614 and the gate structure 610 form the transistor M5. In other words, the transistors M1 and M2 are formed in the P-type well region PW1, and the transistors M3, M4 and M5 are formed in the P-type well region PW2.

[0079] The transistor M1 is a floating gate transistor, the first drain / source terminal of the transistor M1 is connected to the bit line BL1, the body terminal of the transistor M1 is connected to the P-type well area connection PWL1, and the gate terminal of the transistor M1 is a floating gate Gf. The first drain / source terminal of the transistor M2 is connected to the second drain / source terminal of the transistor M1, the second drain / source terminal of the transistor M2 and the body terminal of the transistor M2 are connected to the P-type well area connection PWL1, and the gate terminal of the transistor M2 is connected to the word line WL1. The first drain / source terminal of the transistor M5 is connected to the inhibition line IL1, the body terminal of the transistor M5 is connected to the P-type well area connection PWL2, and the gate terminal of the transistor M5 is connected to the selection line SeL1. The first drain / source terminal of the transistor M3 is connected to the second drain / source terminal of the transistor M5, the body terminal of the transistor M3 is connected to the P-type well area connection PWL2, and the gate terminal of the transistor M3 is connected to the floating gate Gf. The first drain / source terminal of transistor M4 is connected to the second drain / source terminal of transistor M3, the second drain / source terminal of transistor M4 and the body terminal of transistor M4 are connected to P-type well connection line PWL2, and the gate terminal of transistor M4 is connected to control line CL1.

[0080] Please refer to Fig. 6A , which shows a bias table of various operations of the memory cell of the MTP non-volatile memory according to the second embodiment of the present invention. FIG. 6B to FIG. 6E Schematic diagram of bias voltage for various operations of a memory cell. The following description is made by taking the memory cell c11 as an example.

[0081] Please refer to Fig. 6A and Figure 6BDuring the programming operation (PGM), the word line WL1, the bit line BL1, the P-type well area connection line PWL1 and the deep N-type well area DNW (not shown) of the memory cell c11 receive the ground voltage Vss. In addition, the P-type well area connection line PWL2 and the selection line SeL1 receive the negative programming voltage -Vpp, and the control line CL1 and the inhibition line IL1 receive the negative control voltage -Vctrl1. According to the first embodiment of the present invention, the negative programming voltage -Vpp is less than the negative control voltage -Vctrl1, and the negative control voltage -Vctrl1 is less than the ground voltage Vss. For example, the negative programming voltage -Vpp is -10V, the negative control voltage -Vctrl1 is -5V, and the ground voltage Vss is 0V.

[0082] During the programming operation (PGM), transistors M1 and M2 are turned off. In addition, transistor M3 is turned on, and transistor M5 is turned off. The negative programming voltage -Vpp is transmitted from the fourth transistor M4 to the second drain / source terminal of the third transistor M3, and a voltage difference of Vpp is generated between the second drain / source terminal and the gate terminal (floating gate Gf) of the third transistor M3. Therefore, the third transistor M3 undergoes FN electron tunneling injection effect (Fowler-Nordheim (FN) electron tunneling injection), and an electron injection path P is generated between the second drain / source terminal of the third transistor M3 and the gate terminal (i.e., floating gate Gf) of the third transistor M3. th1 That is, electrons are injected from the second drain / source terminal of the third transistor M3 through the gate oxide layer of the third transistor M3 into the floating gate Gf, and the programming operation (PGM) is completed.

[0083] Please refer to Fig. 6A and Figure 6C When the program operation is inhibited (PGM inhibit), the word line WL1, the bit line BL1, the P-type well area connection line PWL1 and the deep N-type well area DNW (not shown) of the memory cell c11 receive the ground voltage Vss. In addition, the P-type well area connection line PWL2 and the control line CL1 receive the negative programming -Vpp, and the inhibition line IL1 and the selection line SeL1 receive the negative control voltage -Vctrl1.

[0084] When the programming operation is inhibited (PGM inhibit), the transistors M1 and M2 are turned off. In addition, the transistor M3 is turned off, and the transistor M5 is turned on. The negative control voltage -Vctrl1 is transmitted from the fifth transistor M5 to the first drain / source terminal of the third transistor M3, and a voltage difference of Vctrl1 is generated between the first drain / source terminal and the gate terminal (floating gate Gf) of the third transistor M3. Since the voltage Vctrl1 between the first drain / source terminal and the gate terminal (floating gate Gf) of the third transistor M3 is too low, the electron injection path P cannot be generated between the first drain / source terminal of the third transistor M3 and the gate terminal of the third transistor M3. th1 In other words, Fowler-Nordheim (FN) electron tunneling injection does not occur, and electrons cannot be injected into the floating gate Gf.

[0085] Please refer to Fig. 6A and Fig.6D , during the erase operation (ERS), the word line WL1, the bit line BL1 and the P-type well area connection line PWL1 of the memory cell c11 receive the ground voltage Vss. In addition, the deep N-type well area DNW (not shown), the P-type well area connection line PWL2 and the inhibition line IL1 receive the erase voltage Vee, and the control line CL1 and the selection line SeL1 receive the control voltage Vctrl2. According to the first embodiment of the present invention, the erase voltage Vee is greater than the control voltage Vctrl2, and the control voltage Vctrl2 is greater than the ground voltage Vss. For example, the erase voltage Vee is 10V, the control voltage Vctrl2 is 5V, and the ground voltage Vss is 0V.

[0086] During the erase operation (ERS), transistors M1 and M2 are turned off. In addition, transistors M3 and M5 are turned off, and the erase voltage Vee is transmitted from the P-type well region connection PWL2 to the body terminal of the third transistor M3, and a voltage difference of Vee is generated between the body terminal and the gate terminal (floating gate Gf) of the third transistor M3. Therefore, the third transistor M3 undergoes FN electron tunneling ejection effect (Fowler-Nordheim (FN) electron tunneling ejection), and an electron exit path P is generated between the body terminal of the third transistor M3 and the gate terminal (i.e., floating gate Gf) of the third transistor M3. th2 That is, the electrons are withdrawn from the floating gate Gf through the gate oxide layer of the third transistor M3 to the body terminal of the third transistor M3, and the erase operation (ERS) is completed.

[0087] Please refer to Fig. 6A and Fig. 6E In the read operation (READ), the word line WL1 and the bit line BL1 of the memory cell c11 receive the read voltage Vr. In addition, the P-type well area line PWL1, the P-type well area line PWL2, the control line CL1, the selection line SeL1, the inhibition line IL1 and the deep N-type well area DNW (not shown) receive the ground voltage Vss. According to the first embodiment of the present invention, the read voltage Vr is greater than the ground voltage Vss. For example, the read voltage Vr is 0.7V and the ground voltage Vss is 0V.

[0088] During the read operation (READ), transistors M3, M4, and M5 are turned off. In addition, transistor M2 is turned on and generates a read current Ir, which flows from the bit line BL1 through transistor M1 to transistor M2. In other words, during the read operation, the storage state of the memory cell c11 can be determined based on the current on the bit line BL. For example, a sense amplifier (not shown) is connected to the bit line BL1. When electrons are stored on the floating gate Gf, the read current Ir is small, and the sense amplifier determines that the memory cell c11 is in the first storage state. On the contrary, when no electrons are stored on the floating gate Gf, the read current Ir is large, and the sense amplifier determines that the memory cell c11 is in the second storage state.

[0089] From the above description, it can be seen that the memory cell c11 of the second embodiment of the present invention utilizes the electron injection path P in the transistor M3 in both the programming operation (PGM) and the erasing operation (ERS). th1 With the electron exit path P th2 Electrons are injected into and removed from the floating gate Gf. That is, during the programming (PGM) operation and the erasing (ERS) operation, electrons tunnel through the gate oxide layer of the transistor M3. That is, the present invention uses a bidirectional path to inject and remove electrons respectively, so that the data retention reliability of the memory cell c11 is higher.

[0090] Furthermore, in the memory cell c11 of the second embodiment of the present invention, electrons do not tunnel through the gate oxide layer of the transistor M1 (floating gate transistor) during the programming operation (PGM) and the erasing operation (ERS). In other words, the gate oxide layer of the transistor M1 (floating gate transistor) will not be damaged, and the transistor M1 only generates a read current Ir during the read operation (READ). Therefore, the endurance reliability of the transistor M1 (floating gate transistor) can be greatly improved.

[0091] In addition, during the operation of the memory cell c11 of the second embodiment, the voltage stress on the transistor M2 is very low, about 0.7 V. That is, the transistor M2 can be a core device transistor with a relatively low operating voltage. Therefore, the read voltage of the memory cell c11 can be reduced.

[0092] Furthermore, the first embodiment and the second embodiment of the present invention do not limit the actual voltage values ​​of the programming voltage Vpp, the control voltage Vctrl1, the erase voltage Vee, and the control voltage Vctrl2. Technicians in this field can modify the voltage values ​​of the programming voltage Vpp, the control voltage Vctrl1, the erase voltage Vee, and the control voltage Vctrl2 according to actual needs to achieve a programming operation (PGM), a programming inhibit operation (PGM inhibit), an erase operation (ERS), and a read operation (READ).

[0093] Similarly, using Fig. 6A The bias table can perform various operations on the memory cell array 600 of the MTP nonvolatile memory. FIG. 7A to FIG. 7C , which is a schematic diagram of bias voltage when the memory cell array of the second embodiment performs various operations.

[0094] like Fig. 7A As shown, word line WL1, word line WL2, bit line BL1, bit line BL2, P-type well area connection line PWL1 and deep N-type well area DNW (not shown) receive ground voltage Vss. In addition, P-type well area connection line PWL2, control line CL2 and selection line SeL1 receive negative programming voltage -Vpp, and P-type well area connection line PWL3, control line CL1, selection line SeL2, inhibition line IL1 and inhibition line IL2 receive negative control voltage -Vctrl1.

[0095] In the memory cell array 600, a row of memory cells c21 and c22 connected to the P-type well line PWL3 is an unselected row. That is, the memory cells c21 and c22 in the unselected row will not be programmed. Furthermore, a row of memory cells c11 and c12 connected to the P-type well line PWL2 is a selected row. The memory cell c11 in the selected row is a selected memory cell, and the other memory cells c12 are unselected memory cells. The selected memory cell c11 will perform a programming operation (PGM), and the unselected memory cell c12 will perform a programming inhibition operation (PGMinhibit). In addition, the voltage (-Vctrl1) applied to the P-type well line PWL3 is between the voltage (Vss) applied to the P-type well line PWL1 and the voltage (-Vpp) applied to the P-type well line PWL2 to achieve the operation of the selected row and the unselected row.

[0096] like Figure 7B As shown, word line WL1, word line WL2, bit line BL1, bit line BL2, isolation line IL2, P-type well area connection line PWL1 and P-type well area connection line PWL3 receive ground voltage Vss. In addition, P-type well area connection line PWL2, isolation line IL1 and deep N-type well area DNW (not shown) receive erase voltage Vee. Select line SeL1, select line SeL2, control line CL1 and control line CL2 receive control voltage Vctrl2.

[0097] In the memory cell array 600, a row of memory cells c21 and c22 connected to the P-type well line PWL3 and the isolation line IL2 is an unselected row. That is, the memory cells c21 and c22 in the unselected row will not be erased. Furthermore, a row of memory cells c11 and c12 connected to the P-type well line PWL2 and the isolation line IL1 is a selected row. All memory cells c11 and c12 in the selected row will undergo an erase operation (ERS).

[0098] like Figure 7C As shown, the word line WL2, the bit line BL2, the P-type well area connection line PWL1, the P-type well area connection line PWL2, the P-type well area connection line PWL3, the control line CL1, the control line CL2, the isolation line IL1, the isolation line IL2, the selection line SeL1, the selection line SeL2, and the deep N-type well area DNW (not shown) receive the ground voltage Vss. In addition, the word line WL1 and the bit line BL1 receive the read voltage Vr.

[0099] In the memory cell array 600, a row of memory cells c21 and c22 connected by word line WL2 is an unselected row. That is, the memory cells c21 and c22 in the unselected row will not be read. Furthermore, a row of memory cells c11 and c12 connected by word line WL1 is a selected row. The memory cell c11 in the selected row is a selected memory cell, and the other memory cells c12 are unselected memory cells. The selected memory cell c11 will perform a read operation (READ), and the unselected memory cell c12 will not perform a read operation.

[0100] In addition, the memory cell of the MTP non-volatile memory of the present invention is described by taking an n-type transistor as an example, but the present invention is certainly not limited thereto, and those skilled in the art can modify it to a p-type transistor and implement the present invention.

[0101] From the above description, it can be seen that the present invention provides a memory cell of a sub-programmable non-volatile memory and a memory cell array thereof. During the programming operation (PGM) and the erasing operation (ERS), electrons tunnel through the same gate end oxide layer. In other words, the present invention uses a bidirectional path to inject and withdraw electrons respectively, so that the memory cell has a higher data retention reliability.

[0102] In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A memory cell array of a multi-programmable non-volatile memory, the memory cell array comprising a first memory cell, the first memory cell comprising: Well Area 1; Well Area 2; A first gate structure covering the first well region and the second well region; A second gate structure covering the first well region; A third gate structure covering the second well region; A first doped region, located in the first well region and on a first side of the first gate structure; A second doped region is located in the first well region between the second side of the first gate structure and the first side of the second gate structure; A third doped region, located in the first well region and on the second side of the second gate structure; a fourth doped region located in the second well region and on the first side of the first gate structure; a fifth doped region located in the second well region and between the second side of the first gate structure and the first side of the third gate structure; a sixth doped region, located in the second well region and on the second side of the third gate structure; A first metal connection line connected to the first doped region; A second metal connection line connected to the second gate structure; A third metal connection line connected to the third gate structure; A fourth metal connection line connected to the first well region; A fifth metal connection line connected to the third doped region, and the fifth metal connection line is connected to the fourth metal connection line; A sixth metal connection line connected to the second well region; as well as A seventh metal connection line connected to the sixth doped region, and the seventh metal connection line is connected to the sixth metal connection line; wherein the first well region, the first doped region, the second doped region and the first gate structure form a first transistor; the first well region, the second doped region, the third doped region and the second gate structure form a second transistor; the second well region, the fourth doped region, the fifth doped region and the first gate structure form a third transistor and the gate terminal of the third transistor is connected to the floating gate; and the second well region, the fifth doped region, the sixth doped region and the third gate structure form a fourth transistor; wherein the channel length of the first transistor is longer than the channel length of the third transistor; In the programming operation, electrons are injected into the floating gate through the gate oxide layer of the third transistor; and in the erasing operation, electrons are withdrawn from the floating gate through the gate oxide layer of the third transistor to the body terminal of the third transistor. 2 . The memory cell array as claimed in claim 1 , wherein an active area of ​​the first transistor is larger than an active area of ​​the third transistor.

3. The memory cell array as claimed in claim 1, wherein the first memory cell comprises: The first transistor has the floating gate, the first drain / source terminal, the second drain / source terminal and the body terminal; wherein the first drain / source terminal of the first transistor is connected to the first bit line, and the body terminal of the first transistor is connected to the first well region connection; The second transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the second transistor is connected to the second drain / source terminal of the first transistor, the body terminal of the second transistor is connected to the first well area connection, the second drain / source terminal of the second transistor is connected to the first well area connection, and the gate terminal of the second transistor is connected to the first word line; The third transistor has the gate terminal, the first drain / source terminal, the second drain / source terminal and the body terminal; wherein the body terminal of the third transistor is connected to the second well region connection, and the gate terminal of the third transistor is connected to the floating gate of the first transistor; and The fourth transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the fourth transistor is connected to the second drain / source terminal of the third transistor, the body terminal of the fourth transistor is connected to the second well area connection, the second drain / source terminal of the fourth transistor is connected to the second well area connection, and the gate terminal of the fourth transistor is connected to the first control line.

4. The memory cell array according to claim 3, further comprising a second memory cell, the second memory cell comprising: A fifth transistor having a floating gate, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the fifth transistor is connected to the first bit line, and the body terminal of the fifth transistor is connected to the first well region connection; a sixth transistor, having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the sixth transistor is connected to the second drain / source terminal of the fifth transistor, the body terminal of the sixth transistor is connected to the first well connection, the second drain / source terminal of the sixth transistor is connected to the first well connection, and the gate terminal of the sixth transistor is connected to the second word line; a seventh transistor having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the body terminal of the seventh transistor is connected to the third well region connection, and the gate terminal of the seventh transistor is connected to the floating gate of the fifth transistor; and An eighth transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the eighth transistor is connected to the second drain / source terminal of the seventh transistor, the body terminal of the eighth transistor is connected to the third well area connection, the second drain / source terminal of the eighth transistor is connected to the third well area connection, and the gate terminal of the eighth transistor is connected to the first control line.

5. The memory cell array of claim 4, wherein the first memory cell is in a selected row and the second memory cell is in a non-selected row; wherein during the programming operation, a voltage applied to the third well area connection is between a voltage applied to the first well area connection and a voltage applied to the second well area connection.

6. The memory cell array according to claim 3, further comprising a second memory cell, the second memory cell comprising: a fifth transistor having a floating gate, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the fifth transistor is connected to the second bit line, and the body terminal of the fifth transistor is connected to the first well region connection; a sixth transistor, having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the sixth transistor is connected to the second drain / source terminal of the fifth transistor, the body terminal of the sixth transistor is connected to the first well connection, the second drain / source terminal of the sixth transistor is connected to the first well connection, and the gate terminal of the sixth transistor is connected to the first word line; a seventh transistor having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the body terminal of the seventh transistor is connected to the second well region connection, and the gate terminal of the seventh transistor is connected to the floating gate of the fifth transistor; and An eighth transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the eighth transistor is connected to the second drain / source terminal of the seventh transistor, the body terminal of the eighth transistor is connected to the second well area connection, the second drain / source terminal of the eighth transistor is connected to the second well area connection, and the gate terminal of the eighth transistor is connected to the second control line.

7. The memory cell array as claimed in claim 3, wherein during the programming operation, the first well area connection, the first word line, and the first bit line receive a ground voltage, the second well area connection receives a negative programming voltage, the first control line receives a negative control voltage, a plurality of electrons penetrate the gate oxide layer of the third transistor and are injected into the floating gate of the first transistor, the negative programming voltage is less than the negative control voltage, and the negative control voltage is less than the ground voltage.

8. The memory cell array of claim 3, wherein during a program inhibit operation, the first well connection, the first word line, and the first bit line receive a ground voltage, and the second well connection and the first control line receive a negative programming voltage, the negative programming voltage being less than the ground voltage.

9. The memory cell array as claimed in claim 3, wherein during the erase operation, the first well connection, the first word line, and the first bit line receive a ground voltage, the second well connection receives an erase voltage, the first control line receives a control voltage, a plurality of electrons penetrate the gate oxide layer of the third transistor and exit the floating gate of the first transistor, the erase voltage is greater than the control voltage, and the control voltage is greater than the ground voltage.

10. The memory cell array as claimed in claim 3, wherein during a read operation, the first well area connection, the second well area connection and the first control line receive a ground voltage, the first word line and the first bit line receive a read voltage, the second transistor is turned on and generates a read current flowing from the first bit line through the first transistor to the second transistor, and the read voltage is greater than the ground voltage.

11. A memory cell array of a multi-programmable non-volatile memory, the memory cell array comprising a first memory cell, the first memory cell comprising: Well Area 1; Well Area 2; A first gate structure covering the first well region and the second well region; A second gate structure covering the first well region; A third gate structure covering the second well region; A fourth gate structure covering the second well region; A first doped region, located in the first well region and on a first side of the first gate structure; A second doped region is located in the first well region between the second side of the first gate structure and the first side of the second gate structure; A third doped region, located in the first well region and on the second side of the second gate structure; a fourth doped region, located in the second well region and on a first side of the fourth gate structure; a fifth doped region located in the second well region and between the second side of the fourth gate structure and the first side of the first gate structure; a sixth doped region, located in the second well region, between the second side of the first gate structure and the first side of the third gate structure; a seventh doped region, located in the second well region and on the second side of the third gate structure; A first metal connection line connected to the first doped region; A second metal connection line connected to the second gate structure; A third metal connection line connected to the third gate structure; A fourth metal connection line connected to the first well region; A fifth metal connection line connected to the third doped region, and the fifth metal connection line is connected to the fourth metal connection line; A sixth metal connection line connected to the second well region; a seventh metal connection line connected to the seventh doped region; an eighth metal connection line connected to the fourth doped region, and the eighth metal connection line is connected to the sixth metal connection line; as well as a ninth metal connection line connected to the fourth gate structure; wherein the first well region, the first doped region, the second doped region and the first gate structure form a first transistor; the first well region, the second doped region, the third doped region and the second gate structure form a second transistor; the second well region, the fifth doped region, the sixth doped region and the first gate structure form a third transistor and the gate terminal of the third transistor is connected to the floating gate; the second well region, the fourth doped region, the fifth doped region and the third gate structure form a fourth transistor; and the second well region, the sixth doped region, the seventh doped region and the fourth gate structure form a fifth transistor; wherein the channel length of the first transistor is longer than the channel length of the third transistor; In the programming operation, electrons are injected into the floating gate through the gate oxide layer of the third transistor; and in the erasing operation, electrons are withdrawn from the floating gate through the gate oxide layer of the third transistor to the body terminal of the third transistor. 12 . The memory cell array as claimed in claim 11 , wherein an active area of ​​the first transistor is larger than an active area of ​​the third transistor.

13. The memory cell array as claimed in claim 11, wherein the memory cell comprises: The first transistor has the floating gate, the first drain / source terminal, the second drain / source terminal and the body terminal; wherein the first drain / source terminal of the first transistor is connected to the first bit line, and the body terminal of the first transistor is connected to the first well region connection; The second transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the second transistor is connected to the second drain / source terminal of the first transistor, the body terminal of the second transistor is connected to the first well area connection, the second drain / source terminal of the second transistor is connected to the first well area connection, and the gate terminal of the second transistor is connected to the first word line; The third transistor has the gate terminal, the first drain / source terminal, the second drain / source terminal and the body terminal; wherein the body terminal of the third transistor is connected to the second well region connection, and the gate terminal of the third transistor is connected to the floating gate of the first transistor; and The fourth transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the fourth transistor is connected to the second drain / source terminal of the third transistor, the body terminal of the fourth transistor is connected to the second well region connection, the second drain / source terminal of the fourth transistor is connected to the second well region connection, and the gate terminal of the fourth transistor is connected to the first control line; and The fifth transistor has a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the fifth transistor is connected to the first inhibition line, the body terminal of the fifth transistor is connected to the second well area connection line, the second drain / source terminal of the fifth transistor is connected to the first drain / source terminal of the third transistor, and the gate terminal of the fifth transistor is connected to the first selection line.

14. The memory cell array according to claim 13, further comprising a second memory cell, the second memory cell comprising: a sixth transistor having a floating gate, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the sixth transistor is connected to the first bit line, and the body terminal of the sixth transistor is connected to the first well region connection; a seventh transistor, having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the seventh transistor is connected to the second drain / source terminal of the sixth transistor, the body terminal of the seventh transistor is connected to the first well connection, the second drain / source terminal of the seventh transistor is connected to the first well connection, and the gate terminal of the seventh transistor is connected to the second word line; an eighth transistor having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the body terminal of the eighth transistor is connected to the third well region connection, and the gate terminal of the eighth transistor is connected to the floating gate of the sixth transistor; a ninth transistor, having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the ninth transistor is connected to the second drain / source terminal of the eighth transistor, the body terminal of the ninth transistor is connected to the third well region connection, the second drain / source terminal of the ninth transistor is connected to the third well region connection, and the gate terminal of the ninth transistor is connected to the first control line; A tenth transistor having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the tenth transistor is connected to the second inhibition line, the body terminal of the tenth transistor is connected to the third well area connection line, the second drain / source terminal of the tenth transistor is connected to the first drain / source terminal of the eighth transistor, and the gate terminal of the tenth transistor is connected to the first selection line.

15. The memory cell array of claim 14, wherein the first memory cell is in a selected row and the second memory cell is in a non-selected row; wherein during the programming operation, a voltage applied to the third well area connection is between a voltage applied to the first well area connection and a voltage applied to the second well area connection.

16. The memory cell array according to claim 13, further comprising a second memory cell, the second memory cell comprising: a sixth transistor having a floating gate, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the sixth transistor is connected to the second bit line, and the body terminal of the sixth transistor is connected to the first well region connection; a seventh transistor, having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the seventh transistor is connected to the second drain / source terminal of the sixth transistor, the body terminal of the seventh transistor is connected to the first well region connection, the second drain / source terminal of the seventh transistor is connected to the first well region connection, and the gate terminal of the seventh transistor is connected to the first word line; an eighth transistor having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the body terminal of the eighth transistor is connected to the second well region connection, and the gate terminal of the eighth transistor is connected to the floating gate of the sixth transistor; a ninth transistor, having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the ninth transistor is connected to the second drain / source terminal of the eighth transistor, the body terminal of the ninth transistor is connected to the second well connection, the second drain / source terminal of the ninth transistor is connected to the second well connection, and the gate terminal of the ninth transistor is connected to the second control line; and A tenth transistor having a gate terminal, a first drain / source terminal, a second drain / source terminal and a body terminal; wherein the first drain / source terminal of the tenth transistor is connected to the first inhibition line, the body terminal of the tenth transistor is connected to the second well area connection line, the second drain / source terminal of the tenth transistor is connected to the first drain / source terminal of the eighth transistor, and the gate terminal of the tenth transistor is connected to the second selection line.

17. The memory cell array as claimed in claim 13, wherein during the programming operation, the first well connection, the first word line, and the first bit line receive a ground voltage, the second well connection and the first selection line receive a negative programming voltage, the first control line and the first inhibition line receive a negative control voltage, a plurality of electrons penetrate the gate oxide layer of the third transistor and are injected into the floating gate of the first transistor, the negative programming voltage is less than the negative control voltage, and the negative control voltage is less than the ground voltage.

18. The memory cell array of claim 13, wherein during a program inhibit operation, the first well connection, the first word line, and the first bit line receive a ground voltage, the second well connection and the first control line receive a negative programming voltage, the first selection line and the first inhibit line receive a negative control voltage, the negative programming voltage is less than the negative control voltage, and the negative control voltage is less than the ground voltage.

19. The memory cell array as claimed in claim 13, wherein during the erase operation, the first well connection, the first word line, and the first bit line receive a ground voltage, the second well connection and the first inhibit line receive an erase voltage, the first control line and the first select line receive a control voltage, a plurality of electrons penetrate the gate oxide layer of the third transistor and exit the floating gate of the first transistor, the erase voltage is greater than the control voltage, and the control voltage is greater than the ground voltage.

20. The memory cell array of claim 13, wherein during a read operation, the first well connection, the second well connection, the first control line, the first inhibit line, and the first select line receive a ground voltage, the first word line and the first bit line receive a read voltage, the second transistor is turned on and generates a read current flowing from the first bit line through the first transistor to the second transistor, and the read voltage is greater than the ground voltage.

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