Semiconductor memory device, memory system, and control method of semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of speeding up an operation, a memory system, and a control method of the semiconductor storage device. The semiconductor storage device of the embodiments includes a first selection transistor, a first selection gate line connected to a gate of the first selection transistor, a first wiring connected to the first selection transistor, a second selection transistor, a second selection gate line connected to a gate of the second selection transistor, a second wiring connected to the second selection transistor, a first and a second storage cell transistor connected between the first selection transistor and the second selection transistor, a first word line connected to the first storage cell transistor, and a second word line connected to the second storage cell transistor. A data write operation of the semiconductor storage device has a program operation and a verify operation, in the write operation to the first storage cell transistor, after the verify operation is performed, during a period in which the second selection transistor is in an on state, a voltage of the first word line is changed from a first voltage to a second voltage, a voltage of the second word line is changed from a third voltage applied in the verify operation to a fourth voltage, after the voltage of the first word line is changed to the second voltage and the voltage of the second word line is changed to the fourth voltage, a voltage of the second selection gate line is changed from a fifth voltage to a sixth voltage that makes the second selection transistor in an off state.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2021-24957 (Filing date: February 19, 2021). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor storage device, a memory system, and a control method of a semiconductor storage device. BACKGROUND

[0004] As a semiconductor storage device, a NAND (Not AND) type flash memory is known. SUMMARY

[0005] Embodiments provide a semiconductor storage device, a memory system, and a control method of a semiconductor storage device that can speed up an operation.

[0006] The semiconductor storage device of the embodiment includes: a first selection transistor; a first selection gate line connected to a gate of the first selection transistor; a first wiring connected to the first selection transistor; a second selection transistor; a second selection gate line connected to a gate of the second selection transistor; a second wiring connected to the second selection transistor; a first and a second storage unit transistor connected between the first selection transistor and the second selection transistor; a first word line connected to the first storage unit transistor; and a second word line connected to the second storage unit transistor. The data write operation of the semiconductor storage device has a program operation and a verify operation, in the write operation to the first storage unit transistor, after the verify operation is performed, during the period in which the second selection transistor is in an on state, the voltage of the first word line changes from a first voltage to a second voltage, the voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, the voltage of the second selection gate line changes from a fifth voltage to a sixth voltage that makes the second selection transistor in an off state. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of the semiconductor storage device of the first embodiment.

[0008] Figure 2 is a circuit diagram of a storage unit array included in the semiconductor storage device of the first embodiment.

[0009] Figure 3 is a cross-sectional view of a storage unit array included in the semiconductor storage device of the first embodiment.

[0010] Figure 4 is a flowchart showing a write operation of the semiconductor storage device of the first embodiment.

[0011] Figure 5 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the first embodiment.

[0012] Figure 6 is a circuit diagram of two NAND strings within a memory cell array included in the semiconductor storage device of the first embodiment.

[0013] Figure 7 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the second embodiment.

[0014] Figure 8 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the third embodiment.

[0015] Figure 9 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the fourth embodiment.

[0016] Figure 10 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the fifth embodiment.

[0017] Figure 11 is a circuit diagram of two NAND strings within a memory cell array included in the semiconductor storage device of the fifth embodiment.

[0018] Figure 12 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the sixth embodiment.

[0019] Figure 13 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the seventh embodiment.

[0020] Figure 14 is a timing chart showing voltages of various wirings and the like at the time of the write operation of the semiconductor storage device of the eighth embodiment. DETAILED DESCRIPTION

[0021] Embodiments will be described below with reference to the accompanying drawings. In the description, common reference signs are assigned to the parts common to all the drawings.

[0022] [1] First Embodiment

[0023] The semiconductor storage device of the first embodiment will be described.

[0024] [1-1] Configuration

[0025] [1-1-1] Overall configuration of semiconductor storage device

[0026] Usage Figure 1 An overall configuration of the semiconductor storage device of the present embodiment will be described. Figure 1 is a block diagram of the semiconductor storage device of the present embodiment.

[0027] The semiconductor storage device 1 is a NAND type flash memory capable of nonvolatile storage of data, and is capable of being controlled by an external memory controller 2. The semiconductor storage device 1 includes a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, a sense amplifier module 16, and a source line driver 17.

[0028] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is a natural number of 1 or more). A block BLK includes a set of a plurality of memory cells capable of nonvolatile storage of data, and is used as a unit of data erasure, for example. In the memory cell array 10, a plurality of bit lines and a plurality of word lines are provided. Each memory cell is associated with one bit line and one word line, for example. Details of the memory cell array 10 will be described later.

[0029] The instruction register 11 stores an instruction CMD received by the semiconductor storage device 1 from the memory controller 2. The instruction CMD includes a command for causing the sequencer 13 to perform a readout operation, a write operation, and an erasure operation, for example.

[0030] The address register 12 stores address information ADD received by the semiconductor storage device 1 from the memory controller 2. The address information ADD includes a block address BAd, a page address PAd, and a column address CAd, for example. The block address BAd, the page address PAd, and the column address CAd are used for selection of a block BLK, a word line, and a bit line, respectively, for example.

[0031] The sequencer 13 controls the operation of the semiconductor storage device 1 as a whole. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, and the like, based on the instruction CMD stored in the instruction register 11, to perform a readout operation, a write operation, and an erasure operation, and the like.

[0032] The driver module 14 generates voltages used for a readout operation, a write operation, and an erasure operation, and the like. The driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on the page address PAd stored in the address register 12.

[0033] The row decoder module 15 selects one block BLK within the memory cell array 10 based on the block address BAd stored in the address register 12. The row decoder module 15 transmits a voltage applied to a signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0034] The sense amplifier module 16 applies a voltage corresponding to the write data DAT received from the memory controller 2 to the bit line in the write operation. In addition, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line in the read operation, and transmits the determination result as the read data DAT to the memory controller 2.

[0035] The sense amplifier module 16 includes a plurality of sense amplifier units SAU not shown. Each sense amplifier unit SAU includes a plurality of latch circuits. The plurality of sense amplifier units SAU are each connected to each bit line. In addition, each sense amplifier unit SAU transmits and receives the data DAT with an input / output circuit not shown within the semiconductor memory device 1.

[0036] The source line driver 17 generates a voltage used in the read operation, the write operation, and the erase operation, and applies the generated voltage to the source line.

[0037] The semiconductor memory device 1 configured as described above is connected to the memory controller 2 via a NAND interface not shown. Specific examples of signals transmitted and received between the semiconductor memory device 1 and the memory controller 2 are a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, an input / output signal I / O, and the like. The memory controller 2 controls the semiconductor memory device 1 using these signals.

[0038] The signal CLE is a signal indicating that the signal I / O received by the semiconductor memory device 1 is a command CMD. The signal ALE is a signal indicating that the signal I / O received by the semiconductor memory device 1 is address information ADD. The signal WEn is a signal instructing the semiconductor memory device 1 to input the signal I / O. The signal REn is a signal instructing the semiconductor memory device 1 to output the signal I / O. The signals CLE, ALE, WEn, and REn are transmitted from the memory controller 2 to the semiconductor memory device 1.

[0039] The signal RBn is a signal indicating either a ready state or a busy state of the semiconductor memory device 1, for example, an "L" level when the semiconductor memory device 1 is in the busy state. The ready state is a state in which the semiconductor memory device 1 can accept a command from the memory controller 2. The busy state is a state in which the semiconductor memory device 1 cannot accept a command from the memory controller 2. The signal RBn is transmitted from the semiconductor memory device 1 to the memory controller 2.

[0040] The signal I / O is, for example, an 8-bit signal. The signal I / O is an entity of data that is transmitted and received between the semiconductor storage device 1 and the memory controller 2, for example, an instruction CMD, address information ADD, and data DAT.

[0041] The semiconductor storage device 1 and the memory controller 2 described above can also be configured as one semiconductor device by a combination thereof. As such a semiconductor device, a memory card such as an SD (Secure Digital) card, or an SSD (solid state drive) can be exemplified. TM

[0042] [1-1-2] Circuit configuration of memory cell array 10

[0043] Use Figure 2 The circuit configuration of the memory cell array 10 will be described. Figure 2 is a circuit diagram of the memory cell array 10 included in the semiconductor storage device 1 of the present embodiment. Figure 2 One block BLK among a plurality of blocks BLK included in the memory cell array 10 is extracted to represent one example of the circuit configuration of the memory cell array 10. The other blocks BLK also all have the configuration shown in Figure 2

[0044] The block BLK includes, for example, four string assemblies SU0 to SU3. Each string assembly SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is a natural number of one or more). Each NAND string NS includes, for example, storage cell transistors MC0 to MC7, and selection transistors ST1 and ST2. The storage cell transistor MC includes a control gate and a charge storage layer, and stores data nonvolatilely. The selection transistors ST1 and ST2 are each used for selection of the string assembly SU at various operations.

[0045] In each NAND string NS, the storage cell transistors MC0 to MC7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the storage cell transistors MC0 to MC7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the storage cell transistors MC0 to MC7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0046] ​​In the same block BLK, the control gates of the memory cell transistors MC0 to MC7 are commonly connected to the word lines WL0 to WL7, respectively. The gates of the selection transistors ST1 in the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3, respectively. The gates of the selection transistors ST2 included in the same block BLK are commonly connected to the selection gate line SGS.

[0047] In the circuit configuration of the memory cell array 10 described above, the bit line BL is commonly shared by the NAND strings NS in each string unit SU that are assigned the same column address CAd, for example. The source line SL is commonly shared among a plurality of blocks BLK, for example.

[0048] A set of a plurality of memory cell transistors MC connected to a common word line WL in one string unit SU is referred to as a cell unit CU, for example. The storage capacity of the cell unit CU including memory cell transistors MC that store one bit of data each is defined as "one page of data", for example. The cell unit CU can have a storage capacity of two or more pages of data depending on the number of bits of data stored by the memory cell transistors MC.

[0049] Furthermore, the circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK, or the number of memory cell transistors MC and selection transistors ST1 and ST2 included in each NAND string NS can each be any number.

[0050] [1-1-3] Configuration of Memory Cell Array 10

[0051] Use Figure 3 The configuration of the memory cell array 10 will be described. Figure 3 is a cross-sectional view of the memory cell array 10 included in the semiconductor storage device 1 of the present embodiment. Figure 3 is an example of a cross-sectional configuration of the memory cell array 10 in which a partial region of a block BLK is extracted. Furthermore, in the cross-sectional views referred to below, constituent elements such as insulator layers (interlayer insulating films), wiring, contacts, and the like are appropriately omitted for easy viewing of the figures.

[0052] The region in which the memory cell array 10 is formed includes a semiconductor substrate 20, conductive layers 21 to 25, a memory pillar MP, and a contact CP.

[0053] The surface of the semiconductor substrate 20 is disposed parallel to the XY plane. Above the semiconductor substrate 20, the conductive layer 21 is provided with an insulator layer interposed therebetween. The conductive layer 21 is formed in a plate shape extending along the XY plane, for example, and is used as a source line SL. Although not shown, a circuit such as a sense amplifier module 16 is provided in a region between the semiconductor substrate 20 and the conductive layer 21. The conductive layer 21 includes silicon doped with phosphorus, for example.

[0054] Above the conductor layer 21, a conductor layer 22 is provided with an intervening insulator layer. The conductor layer 22 is formed, for example, in a plate shape extending along the XY plane, and is used as a select gate line SGS. The conductor layer 22 contains, for example, silicon doped with phosphorus.

[0055] Above the conductor layer 22, an insulator layer and a conductor layer 23 are alternately laminated. The plurality of conductor layers 23 are each formed, for example, in a plate shape extending along the XY plane. The laminated plurality of conductor layers 23 are sequentially used as word lines WL0 to WL7 from the side of the semiconductor substrate 20, respectively. The conductor layer 23 contains, for example, tungsten.

[0056] Above the conductor layer 23 of the uppermost layer, a conductor layer 24 is provided with an intervening insulator layer. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane, and is used as a select gate line SGD. The conductor layer 24 contains, for example, tungsten.

[0057] Above the conductor layer 24, a conductor layer 25 is provided with an intervening insulator layer. The conductor layer 25 is formed, for example, in a line shape extending along the X direction, and is used as a bit line BL. That is, in a region not shown in the drawing, a plurality of conductor layers 25 are arranged along the Y direction. The conductor layer 25 contains, for example, copper.

[0058] The memory pillar MP corresponds to the NAND string NS. The memory pillar MP is formed, for example, in a column shape extending along the Z direction, and penetrates the conductor layers 22 to 24. The upper end of the memory pillar MP is contained, for example, in a layer between the layer provided with the conductor layer 24 and the layer provided with the conductor layer 25. The lower end of the memory pillar MP is in contact with the conductor layer 21, for example.

[0059] In addition, the memory pillar MP contains a semiconductor member 26 and insulator layers 27 to 29.

[0060] The semiconductor member 26 is formed in a column shape extending along the Z direction in the central portion of the memory pillar MP. The semiconductor member 26 functions as a channel of each of the memory cell transistor MC and the selection transistors ST1 and ST2.

[0061] The side surface of the semiconductor member 26 is covered with a laminated film of the insulator layers 27 to 29. The insulator layer 27 is in contact with the semiconductor member 26 and surrounds the side surface of the semiconductor member 26. The insulator layer 27 functions as a tunnel insulating film of the memory cell transistor MC.

[0062] The insulator layer 28 is in contact with the insulator layer 27 and surrounds the side surface of the insulator layer 27. The insulator layer 28 functions as a charge storage layer of the memory cell transistor MC.

[0063] The insulator layer 29 is in contact with the insulator layer 28 and surrounds the side surface of the insulator layer 28. The insulator layer 29 functions as a blocking insulating film of the memory cell transistor MC.

[0064] On the semiconductor part 26, a columnar contact CP is provided. One conductive layer 25, i.e., one bit line BL is in contact with the upper surface of the contact CP. Further, the memory pillar MP and the conductive layer 25 can be electrically connected via two or more contacts, or can be electrically connected via other wiring.

[0065] In the configuration of the memory pillar MP described above, for example, the portion where the memory pillar MP crosses the conductive layer 22 functions as the selection transistor ST2. The portions where the memory pillar MP crosses each of the eight layers of the conductive layer 23 function as the memory cell transistors MC0 to MC7, respectively. The portion where the memory pillar MP crosses the conductive layer 24 functions as the selection transistor ST1.

[0066] [1-2] Write Operation

[0067] A write operation of the semiconductor storage device 1 of the present embodiment will be described. The semiconductor storage device 1 of the present embodiment sequentially performs a write operation from the memory cell transistor MC provided on the selection transistor ST1 side toward the memory cell transistor MC provided on the selection transistor ST2 side within the NAND string NS. In other words, the semiconductor storage device 1 of the present embodiment sequentially performs a write operation from the cell assembly CU on the bit line BL side in each string assembly SU. A word line associated with the selected cell assembly CU is referred to as WLsel, and a word line associated with the non-selected cell assembly CU is referred to as WLusel. A selection gate line associated with the selected string assembly SU is referred to as SGDsel, and a selection gate line associated with the non-selected string assembly SU is referred to as SGDusel.

[0068] [1-2-1] Outline of Write Operation

[0069] An outline of the write operation will be described. The write operation roughly includes a program operation and a verify operation.

[0070] The programming operation is an operation of raising the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by prohibiting injection). The programming voltage VPGM is applied to the word line WLsel. The voltage VPGM is a high voltage capable of raising the threshold voltage of the corresponding memory cell transistor MC. Hereinafter, the operation of raising the threshold voltage will be referred to as "0' programming", and the bit line BL serving as the object of "0" programming is given a voltage corresponding to "0" programming (for example, ground voltage VSS) from the sense amplifier module 16. On the other hand, the operation of maintaining the threshold voltage will be referred to as "1' programming" or "write prohibition", and the bit line BL serving as the object of "1" programming is given a voltage (hereinafter referred to as "voltage VBL") corresponding to "1" programming from the sense amplifier module 16. Hereinafter, the bit line corresponding to "0" programming will be referred to as BLprog, and the bit line corresponding to "1" programming will be referred to as BLinh. In addition, the NAND string NS within the selected string assembly SU connected to the bit line BLprog will be referred to as "NAND string NSprog", and the NAND string NS within the selected string assembly SU connected to the bit line BLinh will be referred to as "NAND string NSinh".

[0071] The verify operation is an operation of reading out data after the programming operation, and determining whether the threshold voltage of the memory cell transistor MC reaches a target level serving as a target. Hereinafter, the case where the threshold voltage of the memory cell transistor MC reaches the target level will be referred to as "verify pass", and the case where the threshold voltage does not reach the target level will be referred to as "verify fail".

[0072] The combination of the programming operation and the verify operation (hereinafter referred to as "programming loop") is repeatedly performed until the threshold voltage of the memory cell transistor MC reaches the target level. Each time the programming loop is repeatedly performed, the set value of the voltage VPGM is raised. In addition, in the semiconductor storage device 1 of the present embodiment, a channel precharge operation can be performed in the programming loop.

[0073] The channel precharge operation is an operation of raising the channel voltage before the programming operation is performed. For example, the channel precharge operation is performed when the set value of the raised voltage VPGM exceeds a predetermined reference value. The semiconductor storage device 1 of the present embodiment precharges the channel voltage from the source line SL in each NAND string NS.

[0074] [1-2-2] Flowchart at the time of write operation

[0075] The flowchart at the time of the write operation will be described using Figure 4 Figure 4 is a flowchart showing the write operation of the semiconductor storage device 1 of the present embodiment. Figure 4 In the flowchart, the number of times of the programming loop is described as i (i is a natural number of 1 or more). ​

[0076] The semiconductor memory device 1 receives a command CMD, address information ADD, and write data from the memory controller 2 for a write operation. The command CMD is transferred to the command register 11. The address information ADD is transferred to the address register 12. The write data is transferred to any of the latches within the sense amplifier assembly SAU.

[0077] When the command CMD is stored in the command register 11, the address information ADD is stored in the address register 12, and the write data is stored in any of the latches within the sense amplifier assembly SAU, the semiconductor memory device 1 starts the write operation.

[0078] The sequencer 13 sets i = 1 (S10).

[0079] Next, the sequencer 13 performs a program operation (Sll).

[0080] When the program operation ends, a verify operation is performed (S12).

[0081] In the case where the verify is successful in S12 (S13_Yes), the sequencer 13 ends the write operation. On the other hand, in the case where the verify is unsuccessful in S12 (S13_No), the sequencer 13 determines whether i reaches a prescribed number of program loops (S14).

[0082] In the case where it is determined that i reaches the prescribed number of program loops (S14_Yes), the sequencer 13 ends the write operation. On the other hand, in the case where it is determined that i does not reach the prescribed number of program loops (S14_No), the sequencer 13 determines whether the set value of the voltage VPGM exceeds a reference value (S15). The reference value is a value used to determine whether to perform a channel precharge operation.

[0083] In the case where it is determined that the set value of the voltage VPGM exceeds the reference value (S15_Yes), the sequencer 13 performs the channel precharge operation (S16).

[0084] When the channel precharge operation ends, the sequencer 13 increases the set value of the voltage VPGM (S17). That is, the voltage VPGM applied to the word line WLsel is increased as the number of program loops that have been performed increases. The amount of increase of the set value of the voltage VPGM can be set to an arbitrary value.

[0085] When the increase of the set value of the voltage VPGM ends, the sequencer 13 increments i to i = i + 1 (S18) and proceeds to Sll.

[0086] On the other hand, in the case where it is determined that the set value of the voltage VPGM does not exceed the reference value (S15_No), the sequencer 13 does not perform the channel precharge operation and proceeds to S17.

[0087] [1-2-3] Voltage of various wirings and the like at the time of write operation

[0088] Using Figure 5 The voltage of various wirings and the like at the time of write operation will be described. Figure 5 is a timing chart showing the voltage of various wirings and the like of the semiconductor storage device 1 of the present embodiment at the time of write operation.

[0089] Hereinafter, a case where the sequencer 13 performs a channel precharge operation continuously after a verify operation in the i-th (i is a natural number of 1 or more) program loop will be described. Further, a case where the channel precharge voltage is supplied from the source line SL in a state where the memory cell transistors MC6 and MC7 are written in the channel precharge operation and the memory cell transistors MC0 to MC5 are not written will be described as an example. The threshold voltage of the memory cell transistor MC which has been programmed with "0" is a positive voltage, and the threshold voltage of the memory cell transistor MC which has been programmed with "1" is a negative voltage. Hereinafter, a case where the threshold voltages of the memory cell transistors MC6 and MC7 are positive voltages will be described for the sake of simplicity. The threshold voltages of the memory cell transistors MC0 to MC5 which are not written are negative voltages. In addition, it is assumed that the voltages of the selected gate lines SGDsel and SGDusel, the word lines WLsel and WLusel, the selected gate line SGS, the bit lines BLprog and BLinh, and the source line SL, and the channel voltages of the NAND string NSprog (hereinafter, referred to as "Vch(prog)") and the NAND string NSinh (hereinafter, referred to as "Vch(inh)") before the start of the i-th program loop are each VSS (for example, 0 V).

[0090] The sequencer 13 sequentially performs the operations at time t1 to time t9. For example, the period from time t1 to time t3 corresponds to the i-th verify operation. The period from time t3 to time t5 corresponds to the channel precharge operation. The period from time t5 to time t6 is a precharge recovery operation. The precharge recovery operation is an operation which combines the end operation of the precharge operation and the preparation operation of the program operation. The period from time t6 to time t8 corresponds to the i+1-th program operation. The period from time t8 to time t9 is a program recovery operation. Hereinafter, the respective operations of the verify operation, the channel precharge operation, and the program operation will be described in order with reference to Figure 5

[0091] (Verify operation)

[0092] ​At time tl, the row decoder module 15 applies a voltage VSGD1 to the select gate lines SGDsel and SGDusel. The voltage VSGD1 is a voltage that makes the select transistor ST1 an on state. The voltage VSGD1 is a voltage higher than the voltage VSS. The row decoder module 15 applies a voltage VREAD to the word lines WLsel and WLusel. The voltage VREAD is a voltage that makes the corresponding memory cell transistor MC an on state regardless of the data stored in the memory cell transistor MC. The row decoder module 15 applies a voltage VSGS1 to the select gate line SGS. The voltage VSGS1 is a voltage that makes the select transistor ST2 an on state. The voltage VSGS1 is a voltage higher than the voltage VSS. The sense amplifier module 16 applies a voltage VBL1 to the bit lines BLprog and BLinh. The voltage VBL1 is a voltage higher than the voltage VSS. The source line driver 17 applies a voltage VCS1 to the source line SL. The voltage VCS1 is a voltage higher than the voltage VSS and lower than the voltage VBL1.

[0093] During the time tl to t2, the select transistors ST1 and ST2 in the block BLK and the memory cell transistor MC are made an on state, whereby the channel voltage of the NAND string NSprog, the NAND string NSinh, and the NAND string NS in the non-selected string assembly SU is the voltage VCS1.

[0094] At time t2, the row decoder module 15 applies the voltage VSS to the select gate line SGDusel. Thereby, the select transistor ST1 included in the non-selected string assembly SU becomes an off state. The row decoder module 15 applies a verify voltage VFY1 to the word line WLsel. The voltage VFY1 is a voltage that determines whether the threshold voltage of the memory cell transistor MC reaches a target level. The voltage VFY1 is a voltage higher than the voltage VSS and lower than the voltage VREAD.

[0095] In the NAND string NSprog, the voltage VFY1 is applied to the word line WLsel, whereby the memory cell transistor MC connected to the word line WLsel becomes an on state or an off state based on the stored data (threshold voltage). When the memory cell transistor MC connected to the word line WLsel becomes an on state, that is, the threshold voltage of the memory cell transistor MC as a write target is lower than the target level, a current flows from the bit line BLprog to the source line SL. In this case, the sequencer 13 determines that the verification fails. On the other hand, when the memory cell transistor MC connected to the word line WLsel becomes an off state, that is, the threshold voltage of the memory cell transistor MC as a write target is the target level or higher, a current hardly flows from the bit line BLprog to the source line SL. In this case, the sequencer 13 determines that the verification passes.

[0096] In the NAND string NSinh, the threshold voltage of the memory cell transistor MC is not raised by the programming operation, and therefore the memory cell transistor MC connected to the word line WLsel is in an on state.

[0097] (Channel pre-charge operation)

[0098] At time t3, the row decoder module 15 applies the voltage VSGD1 to the selected gate line SGDusel. The row decoder module 15 applies the voltage VREAD to the word line WLsel. As a result, the channel voltage of the NAND string NSprog, the NAND string NSinh, and the NAND string NS in the non-selected string assembly SU becomes the voltage VCS1, the verify operation ends, and the channel pre-charge operation starts.

[0099] At time t4, the row decoder module 15 applies the voltage VSS to the selected gate lines SGDsel and SGDusel, and the word lines WLsel and WLusel, respectively. The sense amplifier module 16 applies the voltage VSS to the bit line BLprog. During the period in which the voltage of each of the selected gate lines SGDsel and SGDusel is changed from the voltage VSGD1 to the voltage VSS (the voltage of each of the selected gate lines SGDsel and SGDusel is discharged), and the voltage of each of the word lines WLsel and WLusel is changed from the voltage VREAD to the voltage VSS (the voltage of each of the word lines WLsel and WLusel is discharged), the channel pre-charge operation is continued. In addition, in the case where the channel pre-charge operation is not performed, that is, in the case where the sequencer 13 determines that the set value of the voltage VPGM does not exceed the reference value (S15_no), the row decoder module 15 further applies the voltage VSS to the selected gate line SGS. The sense amplifier module 16 further sets the bit lines BLprog and BLinh in a floating state. The channel voltage of the NAND string NSprog, the NAND string NSinh, and the NAND string NS in the non-selected string assembly SU is lowered to an indefinite voltage by coupling between the channel and the word line WLsel, and coupling between the channel and the word line WLusel. As a result, the voltage of the bit lines BLprog and BLinh, and the source line SL is an indefinite voltage. Figure 4

[0100] During the period from time t4 to time t5, the row decoder module 15 further applies the voltage VSGS1 to the selected gate line SGS. The sense amplifier module 16 further applies the voltage VBL2 to the bit line BLinh. The voltage VBL2 can be the same voltage as the voltage VBL1, or can be a voltage higher than the voltage VBL1. In addition, the source line driver 17 applies the voltage VCS2 to the source line SL. The voltage VCS2 can be the same voltage as the voltage VCS1, or can be a voltage higher than the voltage VCS1.

[0101] ​During the time period from time t4 to time t5, the voltages of the selected gate lines SGDsel and SGDusel, the word lines WLsel and WLusel, and the bit line BLprog are each changed to the voltage VSS.

[0102] Here, the voltages of the selected gate lines SGDsel and SGDusel, the word lines WLsel and WLusel, and the bit line BLprog are each changed to the voltage VSS. Figure 6 The case of the NAND string NS at the time of the channel precharge operation will be described. Figure 6 is a circuit diagram of two NAND strings NS within the memory cell array 10 included in the semiconductor storage device 1 of the present embodiment. As an example, Figure 6 The NAND string NSprog and the NAND string NSinh are shown.

[0103] As shown in Figure 6 In the NAND string NSprog, the select transistor ST1 is brought to the off state by applying the voltage VSS to the selected gate line SGDsel. The select transistor ST2 is brought to the on state by applying the voltage VSGS1 to the selected gate line SGS. The memory cell transistors MC0 to MC5, each of which is not subjected to the write operation, are each brought to the on state by applying the voltage VSS to the word lines WLsel and WLusel, respectively. The memory cell transistors MC6 and MC7, each of which is subjected to the write operation, are each brought to the off state. As a result, in the NAND string NSprog, the voltage VCS2 is applied from the source line SL to the channel of each of the select transistor ST2 and the memory cell transistors MC0 to MC5. Thus, the channel voltage Vch(prog) is precharged to the voltage VCS2.

[0104] In the NAND string NSinh, the select transistor ST1 and the memory cell transistors MC6 and MC7, each of which is subjected to the write operation, are each brought to the off state, and the select transistor ST2 and the memory cell transistors MC0 to MC5, each of which is not subjected to the write operation, are each brought to the on state, as in the NAND string NSprog. Therefore, in the NAND string NSinh, the voltage VCS2 is applied from the source line SL to the channel of each of the select transistor ST2 and the memory cell transistors MC0 to MC5. Thus, the channel voltage Vch(inh) is precharged to the voltage VCS2.

[0105] In the NAND string NS within the non-selected string component SU, the select transistor ST1 is brought to the off state by applying the voltage VSS to the selected gate line SGDusel. In addition, the select transistor ST2 is brought to the on state. Therefore, the channel voltage of the NAND string NS within the non-selected string component SU is also precharged to the voltage VCS2.

[0106] Further, the channel precharge operation is not limited to the case where the channel from the source line SL to the memory cell transistor MC to which no write is performed is precharged. For example, the channel from the source line SL to the memory cell transistor MC to which a write ("0" program or "1" program) has been performed can be precharged by controlling the voltages of the word lines WLsel and WLusel respectively. Further, the channel from the source line SL to the select transistor ST1 can be precharged by controlling the voltages of the select gate lines SGDsel and SGDusel and the word lines WLsel and WLusel respectively.

[0107] At Figure 5 At time t5, the row decoder module 15 applies the voltage VSS to the select gate line SGS. By bringing the select transistor ST2 to the off state, the channels of the NAND string NSprog, the NAND string NSinh, and the NAND string NS within the non-selected string assembly SU become a floating state, and the channel precharge operation ends. Further, the channel voltages of the NAND string NSprog, the NAND string NSinh, and the NAND string NS within the non-selected string assembly SU are maintained at the voltage VCS2.

[0108] The period from time t5 to time t6 is a precharge recovery operation. By bringing the select transistors ST1 and ST2 to the off state respectively, the channels of the NAND string NSprog, the NAND string NSinh, and the NAND string NS within the non-selected string assembly SU are maintained in a floating state. Thereby, the channel voltages of the NAND string NSprog, the NAND string NSinh, and the NAND string NS within the non-selected string assembly SU are maintained at the voltage VCS2.

[0109] (Program operation)

[0110] At time t6, the row decoder module 15 applies a voltage VSGD2 to the selection gate line SGDsel. The voltage VSGD2 is a voltage that brings the selection transistor ST1 included in the NAND string NSprog into the on state and brings the selection transistor ST1 included in the NAND string NSinh into the off state. The row decoder module 15 applies a voltage VSS (e.g., 0 V) to the selection gate line SGDusel. By these controls, the selection transistor ST1 included in the NAND string NSprog is brought into the on state. In addition, the selection transistor ST1 included in the NAND string NSinh and the selection transistor ST1 included in the non-selected string component SU are brought into the off state. The row decoder module 15 applies a program voltage VPGM to the word line WLsel. The row decoder module 15 applies a voltage VPASS to the word line WLusel. The voltage VPASS is a voltage that brings the corresponding memory cell transistor MC into the on state regardless of the data (threshold voltage) stored in the memory cell transistor MC. The voltage VPASS is a voltage higher than the voltage VSGD2 and lower than the voltage VPGM. The row decoder module 15 applies a voltage VSS to the selection gate line SGS. Thus, the selection transistor ST2 is brought into the off state. The sense amplifier module 16 applies a voltage VSS to the bit line BLprog. The sense amplifier module 16 applies a voltage VBL2 to the bit line BLinh. The voltage VBL2 is a voltage higher than the voltage VSS. The source line driver 17 applies a voltage VCS2 to the source line SL. The voltage VCS2 is a voltage higher than the voltage VSS and brings the selection transistor ST2 into a stronger off state.

[0111] In the NAND string NSprog, the voltage VSGD2 is applied to the selection gate line SGDsel and the voltage VSS is applied to the bit line BLprog. Thus, the selection transistor ST1 is brought into the on state. The selection transistor ST2 is brought into the off state. In this state, the voltage VPGM is applied to the word line WLsel. Thus, the memory cell transistor MC connected to the word line WLsel is brought into the on state. By applying the voltage VPASS to the word line WLusel, the memory cell transistor MC connected to the word line WLusel is brought into the on state. As a result, the channel of the NAND string NSprog is electrically connected to the bit line BLprog. Thus, the channel voltage Vch(prog) becomes the voltage VSS. In the NAND string NSprog, electrons are injected from the channel to the charge storage layer of the memory cell transistor MC connected to the word line Wsel based on the voltage difference between the channel and the word line WLsel. Thus, the threshold voltage of the memory cell transistor MC connected to the word line Wsel is raised.

[0112] In the NAND string NSinh, a voltage VSGD2 is applied to the select gate line SGDsel, and a voltage VBL2 is applied to the bit line BLinh, whereby the select transistor ST1 is made to be in an off state. By making the select transistors ST1 and ST2 to be in the off state, the channel of the NAND string NSinh is made to be in a floating state. As a result, the channel voltage Vch(inh) rises to a voltage VBT through coupling between the channel and the word line WLusel (hereinafter, referred to as "self-boosting"). In the NAND string NSinh, the voltage difference between the channel and the word line WLsel is made to be smaller than that in the NAND string NSprog by the self-boosting, and therefore, the rise of the threshold voltage of the memory cell transistor MC connected to the word line WLsel is suppressed.

[0113] The select transistors ST1 and ST2 are also made to be in the off state in the non-selected string assembly SU. Therefore, as in the NAND string NSinh, the threshold voltage of the memory cell transistor MC connected to the word line WLsel is suppressed from rising due to the self-boosting.

[0114] At time t8, the row decoder module 15 applies a voltage VSS to the select gate line SGDsel, and to the word lines WLsel and WLusel, respectively. The sense amplifier module 16 applies a voltage VSS to the bit line BLinh. The source line driver 17 applies a voltage VSS to the source line SL. As a result, the programming operation ends.

[0115] The period from time t8 to time t9 is a programming recovery operation. By making the select transistors ST1 and ST2, and the memory cell transistors MC0 to MC7 to be in the off state, respectively, the channel voltages of the NAND strings NS in the NAND string NSprog, the NAND string NSinh, and the non-selected string assembly SU are made to be a voltage VSS.

[0116] [1-3] Effects

[0117] In the configuration of the present embodiment, in the i-th programming cycle, the pass precharge operation is performed continuously after the verify operation. In the pass precharge operation, in a state where the select transistor ST2 is turned on, the voltage of the select gate line SGDsel is changed from the voltage VSGD1 applied in the verify operation to the voltage VSS. After the voltage of the select gate line SGDusel is changed from the voltage VSS applied in the verify operation to the voltage VSGD1, the voltage is changed again from the voltage VSGD1 to the voltage VSS. Further, after the voltage of the word line WLsel is changed from the voltage VFY1 applied in the verify operation to the voltage VREAD, the voltage is changed again from the voltage VREAD to the voltage VSS. The voltage of the word line WLusel is changed from the voltage VREAD applied in the verify operation to the voltage VSS. After the voltages of the select gate lines SGDsel and SGDusel and the word lines WLsel and WLusel are each changed to the voltage VSS, the voltage of the select gate line SGS is changed from the voltage VSGS1 applied in the verify operation to the voltage VSS. By these controls, the pass voltage Vch(inh) is precharged to the voltage of the source line SL. That is, during the period in which the voltages of the select gate lines SGDsel and SGDusel and the word lines WLsel and WLusel are each changed from the voltage applied in the verify operation to the voltage VSS, the pass voltage Vch(inh) can be precharged. Thus, the time for performing the write operation can be reduced, and the operation of the semiconductor storage device 1 can be speeded up.

[0118] When the voltages of the word lines WLsel and WLusel are each changed to the voltage VSS after the pass voltage Vch(inh) is precharged, the precharged pass voltage Vch(inh) can sometimes be reduced due to the influence of the change to the voltage VSS. However, in the configuration of the present embodiment, the precharge of the pass voltage Vch(inh) ends after the voltages of the word lines WLsel and WLusel are each changed to the voltage VSS. Therefore, the voltages of the word lines WLsel and WLusel can also be changed to the voltage VSS after the pass voltage Vch(inh) is precharged. Thus, the precharged pass voltage Vch(inh) can be suppressed from being reduced, and the boost efficiency (the pass voltage Vch(inh) after precharge / the voltage VPASS of the word line WLusel) can be improved.

[0119] [2] Second Embodiment

[0120] The second embodiment will be described. The semiconductor storage device 1 of the present embodiment has the same configuration as that of the first embodiment. The flowchart showing the write operation is the same as that shown in the first embodiment Figure 4The semiconductor storage device 1 of this embodiment is the same as the semiconductor storage device 1 of the first embodiment. The semiconductor storage device 1 of this embodiment differs from the semiconductor storage device 1 of the first embodiment in that, at the time of the channel precharge operation, the voltage of the selection gate line SGS is changed from the voltage VSGSl applied at the time of the verify operation to the voltage VSS in two stages. Hereinafter, the differences from the first embodiment will be described.

[0121] [2-1] Voltages of various wirings and the like at the time of the write operation

[0122] The voltages of various wirings and the like at the time of the write operation will be described. Figure 7 The voltages of various wirings and the like at the time of the write operation will be described. Figure 7 is a timing chart showing the voltages of various wirings and the like of the semiconductor storage device 1 of this embodiment at the time of the write operation.

[0123] Hereinafter, a case where the sequencer 13, at the i-th (i is a natural number of 1 or more) programming cycle, performs the channel precharge operation continuously after the verify operation will be described. Further, a case where the channel precharge voltage is supplied from the source line SL in a state where the memory cell transistors MC6 and MC7 are written and the memory cell transistors MC0 to MC5 are not written in the channel precharge operation will be described as an example. Hereinafter, a case where the threshold voltages of the memory cell transistors MC6 and MC7 are positive voltages will be described for the sake of simplicity.

[0124] In the i-th programming cycle, after the programming operation is performed, the voltages of various wirings and the like are controlled as shown in the period from time t1 to time t3 in the first embodiment. Figure 5 Similarly, the voltages of various wirings and the like are controlled and the verify operation is performed. After the verify operation is performed, the channel precharge operation is performed. The voltages of various wirings and the like at the time of the channel precharge operation are controlled as follows.

[0125] (Channel precharge operation)

[0126] During the period from time t3 to time t4, the voltages of various wirings are the same as in the first embodiment. During the period from time t4 to time t5, the row decoder module 15 applies the voltage VSGS2 to the selection gate line SGS. The voltage VSGS2 is a voltage that brings the selection transistor ST2 to an on state. The voltage VSGS2 is a voltage that is higher than the voltage VSS and lower than the voltage VSGSl. Further, the voltage VSGS2 can be the same voltage as the voltage VSGSl or can be a voltage higher than the voltage VSGSl. The voltages of the other wirings are the same as in the first embodiment.

[0127] During the period from time t4 to time t5, the voltages of the selection gate lines SGDsel and SGDusel, the word lines WLsel and WLusel, and the bit line BLprog are each changed to the voltage VSS. The voltage of the selection gate line SGS is changed to the voltage VSGS2.

[0128] In the NAND string NSprog, a voltage VSS is applied to the select gate line SGDsel, whereby the select transistor ST1 becomes an off state. By applying a voltage VSGS2 to the select gate line SGS, the select transistor ST2 becomes an on state. By applying a voltage VSS to the word lines WLsel and WLusel, respectively, the memory cell transistors MC0 to MC5, which are not subjected to the write, each become an on state, and the memory cell transistors MC6 and MC7, which are subjected to the write, each become an off state. As a result, in the NAND string NSprog, a voltage VCS2 is applied from the source line SL to the channel of each of the select transistor ST2 and the memory cell transistors MC0 to MC5. Thereby, the channel voltage Vch(prog) is precharged to the voltage VCS2.

[0129] In the NAND string NSinh, as in the NAND string NSprog, the select transistor ST1 and the memory cell transistors MC6 and MC7, which are subjected to the write, each become an off state, and the select transistor ST2 and the memory cell transistors MC0 to MC5, which are not subjected to the write, each become an on state. Therefore, in the NAND string NSinh, a voltage VCS2 is applied from the source line SL to the channel of each of the select transistor ST2 and the memory cell transistors MC0 to MC5. Thereby, the channel voltage Vch(inh) is precharged to the voltage VCS2.

[0130] In the NAND string NS within the non-selected string unit SU, the select transistor ST1 becomes an off state by applying a voltage VSS to the select gate line SGDusel. In addition, the select transistor ST2 becomes an on state. Therefore, the channel voltage of the NAND string NS within the non-selected string unit SU is also precharged to the voltage VCS2.

[0131] After the channel precharge operation is performed, during a period from time t5 to time t9, the voltage of each of the various lines and the like is controlled as in the period from time t5 to time t9 in the first embodiment Figure 5 As in the period from time t5 to time t9 in the first embodiment, the channel precharge recovery operation, the program operation, and the program recovery operation are performed.

[0132] [2-2] Effects

[0133] According to the configuration of this embodiment, the same effects as in the first embodiment are achieved. Furthermore, in this embodiment, during the channel pre-charge operation, while applying voltage VSS to the select gate lines SGDsel and SGDusel, and word lines WLsel and WLusel respectively, the voltage of the select gate line SGS begins to change, from voltage VSGS1 applied during the verification operation to voltage VSGS2. Therefore, when voltage VSGS2 is lower than voltage VSGS1, the select gate line SGS is discharged. In this case, the speed at which the select gate line SGS changes from voltage VSGS2 to voltage VSS can be accelerated. On the other hand, when voltage VSGS2 is higher than voltage VSGS1, the select gate line SGS is charged. In this case, channel charging can be enhanced.

[0134] [3] Third embodiment

[0135] The third embodiment will be described. The semiconductor memory device 1 of this embodiment has the same configuration as that of the first embodiment. The flowchart illustrating the write operation is the same as that shown in the first embodiment. Figure 4 The semiconductor memory device 1 of this embodiment differs from that of the first embodiment in that, during the channel pre-charge operation, the voltages of the word lines WLsel and WLusel are changed to a voltage higher than the voltage VSS. Hereinafter, the description will focus on the differences from the first embodiment.

[0136] [3-1] Voltage of various wiring components during write operation

[0137] use Figure 8 The voltage of various wiring components during the write operation is explained. Figure 8 This is a timing diagram showing the voltages of various wirings, etc., during the write operation of the semiconductor memory device 1 in this embodiment.

[0138] The following explanation describes the case where, in the i-th programming loop (where i is a natural number greater than or equal to 1), the sequencer 13 performs the channel precharge operation consecutively with the verification operation after the verification operation. Furthermore, the explanation will focus on the case where, during the channel precharge operation, memory cell transistors MC6 and MC7 are written to, but memory cell transistors MC0 to MC5 are not written to, and the channel precharge voltage is applied from the source line SL. For simplicity, the explanation will focus on the case where the threshold voltages of memory cell transistors MC6 and MC7 are positive.

[0139] In the i-th programming loop, after performing the programming action, it is consistent with the first embodiment. Figure 5The voltage of each wiring and the like is controlled during the period from time tl to time t3 as shown, and a verification operation is performed. After the verification operation is performed, a channel pre-charge operation is performed. The voltage of each wiring and the like at the time of the channel pre-charge operation is controlled as follows.

[0140] (Channel pre-charge operation)

[0141] During the period from time t3 to time t4, the voltage of each wiring is the same as in the first embodiment. During the period from time t4 to time t5, the row decoder module 15 applies the voltage VWLs to the word line WLsel. The row decoder module 15 applies the voltage VWLu to the word line WLusel. The voltages VWLs and VWLu are voltages that cause the storage unit transistor MC that has not undergone writing to be in an on state and the storage unit transistor MC that has undergone writing to be in an off state, respectively. The voltages VWLs and VWLu are voltages that are higher than the voltage VSS, respectively. The voltage VWLu can be the same voltage as the voltage VWLs or a different voltage from the voltage VWLs. The voltage of the other wiring is the same as in the first embodiment.

[0142] During the period from time t4 to time t5, the voltage of each of the select gate lines SGDsel and SGDusel and the bit line BLprog changes to the voltage VSS. The voltage of the word line WLsel changes to the voltage VWLs. The voltage of the word line WLusel changes to the voltage VWLu.

[0143] In the NAND string NSprog, the voltage VSS is applied to the select gate line SGDsel, whereby the select transistor ST1 is brought to an off state. The voltage VSGSl is applied to the select gate line SGS, whereby the select transistor ST2 is brought to an on state. The voltage VWLs is applied to the word line WLsel, and the voltage VWLu is applied to the word line WLusel, whereby the storage unit transistors MC0 to MC5 that have not undergone writing are each brought to an on state, and the storage unit transistors MC6 and MC7 that have undergone writing are each brought to an off state. As a result, in the NAND string NSprog, the voltage VCS2 is applied from the source line SL to each of the channel of the select transistor ST2 and the storage unit transistors MC0 to MC5. Thereby, the channel voltage Vch(prog) is pre-charged to the voltage VCS2.

[0144] In the NAND string NSinh, as in the NAND string NSprog, the selection transistor ST1 and the memory cell transistors MC6 and MC7, which have undergone the write, each become the off state, and the selection transistor ST2 and the memory cell transistors MC0 to MC5, which have not undergone the write, each become the on state. Therefore, in the NAND string NSinh, the voltage VCS2 is applied to the channel of each of the selection transistor ST2 and the memory cell transistors MC0 to MC5 from the source line SL. Thus, the channel voltage Vch(inh) is precharged to the voltage VCS2.

[0145] In the NAND string NS within the non-selected string assembly SU, the selection transistor ST1 becomes the off state by applying the voltage VSS to the selection gate line SGDusel. In addition, the selection transistor ST2 becomes the on state. Therefore, the channel voltage of the NAND string NS within the non-selected string assembly SU is also precharged to the voltage VCS2.

[0146] After the channel precharge operation is performed, during the period from time t5 to time t9, the voltage of each of the various wirings and the like is controlled, and the channel precharge recovery operation, the program operation, and the program recovery operation are performed. Figure 5 As in the period from time t5 to time t9 in the first embodiment

[0147] [3-2] Effects

[0148] According to the configuration of the present embodiment, the same effects as those of the first embodiment are exerted. In addition, in the configuration of the present embodiment, in the channel precharge operation, the voltage of the selection gate line SGDsel is changed from the voltage VSGD1 applied in the verify operation to the voltage VSS while the selection transistor ST2 is in the on state. After the voltage of the selection gate line SGDusel is changed from the voltage VSS applied in the verify operation to the voltage VSGD1, the voltage is changed from the voltage VSGD1 to the voltage VSS. Furthermore, after the voltage of the word line WLsel is changed from the voltage VFY1 applied in the verify operation to the voltage VREAD, the voltage is changed from the voltage VREAD to the voltage VWLs (> voltage VSS). The voltage of the word line WLusel is changed from the voltage VREAD applied in the verify operation to the voltage VWLu (> voltage VSS). The voltages of the word lines WLsel and WLusel after the voltage change become voltages higher than the voltage VSS. Therefore, it is possible to accelerate the charging speed of the channel of the NAND string NS. In addition, it is also possible not to change the voltages of the word lines WLsel and WLusel to the voltage VSS. Therefore, it is possible to reduce the time for changing the voltage of the word line WLsel from the voltage VREAD to the voltage VWLs and the time for changing the voltage of the word line WLusel from the voltage VREAD to the voltage VWLu. Furthermore, it is possible to shorten the voltage VPASS and the voltage VPGM rise time in the next program operation.

[0149] Of course, the semiconductor memory device 1 of this embodiment can also be applied to the second embodiment.

[0150] [4] Fourth Embodiment

[0151] The fourth embodiment will be described. The semiconductor memory device 1 of this embodiment has the same configuration as that of the first embodiment. The flowchart illustrating the write operation is the same as that shown in the first embodiment. Figure 4 The semiconductor memory device 1 of this embodiment differs from that of the first embodiment in that, during the channel pre-charge operation, the voltage of the source line SL is increased from voltage VCS1 to voltage VCS2. Hereinafter, the description will focus on the differences from the first embodiment.

[0152] [4-1] Voltage of various wiring components during write operation

[0153] use Figure 9 The voltage of various wiring components during the write operation is explained. Figure 9 This is a timing diagram showing the voltages of various wirings, etc., during the write operation of the semiconductor memory device 1 in this embodiment.

[0154] The following explanation describes the case where, in the i-th programming loop (where i is a natural number greater than or equal to 1), the sequencer 13 performs the channel precharge operation consecutively with the verification operation after the verification operation. Furthermore, the explanation will focus on the case where, during the channel precharge operation, memory cell transistors MC6 and MC7 are written to, but memory cell transistors MC0 to MC5 are not written to, and the channel precharge voltage is applied from the source line SL. For simplicity, the explanation will focus on the case where the threshold voltages of memory cell transistors MC6 and MC7 are positive.

[0155] In the i-th programming loop, after performing the programming action, it is consistent with the first embodiment. Figure 5 During the period from time t1 to time t3, the voltages of various wiring components are controlled to perform a verification operation. After the verification operation, a channel pre-charge operation is performed. The voltage control of various wiring components during the channel pre-charge operation is as follows.

[0156] (Channel pre-charging action)

[0157] During time t3 to time t4, the voltages of all wirings are the same as in the first embodiment. During time t4 to time t5, the source line driver 17 applies voltage VCS2 to the source line SL. In this embodiment, voltage VCS2 is a higher voltage than voltage VCS1. The voltages of the other wirings are the same as in the first embodiment.

[0158] During the period from time t4 to time t5, the voltages of the selected gate lines SGDsel and SGDusel, the word lines WLsel and WLusel, and the bit line BLprog are each changed to the voltage VSS.

[0159] In the NAND string NSprog, the voltage VSS is applied to the selected gate line SGDsel, whereby the select transistor ST1 becomes an off state. The select transistor ST2 becomes an on state by applying the voltage VSGSl to the selected gate line SGS. By applying the voltage VSS to the word lines WLsel and WLusel, respectively, the memory cell transistors MC0 to MC5, which have not undergone the write, each become an on state, and the memory cell transistors MC6 and MC7, which have undergone the write, each become an off state. As a result, in the NAND string NSprog, the voltage VCS2 is applied from the source line SL to the channel of each of the select transistor ST2 and the memory cell transistors MC0 to MC5. Thereby, the channel voltage Vch(prog) is precharged to the voltage VCS2.

[0160] In the NAND string NSinh, as in the NAND string NSprog, the select transistor ST1 and the memory cell transistors MC6 and MC7, which have undergone the write, each become an off state, and the select transistor ST2 and the memory cell transistors MC0 to MC5, which have not undergone the write, each become an on state. Therefore, in the NAND string NSinh, the voltage VCS2 is applied from the source line SL to the channel of each of the select transistor ST2 and the memory cell transistors MC0 to MC5. Thereby, the channel voltage Vch(inh) is precharged to the voltage VCS2.

[0161] In the NAND string NS within the non-selected string component SU, the select transistor ST1 becomes an off state by applying the voltage VSS to the selected gate line SGDusel. In addition, the select transistor ST2 becomes an on state. Therefore, the channel voltage of the NAND string NS within the non-selected string component SU is also precharged to the voltage VCS2.

[0162] At time t5, the row decoder module 15 applies the voltage VSS to the selected gate line SGS. By making the select transistor ST2 an off state, the channels of the NAND string NSprog, the NAND string NSinh, and the NAND string NS within the non-selected string component SU become a floating state, and the channel precharge operation ends. In addition, the channel voltages of the NAND string NSprog, the NAND string NSinh, and the NAND string NS within the non-selected string component SU are maintained at the voltage VCS2.

[0163] The period from time t5 to time t7 is a precharge recovery operation. At time t6, the source line driver 17 applies a voltage VCS3 to the source line SL. The voltage VCS3 is a voltage higher than the voltage VSS and lower than the voltage VCS2. By making the selection transistor ST2 an off state, the channels of the NAND string NSprog, the NAND string NSinh, and the NAND string NS in the non-selected string assembly SU are maintained in a floating state. Thus, the channel voltages of the NAND string NSprog, the NAND string NSinh, and the NAND string NS in the non-selected string assembly SU are maintained at the voltage VCS2.

[0164] After the precharge recovery operation is performed, in the i+1th programming cycle, during the period from time t7 to time t10, the same as the period from time t6 to time t9 in the first embodiment Figure 5 The voltage of each wiring and the like is controlled, and a programming operation and a programming recovery operation are performed.

[0165] [4-2] Effects

[0166] According to the configuration of the present embodiment, the same effects as the first embodiment are exerted. In the configuration of the present embodiment, in the channel precharge operation, while the selection transistor ST2 is made on, the voltage of the source line SL is raised from the voltage VCS1 to the voltage VCS2 at the same time as the voltage VSS is applied to the selection gate lines SGDsel and SGDusel and the word lines WLsel and WLusel, respectively. Thus, the voltage of the channel precharge to each NAND string NS can be adjusted.

[0167] Of course, the semiconductor storage device 1 of the present embodiment can also be applied to the second and third embodiments.

[0168] [5] Fifth Embodiment

[0169] The fifth embodiment will be described. The semiconductor storage device 1 of the present embodiment has the same configuration as the first embodiment. The semiconductor storage device 1 of the present embodiment sequentially performs a write operation in each NAND string NS from the memory cell transistor MC provided on the selection transistor ST2 side toward the memory cell transistor MC provided on the selection transistor ST1 side. In other words, the semiconductor storage device 1 of the present embodiment sequentially performs a write operation in each string assembly SU from the cell assembly CU on the source line SL side. In addition, the semiconductor storage device 1 of the present embodiment applies a channel precharge voltage from the bit line BL in each NAND string NS. Hereinafter, the description will be centered on the points different from the first embodiment.

[0170] [5-1] Outline of Write Operation

[0171] An overview of the write operation is provided. The flowchart illustrating the write operation is the same as that shown in the first embodiment. Figure 4 same.

[0172] [5-2] Voltage of various wiring components during write operation

[0173] use Figure 10 The voltage of various wiring components during the write operation is explained. Figure 10 This is a timing diagram showing the voltages of various wirings, etc., during the write operation of the semiconductor memory device 1 in this embodiment.

[0174] The following explanation describes the case where, in the i-th programming loop (where i is a natural number greater than or equal to 1), the sequencer 13 performs the channel precharge operation consecutively with the verification operation after the verification operation. Furthermore, the explanation will take the case where, during the channel precharge operation, memory cell transistors MC0 and MC1 are written to, but memory cell transistors MC2 to MC7 are not written to, and the channel precharge voltage is applied from the bit line BL as an example. For simplicity, the explanation will now focus on the case where the threshold voltages of memory cell transistors MC0 and MC1 are positive.

[0175] In the i-th programming loop, after performing the programming action, it is consistent with the first embodiment. Figure 5 During the period from time t1 to time t3, the voltages of various wiring components are controlled to perform a verification operation. After the verification operation, a channel pre-charge operation is performed. The voltage control of various wiring components during the channel pre-charge operation is as follows.

[0176] (Channel pre-charging action)

[0177] During time t3 to time t4, the voltages of all wirings are the same as in the first embodiment. During time t4 to time t5, the line decoder module 15 applies voltage VSGD1 to the select gate line SGDsel and the select gate line SGDusel, respectively. Additionally, the line decoder module 15 applies voltage VSS to the select gate line SGS. The voltages of the other wirings are the same as in the first embodiment.

[0178] During the period from time t4 to time t5, the voltage changes of word lines WLsel and WLusel, select gate line SGS, and bit line BLprog are respectively called voltage VSS.

[0179] Here, use Figure 11 The status of the NAND string NS during the channel precharge operation is explained. Figure 11 This is a circuit diagram of two NAND strings NS within the memory cell array 10 included in the semiconductor memory device 1 of this embodiment. Figure 11The NAND string NSprog and NAND string NSinh are shown as examples.

[0180] like Figure 11 As shown, in the NAND string NSProg, applying voltage VSGD1 to the select gate line SGDsel turns select transistor ST1 on. Applying voltage VSS to the select gate line SGS turns select transistor ST2 off. Applying voltage VSS to word lines WLsel and WLusel respectively turns on unwritten memory cell transistors MC2-MC7, while written memory cell transistors MC0 and MC1 turn off. As a result, in the NAND string NSProg, voltage VSS is applied from the bit line BLprog to the channels of select transistor ST1 and memory cell transistors MC2-MC7. Thus, the channel voltage Vch(prog) is pre-charged to voltage VSS.

[0181] In the NAND string NSiNh, similar to the NAND string NSProg, the select transistor ST2 and the memory cell transistors MC0 and MC1 that have been written to are in the off state, while the select transistor ST1 and the memory cell transistors MC2 to MC7 that have not been written to are in the on state. Therefore, in the NAND string NSiNh, a voltage VBL2 is applied from the bit line BLinH to the respective channels of the select transistor ST1 and the memory cell transistors MC2 to MC7. As a result, the channel voltage Vch(inh) is precharged to the voltage VBL2.

[0182] In the NAND string NS within the non-select string assembly SU, by applying voltage VSS to the select gate line SGS, the select transistor ST2 becomes off. Simultaneously, the select transistor ST1 becomes on. Therefore, the channel voltage of the NAND string NS connected to the bit line BLprog within the non-select string assembly SU is pre-charged to voltage VSS. The channel voltage of the NAND string NS connected to the bit line BLinh within the non-select string assembly SU is also pre-charged to voltage VBL2.

[0183] Furthermore, the channel pre-charge operation is not limited to the case where pre-charging is performed from the bit lines BLprog and BLinh to the channels of the memory cell transistor MC that has not been written to. For example, pre-charging can also be performed from the bit lines BLprog and BLinh to the channels of the memory cell transistor MC that has been written to ("0" programming or "1" programming) by controlling the voltages of the word lines WLsel and WLusel. Alternatively, pre-charging can also be performed from the bit lines BLprog and BLinh to the channels of the select transistor ST2 by controlling the voltages of the select gate line SGS and the word lines WLsel and WLusel.

[0184] At Figure 10 time t5, the row decoder module 15 applies a voltage VSGD2 to the select gate line SGDsel. The row decoder module 15 applies a voltage VSS to the select gate line SGDusel. By making the select transistors ST1 included in the NAND string NSinh, the select transistors ST1 included in the non-select string component SU, and the select transistor ST2 into the off state, the channels of the NAND string NSinh and the NAND strings NS within the non-select string component SU become in the floating state, and the channel precharge operation ends. Further, the channel voltages of the NAND string NSprog and the NAND strings NS within the non-select string component SU connected to the bit line BLprog are maintained at the voltage VSS. The channel voltages of the NAND string NSinh and the NAND strings NS within the non-select string component SU connected to the bit line BLinh are maintained at the voltage VBL2.

[0185] The period from time t5 to time t6 is the precharge recovery operation. By making the select transistors ST1 included in the NAND string NSinh, the select transistors ST1 included in the non-select string component SU, and the select transistor ST2 into the off state, the channels of the NAND string NSinh and the NAND strings NS within the non-select string component SU are maintained in the floating state. Thereby, the channel voltages of the NAND string NSprog and the NAND strings NS within the non-select string component SU connected to the bit line BLprog are maintained at the voltage VSS. The channel voltages of the NAND string NSinh and the NAND strings NS within the non-select string component SU connected to the bit line BLinh are maintained at the voltage VBL2.

[0186] After the precharge recovery operation is performed, in the i+1th programming cycle, during the period from time t6 to time t9, the same as in the period from time t6 to time t9 in the first embodiment Figure 5 shown in the period from time t6 to time t9 in the first embodiment, the voltages of various wiring lines and the like are controlled, and the programming operation and the programming recovery operation are performed.

[0187] [5-3] Effects

[0188] In the configuration of this embodiment, in the i-th programming cycle, after the verify operation, a channel precharge operation is performed continuously with the verify operation. In the channel precharge operation, in a state where the select transistor ST1 is turned on, the voltage of the word line WLsel is changed from the voltage VFY1 applied in the verify operation to the voltage VREAD, and then from the voltage VREAD to the voltage VSS. The voltage of the word line WLusel is changed from the voltage VREAD applied in the verify operation to the voltage VSS. Further, the voltage of the select gate line SGS is changed from the voltage VSGS1 applied in the verify operation to the voltage VSS. After the voltages of the word lines WLsel and WLusel and the select gate line SGS are each changed to the voltage VSS, the voltage of the select gate line SGDsel is changed from the voltage VSGD1 applied in the verify operation to the voltage VSGD2, and the voltage of the select gate line SGDusel is changed from the voltage VSGD1 to the voltage VSS. By these controls, the channel voltage Vch(inh) is precharged to the voltage of the bit line BLinh. That is, during the period in which the voltages of the word lines WLsel and WLusel and the select gate line SGS are each changed from the voltage applied in the verify operation to the voltage VSS, the channel voltage Vch(inh) is precharged. In addition, in the configuration of this embodiment, after the voltages of the word lines WLsel and WLusel are each changed to the voltage VSS, the precharge of the channel voltage Vch(inh) ends. Thus, according to the configuration of this embodiment, the same effects as those of the first embodiment are exerted.

[0189] [6] Embodiment 6

[0190] Embodiment 6 will be described. The semiconductor storage device 1 of this embodiment has the same configuration as that of Embodiment 5. The flowchart showing the write operation is the same as that shown in Embodiment 1. The semiconductor storage device 1 of this embodiment differs from that of Embodiment 5 in that, in the channel precharge operation, the voltage of the select gate line SGDsel is changed from the voltage VSGD1 applied in the verify operation to the voltage VSGD2 in two stages. Hereinafter, the difference from Embodiment 5 will be described. Figure 4

[0191] [6-1] Voltages of various wiring lines and the like at the time of the write operation

[0192] The voltages of various wiring lines and the like at the time of the write operation will be described. Figure 12 The voltages of various wiring lines and the like at the time of the write operation will be described. Figure 12 is a timing chart showing the voltages of various wiring lines and the like at the time of the write operation of the semiconductor storage device 1 of this embodiment.

[0193] ​The following describes a case where the pass pre-charge operation is performed continuously after the verify operation in the i-th (i is a natural number of 1 or more) program loop of the sequencer 13. Further, a case where the pass pre-charge voltage is applied from the bit line BL in a state where the memory cell transistors MC0 and MC1 are written and the memory cell transistors MC2 to MC7 are not written in the pass pre-charge operation is exemplified. The following describes a case where the threshold voltages of the memory cell transistors MC0 and MC1 are positive voltages in order to simplify the description.

[0194] In the i-th program loop, the pass pre-charge operation is performed after the verify operation in the same period as the period from the time t1 to the time t3 in the 5th embodiment Figure 10 The voltage of each of the various wirings is controlled and the verify operation is performed in the same manner as in the 5th embodiment. After the verify operation is performed, the pass pre-charge operation is performed. The voltage of each of the various wirings at the time of the pass pre-charge operation is controlled as follows.

[0195] (Pass pre-charge operation)

[0196] The voltage of each of the various wirings is controlled and the verify operation is performed in the same manner as in the 5th embodiment. After the verify operation is performed, the pass pre-charge operation is performed. The voltage of each of the various wirings at the time of the pass pre-charge operation is controlled as follows.

[0197] The voltage of each of the various wirings is controlled and the verify operation is performed in the same manner as in the 5th embodiment. After the verify operation is performed, the pass pre-charge operation is performed. The voltage of each of the various wirings at the time of the pass pre-charge operation is controlled as follows.

[0198] In the NAND string NSprog, the selection transistor ST1 is brought to the on state by applying the voltage VSGD3 to the selection gate line SGDsel. The selection transistor ST2 is brought to the off state by applying the voltage VSS to the selection gate line SGS. The memory cell transistors MC2 to MC7 each of which is not written is brought to the on state and the memory cell transistors MC0 and MC1 each of which is written is brought to the off state by applying the voltage VSS to the word lines WLsel and WLusel, respectively. As a result, the voltage VSS is applied from the bit line BLprog to the channel of each of the selection transistor ST1 and the memory cell transistors MC2 to MC7 in the NAND string NSprog. Thus, the channel voltage Vch(prog) is pre-charged to the voltage VSS.

[0199] In the NAND string NSinh, as in the NAND string NSprog, the selection transistor ST2 and the memory cell transistors MC0 and MC1, which have undergone the write, are made to be in the off state, and the selection transistor ST1 and the memory cell transistors MC2 to MC7, which have not undergone the write, are made to be in the on state. Therefore, in the NAND string NSinh, the voltage VBL2 is applied to the channels of the selection transistor ST1 and the memory cell transistors MC2 to MC7, respectively, from the bit line BLinh. Thus, the channel voltage Vch(inh) is precharged to the voltage VBL2.

[0200] In the NAND string NS within the non-selected string assembly SU, the selection transistor ST2 is made to be in the off state by applying the voltage VSS to the selection gate line SGS. In addition, the selection transistor ST1 is made to be in the on state. Therefore, the channel voltage of the NAND string NS within the non-selected string assembly SU, which is connected to the bit line BLprog, is also precharged to the voltage VSS. The channel voltage of the NAND string NS within the non-selected string assembly SU, which is connected to the bit line BLinh, is also precharged to the voltage VBL2.

[0201] After the channel precharge operation is performed, during the period from time t5 to time t9, the voltage of each of the various wirings and the like is controlled, and the channel precharge recovery operation, the program operation, and the program recovery operation are performed, as in the period from time t5 to time t9 in the fifth embodiment. Figure 10

[0202] [6-2] Effects

[0203] According to the configuration of the present embodiment, the same effects as those of the fifth embodiment are exerted. In addition, in the configuration of the present embodiment, in the channel precharge operation, the voltage of the selection gate line SGDsel starts to change while the voltages of the word lines WLsel and WLusel and the selection gate line SGS are being applied with the voltage VSS, and the voltage VSGD1 applied in the verify operation changes to the voltage VSGD3. Therefore, in the case where the voltage VSGD3 is lower than the voltage VSGD1, the selection gate line SGDsel is discharged. In this case, it is possible to accelerate the speed of the change of the voltage of the selection gate line SGDsel to the voltage VSGD2. On the other hand, in the case where the voltage VSGD3 is higher than the voltage VSGD1, the selection gate line SGDsel is charged. In this case, it is possible to strengthen the charge of the channel.

[0204] [7] Seventh Embodiment

[0205] The seventh embodiment will be described. The semiconductor storage device 1 of the present embodiment has the same configuration as that of the fifth embodiment. The flowchart showing the write operation is the same as that shown in the first embodiment. Figure 4 ​The semiconductor storage device 1 of this embodiment is different from the fifth embodiment in that the voltage of each of the word lines WLsel and WLusel is changed to a voltage higher than the voltage VSS at the time of the passage precharge operation. Hereinafter, the differences from the fifth embodiment will be described.

[0206] [7-1] Voltages of various wirings and the like at the time of the write operation

[0207] The voltages of various wirings and the like at the time of the write operation will be described. Figure 13 The voltages of various wirings and the like at the time of the write operation will be described. Figure 13 is a timing chart showing the voltages of various wirings and the like of the semiconductor storage device 1 of this embodiment at the time of the write operation.

[0208] Hereinafter, a case where the sequencer 13 performs the passage precharge operation continuously after the verify operation in the i-th (i is a natural number of 1 or more) program loop will be described. Further, a case where the passage precharge voltage is supplied from the bit line BL in a state where the memory cell transistors MC0 and MC1 are written and the memory cell transistors MC2 to MC7 are not written in the passage precharge operation will be described as an example. Hereinafter, a case where the threshold voltages of the memory cell transistors MC0 and MC1 are positive voltages will be described for the sake of simplicity of the description.

[0209] In the i-th program loop, the passage precharge operation is performed after the program operation as in the fifth embodiment Figure 10 As in the fifth embodiment, the voltages of various wirings and the like are controlled and the verify operation is performed during the period from the time t1 to the time t3 shown in FIG. 27. After the verify operation is performed, the passage precharge operation is performed. The voltages of various wirings and the like at the time of the passage precharge operation are controlled as follows.

[0210] (Passage precharge operation)

[0211] During the period from the time t3 to the time t4, the voltages of various wirings are the same as in the fifth embodiment. During the period from the time t4 to the time t5, the row decoder module 15 applies the voltage VWLs to the word line WLsel. The row decoder module 15 applies the voltage VWLu to the word line WLusel. The voltages of the other wirings are the same as in the fifth embodiment.

[0212] During the period from the time t4 to the time t5, the word line WLsel is changed to the voltage VWLs. The word line WLusel is changed to the voltage VWLu. The voltages of the select gate line SGS and the bit line BLprog are each changed to the voltage VSS.

[0213] In the NAND string NSprog, the selection transistor ST1 becomes in the on state by applying the voltage VSGD1 to the selection gate line SGDsel. The selection transistor ST2 becomes in the off state by applying the voltage VSS to the selection gate line SGS. The voltage VWLs is applied to the word line WLsel, and the voltage VWLu is applied to the word line WLusel, whereby the memory cell transistors MC2 to MC7 which are not subjected to the write operation each become in the on state, and the memory cell transistors MC0 and MC1 which are subjected to the write operation each become in the off state. As a result, in the NAND string NSprog, the voltage VSS is applied from the bit line BLprog to the channel of each of the selection transistor ST1 and the memory cell transistors MC2 to MC7. Thus, the channel voltage Vch(prog) is precharged to the voltage VSS.

[0214] In the NAND string NSinh, as in the NAND string NSprog, the selection transistor ST2 and the memory cell transistors MC0 and MC1 which are subjected to the write operation are each made in the off state, and the selection transistor ST1 and the memory cell transistors MC2 to MC7 which are not subjected to the write operation are each made in the on state. Therefore, in the NAND string NSinh, the voltage VBL2 is applied from the bit line BLinh to the channel of each of the selection transistor ST1 and the memory cell transistors MC2 to MC7. Thus, the channel voltage Vch(inh) is precharged to the voltage VBL2.

[0215] In the NAND string NS within the non-selected string assembly SU, the selection transistor ST2 becomes in the off state by applying the voltage VSS to the selection gate line SGS. In addition, the selection transistor ST1 becomes in the on state. Therefore, the channel voltage of the NAND string NS within the non-selected string assembly SU which is connected to the bit line BLprog is also precharged to the voltage VSS. The channel voltage of the NAND string NS within the non-selected string assembly SU which is connected to the bit line BLinh is also precharged to the voltage VBL2.

[0216] After the channel precharge operation is performed, during the period from time t5 to time t9, the voltage of each of the various wiring lines and the like is controlled as in the period from time t5 to time t9 in the fifth embodiment Figure 10 The channel precharge recovery operation, the program operation, and the program recovery operation are performed.

[0217] [7-2] Effects

[0218] According to the configuration of this embodiment, the same effects as the fifth embodiment are exerted. In addition, in the configuration of this embodiment, in the passage precharge operation, after the voltage of the word line WLsel is changed from the voltage VFY1 applied in the verify operation to the voltage VREAD, the voltage is further changed from the voltage VREAD to the voltage VWLs (> VSS) in a state where the selection transistor ST1 is made to be on. The voltage of the word line WLusel is changed from the voltage VREAD applied in the verify operation to the voltage VWLu (> VSS). Further, the voltage of the select gate line SGS is changed from the voltage VSGS1 applied in the verify operation to the voltage VSS. The voltages of the word lines WLsel and WLusel after the voltage change become voltages higher than the voltage VSS. In addition, the voltages of the word lines WLsel and WLusel can not be changed to the voltage VSS. Thus, according to the configuration of this embodiment, the same effects as the third embodiment are exerted.

[0219] Of course, the semiconductor storage device 1 of this embodiment can also be applied to the sixth embodiment.

[0220] [8] The eighth embodiment

[0221] The eighth embodiment will be described. The semiconductor storage device 1 of this embodiment has the same configuration as the fifth embodiment. The flowchart showing the write operation is the same as that shown in the first embodiment. Figure 4 The semiconductor storage device 1 of this embodiment differs from the fifth embodiment in that, in the passage precharge operation, the voltage of the bit line BL is raised from the voltage VBL1 to the voltage VBL2. Hereinafter, the differences from the fifth embodiment will be described.

[0222] [8-1] Voltages of various wiring lines and the like at the time of the write operation

[0223] The voltages of various wiring lines and the like at the time of the write operation will be described. Figure 14 The voltages of various wiring lines and the like at the time of the write operation will be described. Figure 14 is a timing chart showing the voltages of various wiring lines and the like at the time of the write operation of the semiconductor storage device 1 of this embodiment.

[0224] Hereinafter, a case where, in the programming cycle of the i-th (i is a natural number of 1 or more) time, the passage precharge operation is executed continuously with the verify operation after the verify operation by the sequencer 13 will be described. In addition, a case where, in the passage precharge operation, the passage precharge voltage is supplied from the bit line BL in a state where the memory cell transistors MC0 and MC1 are written and the memory cell transistors MC2 to MC7 are not written will be described as an example. Hereinafter, for the sake of simplicity, a case where the threshold voltages of the memory cell transistors MC0 and MC1 are positive voltages will be described.

[0225] In the i-th programming cycle, after the programming operation, the voltages of the various lines are controlled as shown in the period from time tl to time t3 in the fifth embodiment Figure 10 Similarly, the voltages of the various lines are controlled, and the verify operation is performed in the period from time tl to time t3. After the verify operation, the channel pre-charge operation is performed. The voltages of the various lines at the time of the channel pre-charge operation are controlled as follows.

[0226] (Channel pre-charge operation)

[0227] In the period from time t3 to time t4, the voltages of the various lines are the same as in the fifth embodiment. In the period from time t4 to time t5, the sense amplifier module 16 applies the voltage VBL2 to the bit line BLinh. In the present embodiment, the voltage VBL2 is a voltage higher than the voltage VBLl. The voltages of the other lines are the same as in the fifth embodiment.

[0228] In the period from time t4 to time t5, the voltages of the word lines WLsel and WLusel, the select gate line SGS, and the bit line BLprog each change to the voltage VSS.

[0229] In the NAND string NSprog, the select transistor STl is brought to the on state by applying the voltage VSGDl to the select gate line SGDsel. The select transistor ST2 is brought to the off state by applying the voltage VSS to the select gate line SGS. The memory cell transistors MC2 to MC7 each of which has not undergone the write operation is brought to the on state, and the memory cell transistors MC0 and MC1 each of which has undergone the write operation is brought to the off state by applying the voltage VSS to the word lines WLsel and WLusel, respectively. As a result, in the NAND string NSprog, the voltage VSS is applied from the bit line BLprog to the channels of the select transistor STl and the memory cell transistors MC2 to MC7 each. Thus, the channel voltage Vch(prog) is pre-charged to the voltage VSS.

[0230] In the NAND string NSinh, the select transistor ST2 and the memory cell transistors MC0 and MC1 each of which has undergone the write operation are brought to the off state, and the select transistor STl and the memory cell transistors MC2 to MC7 each of which has not undergone the write operation are brought to the on state, as in the NAND string NSprog. Therefore, in the NAND string NSinh, the voltage VBL2 is applied from the bit line BLinh to the channels of the select transistor STl and the memory cell transistors MC2 to MC7 each. Thus, the channel voltage Vch(inh) is pre-charged to the voltage VBL2.

[0231] In the NAND string NS in the non-selected string assembly SU, the selection transistor ST2 becomes the off state by applying the voltage VSS to the selection gate line SGS. In addition, the selection transistor ST1 becomes the on state. Therefore, the channel voltage of the NAND string NS in the non-selected string assembly SU, which is connected to the bit line BLprog, is also pre-charged to the voltage VSS. The channel voltage of the NAND string NS in the non-selected string assembly SU, which is connected to the bit line BLinh, is also pre-charged to the voltage VBL2.

[0232] At time t5, the row decoder module 15 applies the voltage VSGD2 to the selection gate line SGDsel. The row decoder module 15 applies the voltage VSS to the selection gate line SGDusel. By making the selection transistor ST1 included in the NAND string NSinh, the selection transistor ST1 included in the non-selected string assembly SU, and the selection transistor ST2 become the off state, the channels of the NAND string NSinh and the NAND string NS in the non-selected string assembly SU become the floating state, and the channel pre-charge operation ends. In addition, the channel voltage of the NAND string NSprog and the NAND string NS in the non-selected string assembly SU, which is connected to the bit line BLprog, is maintained at the voltage VSS. The channel voltage of the NAND string NSinh and the NAND string NS in the non-selected string assembly SU, which is connected to the bit line BLinh, is maintained at the voltage VBL2.

[0233] The period from time t5 to time t7 is the pre-charge recovery operation. At time t6, the row decoder module 15 applies the voltage VBL3 to the bit line BLinh. The voltage VBL3 is a voltage higher than the voltage VSS and lower than the voltage VBL2. By making the selection transistor ST2 become the off state, the channels of the NAND string NSinh and the NAND string NS in the non-selected string assembly SU are maintained in the floating state. Thereby, the channel voltage of the NAND string NSprog and the NAND string NS in the non-selected string assembly SU, which is connected to the bit line BLprog, is maintained at the voltage VSS. The channel voltage of the NAND string NSinh and the NAND string NS in the non-selected string assembly SU, which is connected to the bit line BLinh, is maintained at the voltage VBL2.

[0234] After the pre-charge recovery operation is performed, in the (i+1)th programming cycle, during the period from time t7 to time tlO, the same as the period from time t6 to time t9 in the 5th embodiment Figure 10 is shown, the voltage of various wiring lines and the like is controlled, and the programming operation and the programming recovery operation are performed.

[0235] [8-2] Effects

[0236] According to the configuration of this embodiment, the same effects as the 5th embodiment are exerted. In addition, in the configuration of this embodiment, in the pass-gate precharge operation, while the voltage VSS is applied to the word lines WLsel and WLusel and the select gate line SGS, the voltage of the bit line BLinh is raised from the voltage VBL1 to the voltage VBL2 in the state where the selection transistor ST1 is turned on. Therefore, the voltage of the pass-gate precharge to each NAND string NS can be adjusted.

[0237] Of course, the semiconductor storage device 1 of this embodiment can also be applied to the 6th embodiment and the 7th embodiment.

[0238] [9] Variations

[0239] As described above, the semiconductor storage device of the embodiment is provided with: a first selection transistor (ST1); a first select gate line (SGDsel / SGDusel) connected to a gate of the first selection transistor; a first bit line (BLprog / BLinh) connected to the first selection transistor; a second selection transistor (ST2); a second select gate line (SGS) connected to a gate of the second selection transistor; a source line (SL) connected to the second selection transistor; first and second memory cell transistors (MC) connected between the first selection transistor and the second selection transistor; a first word line (WLsel) connected to the first memory cell transistor; and a second word line (WLusel) connected to the second memory cell transistor. The data write operation is performed by repeatedly executing a cycle including a program operation and a verify operation. In the write operation to the first memory cell transistor, after the verify operation is performed, during a period where the second selection transistor (ST2) is in an on state, the voltage of the first word line (WLsel) is changed from a first voltage to a second voltage, the voltage of the second word line (WLusel) is changed from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line is changed to the second voltage and the voltage of the second word line is changed to the fourth voltage, the voltage of the second select gate line (SGS) is changed from a fifth voltage to a sixth voltage.

[0240] Furthermore, the embodiment is not limited to the modes described above, and various changes can be made.

[0241] In addition, the flowcharts described in the embodiment can exchange the order of processing as much as possible.

[0242] The present application has been described with several embodiments, but these embodiments are presented as examples and are not intended to limit the scope of the application. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments or variations thereof are included in the scope or spirit of the application, and are also included in the scope of the application as recited in the claims and equivalents thereof.

[0243] [Explanation of symbols]

[0244] 1 semiconductor memory device

[0245] 2 memory controller

[0246] 10 memory cell array

[0247] 11 instruction register

[0248] 12 address register

[0249] 13 sequencer

[0250] 14 driver module

[0251] 15 row decoder module

[0252] 16 sense amplifier module

[0253] 17 source line driver

[0254] 20 semiconductor substrate

[0255] 21 to 25 conductive layer

[0256] 26 semiconductor component

[0257] 27 to 29 insulator layer

Claims

1. A semiconductor memory device, characterized in that... include: First-choice transistor; The first selected gate line is connected to the gate of the first selected transistor; The first wiring is connected to the first selection transistor; Second-choice transistor; The second selection gate line is connected to the gate of the second selection transistor; The second wiring is connected to the second selection transistor; The first and second memory cell transistors are connected between the first selection transistor and the second selection transistor; The first word line is connected to the transistor in the first memory cell; as well as The second word line is connected to the transistor in the second memory cell; and During the write operation of the second memory cell transistor, after the verification operation is performed, during the first period when the second selection transistor is in the on state, the voltage of the first word line changes from a first voltage to a second voltage lower than the first voltage, and the voltage of the second word line changes from a third voltage applied during the verification operation to a fourth voltage lower than the third voltage. After the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, the voltage of the second select gate line changes from the fifth voltage to the sixth voltage that turns the second select transistor off. During the first period, the voltage of the second word line changes to the fourth voltage after changing from the third voltage to a seventh voltage, which is higher than the third voltage.

2. The semiconductor memory device according to claim 1, characterized in that: During the first period when the second selection transistor is in the on state, the voltage of the second selection gate line is maintained at the fifth voltage.

3. The semiconductor memory device according to claim 1, characterized in that: During the first period when the second selection transistor is in the on state, the voltage of the second selection gate line changes from the fifth voltage applied during the verification operation to the eighth voltage, and The voltage of the second selected gate line changes from the fifth voltage to the eighth voltage, and then changes to the sixth voltage.

4. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The second and fourth voltages are voltages that turn off the transistors of memory cells that have been written to and turn on the transistors of memory cells that have not been written to, and are higher than the ground voltage.

5. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The second voltage is applied to the first word line and the fourth voltage is applied to the second word line, and the voltage of the second wiring rises to a ninth voltage that is higher than that during the verification operation.

6. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The second selection transistor is connected between the second wiring and one end of the first memory cell transistor; The other end of the first memory cell transistor is connected to one end of the second memory cell transistor; The first selection transistor is connected between the first wiring and the other end of the second memory cell transistor; The write operation is performed in the order of the second memory cell transistor and the first memory cell transistor.

7. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The data writing action has a loop that includes programming actions and verification actions; The verification action is the nth verification action, and the programming action is the (n+1)th programming action, where n is an integer greater than or equal to 1.

8. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The first wiring is a bit line, and the second wiring is a source line.

9. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The first wiring is a source line, and the second wiring is a bit line.

10. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: The fifth voltage is higher than the sixth voltage.

11. The semiconductor memory device according to any one of claims 1 to 3, characterized in that: A channel precharge operation is performed between the verification operation and the programming operation. During the channel precharge operation, the voltage of the first word line changes from the first voltage to the second voltage, and the voltage of the second word line changes from the third voltage to the fourth voltage.

12. A memory system, characterized in that... It includes a semiconductor memory device and a memory controller for controlling the semiconductor memory device. The semiconductor memory device includes: The input / output circuit communicates with the memory controller to send and receive data. The control circuit controls the input / output circuit based on the control signal received from the memory controller; First-choice transistor; The first selected gate line is connected to the gate of the first selected transistor; The first wiring is connected to the first selection transistor; Second-choice transistor; The second selection gate line is connected to the gate of the second selection transistor; The second wiring is connected to the second selection transistor; The first and second memory cell transistors are connected between the first selection transistor and the second selection transistor; The first word line is connected to the transistor in the first memory cell; and The second word line is connected to the transistor in the second memory cell; and The input / output circuit receives a write command indicating a write operation from the memory controller; During the write operation of the second memory cell transistor, after the verification operation is performed, during the first period when the second selection transistor is in the on state, the voltage of the first word line changes from the first voltage to a second voltage lower than the first voltage, and the voltage of the second word line changes from the third voltage applied in the verification operation to a fourth voltage lower than the third voltage. After the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, the voltage of the second selected gate line changes from the fifth voltage to the sixth voltage that turns the second selected transistor off. During the first period, the voltage of the second word line changes to the fourth voltage after changing from the third voltage to a seventh voltage, which is higher than the third voltage.

13. A control method for a semiconductor memory device, characterized in that... The semiconductor memory device includes: First-choice transistor; The first selected gate line is connected to the gate of the first selected transistor; The first wiring is connected to the first selection transistor; Second-choice transistor; The second selection gate line is connected to the gate of the second selection transistor; The second wiring is connected to the second selection transistor; The first and second memory cell transistors are connected between the first selection transistor and the second selection transistor; The first word line is connected to the transistor in the first memory cell; and The second word line is connected to the transistor in the second memory cell; and The control method for the semiconductor memory device includes: During the write operation of the second memory cell transistor, after the verification operation is performed, during the first period when the second selection transistor is in the on state, the voltage of the first word line is changed from a first voltage to a second voltage lower than the first voltage, and the voltage of the second word line is changed from a third voltage applied during the verification operation to a fourth voltage lower than the third voltage. After the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, the voltage of the second select gate line changes from the fifth voltage to the sixth voltage that turns the second select transistor off. During the first period, the voltage of the second word line is changed from the third voltage to a seventh voltage, which is higher than the third voltage, and then changed to the fourth voltage.

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