Power failure protection circuit and method, storage medium and electronic device

Abstract

The present disclosure relates to the technical field of power-off protection, and specifically discloses a power-off protection circuit and method, a computer readable storage medium and an electronic device. The power-off protection circuit comprises a power supply conversion unit, a voltage comparison unit, an energy storage unit and a processor. The input end of the power supply conversion unit is connected to a voltage source, and the output end is connected to the processor. The voltage comparison unit is connected to the voltage source and the processor, and is configured to send a first interrupt signal to the processor when the voltage of the voltage source is less than a first reference voltage. The energy storage unit is connected to the processor. The processor is configured to control the communication state of the non-volatile memory according to the first interrupt signal. The technical scheme of the present disclosure overcomes the problem of data loss caused by power-off and improves the service life of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of power failure protection technology, and more specifically, to a power failure protection circuit and method, a computer-readable storage medium, and an electronic device. Background Technology

[0002] FLASH memory is a type of non-volatile memory that cannot retain data for long periods of time without a power supply.

[0003] Existing FLASH memory typically lacks protection circuitry. If an accident causes the power supply system of the FLASH memory to fail during read / write operations, it will not only result in data loss but also affect the lifespan of the memory.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a power-loss protection circuit, a power-loss protection method, a computer-readable medium, and an electronic device, thereby at least to some extent overcoming the problem of data loss due to power failure and improving the lifespan of the memory.

[0006] According to a first aspect of this disclosure, a power-down protection circuit is provided for use in a non-volatile memory, comprising: a processor; a power conversion unit, with its input terminal connected to a voltage source and its output terminal connected to the processor; a voltage comparison unit, connected to the voltage source and the processor, configured to send a first interrupt signal to the processor when the voltage of the voltage source is less than a first reference voltage; and an energy storage unit, connected to the processor; wherein the processor is configured to control the communication state with the non-volatile memory according to the first interrupt signal.

[0007] According to a second aspect of this disclosure, a power-down protection method is provided, applied to a power-down protection circuit connected to a non-volatile memory. The power-down protection circuit includes a power conversion unit, a voltage comparison unit, an energy storage unit, and a processor. The input terminal of the power conversion unit is connected to a voltage source, and the output terminal is connected to the processor. The energy storage unit is connected to the processor. The method includes: when the voltage of the voltage source is less than a first reference voltage, the voltage comparison unit sends a first interrupt signal to the processor; the processor controls the communication state with the non-volatile memory according to the first interrupt signal.

[0008] According to a third aspect of this disclosure, a computer-readable medium is provided that stores a computer program thereon, which, when executed by a processor, implements the method described above.

[0009] According to a fourth aspect of this disclosure, an electronic device is provided, characterized in that it includes the power-off protection circuit described above.

[0010] One embodiment of this disclosure provides a power-loss protection circuit including a power conversion unit, a voltage comparison unit, an energy storage unit, and a processor. The power conversion unit's input is connected to a voltage source, and its output is connected to the processor. The voltage comparison unit is connected to both the voltage source and the processor, and is used to send a first interrupt signal to the processor when the voltage of the voltage source is lower than a first reference voltage. The energy storage unit is connected to the processor. The processor controls the communication state with the non-volatile memory based on the first interrupt signal. Compared to existing technologies, by using a voltage comparison unit to determine whether the voltage of the voltage source can meet the operating requirements of the processor and the non-volatile memory, and sending a first interrupt signal to the processor when the voltage of the voltage source is lower than the first reference voltage (i.e., when the voltage of the voltage source cannot meet the operating requirements of the processor and the non-volatile memory), a signal is sent to the processor so that the processor can control the communication state with the non-volatile memory, thus avoiding data loss due to unexpected power failure. Furthermore, when a power failure occurs during data transmission, the energy storage unit connected to the processor can provide a voltage that meets the conditions for the processor and the non-volatile memory, enabling them to complete the currently executed interaction, further improving data security.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0013] Figure 1 This schematic diagram illustrates the structure of a power-off protection circuit according to an exemplary embodiment of the present disclosure;

[0014] Figure 2 This schematic diagram illustrates the structure of another power-down protection circuit in an exemplary embodiment of the present disclosure.

[0015] Figure 3 This schematic diagram illustrates the structure of yet another power-down protection circuit according to an exemplary embodiment of the present disclosure;

[0016] Figure 4This schematic diagram illustrates the structure of another power-down protection circuit in an exemplary embodiment of the present disclosure.

[0017] Figure 5 A flowchart illustrating a power failure protection method according to an exemplary embodiment of the present disclosure is shown schematically.

[0018] Figure 6 This schematically illustrates a flowchart of a processor adjusting a communication state in an exemplary embodiment of the present disclosure;

[0019] Figure 7 A schematic diagram of an electronic device to which embodiments of the present disclosure may be applied is shown. Detailed Implementation

[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0022] Flash memory is a non-volatile memory that allows memory cells to be erased, written to, and reprogrammed. Write operations on any Flash device can only be performed in empty or erased memory cells; in most cases, an erase operation must be performed before a write operation. Flash memory has seen rapid development in recent years, with write and erase speeds reaching millisecond levels. However, compared to RAM, Flash memory's write and erase speeds are relatively slow. Therefore, if a power outage occurs during the write and erase process of Flash memory, it is still difficult to avoid the generation of corrupted data.

[0023] In existing technologies, the characteristic of Flash memory that data is not easily lost when power is off is often used to achieve data storage and software protection. The first byte of the physical block address in Flash memory is usually the logical block number, arranged in linear order. This logical block number is changed by developers through corresponding programs, and the logical block number of the physical block can be modified. Before rewriting a block, the original data in the block to be operated on needs to be read into RAM, the rewrite operation is performed in RAM, and the rewritten data is written into a backup block. Simultaneously, the logical block numbers of the backup block and the original operation block are swapped, making the original operation block the new backup block. The next time the same operation is performed, the data in the new backup block must be erased to store the rewritten data, following the same process. This existing technology, which uses code written by developers to operate on blocks and thus achieves software protection, can prevent data loss due to sudden power failure during block rewriting operations. However, this method comes at the cost of storing a large amount of operation code in Flash. Developers need to write corresponding programs to prevent the generation of bad data after power failure. This software protection method requires a lot of storage space to store firmware programs.

[0024] Based on one or more of the above-mentioned drawbacks, this disclosure first provides a power-loss protection circuit applied to a non-volatile memory 104, as shown in the reference. Figure 1 As shown, the power-down protection circuit may include a power conversion unit 101, a voltage comparison unit 102, an energy storage unit 107, and a processor 103. The input terminal of the power conversion unit 101 is connected to the voltage source 105, and the output terminal is connected to the processor 103. The voltage comparison unit 102 is connected to the voltage source 105 and the processor 103, and is used to send a first interrupt signal to the processor 103 when the voltage of the voltage source 105 is less than the first reference voltage. The energy storage unit 107 is connected to the processor 103. The processor 103 is used to control the communication state with the non-volatile memory 104 according to the first interrupt signal.

[0025] Compared to existing technologies, the power-loss protection circuit disclosed herein uses a voltage comparison unit 102 to determine whether the voltage of the voltage source 105 can meet the operating requirements of the processor 103 and the non-volatile memory 104. When the voltage of the voltage source 105 is less than the first reference voltage, a first interrupt signal is sent to the processor 103. That is, when the voltage of the voltage source 105 cannot meet the operating requirements of the processor 103 and the non-volatile memory 104, a first interrupt signal is sent to the processor 103 so that the processor 103 can control the communication state with the non-volatile memory 104, thus avoiding data loss caused by accidental power failure. Furthermore, when a power failure occurs during data transmission, the energy storage unit 107 connected to the processor 103 can provide the processor 103 and the non-volatile memory 104 with a voltage that meets the conditions, enabling the processor 103 and the non-volatile memory 104 to complete the currently executed interaction, further improving data security.

[0026] In one exemplary embodiment of this disclosure, the power conversion unit 101 may be a conversion unit for stepping down the voltage of the voltage source 105 or a voltage conversion unit for stepping up the voltage. The power conversion unit 101 may be a DC-DC converter or other converters, and no specific limitation is made in this exemplary embodiment.

[0027] In this example embodiment, the non-volatile memory 104 refers to a computer memory that does not lose the stored data when the current is turned off. It can be a Flash memory or other non-volatile memory 104, such as programmable read-only memory, electrically rewritable read-only memory, etc. It can also be customized according to user needs. In this example embodiment, no specific limitation is made.

[0028] In this example embodiment, the input terminal of the voltage conversion unit is connected to the voltage source 105, and the output terminal is connected to the processor 103.

[0029] In this example embodiment, the voltage comparison unit 102 can be connected to both the voltage source 105 and the processor 103, and is used to send a first interrupt signal to the processor 103 when the voltage of the voltage source 105 is less than the first reference voltage.

[0030] In one example implementation, when the processor 103 receives a first interrupt signal, it disables the write operation of the non-volatile memory 104. The content being written can be completed by the power storage unit 107 connected to the processor 103, which can protect the security of the data in the non-volatile memory 104.

[0031] In one example implementation, reference is made to Figure 2As shown, the voltage comparison unit 102 may include a first comparator 1021, wherein the first input terminal of the first comparator 1021 is connected to the input terminal of the power conversion unit 101, the second input terminal is connected to the first reference power supply, and the output terminal of the first comparator 1021 is connected to the processor 103.

[0032] In one example embodiment of this disclosure, the first reference voltage source 106 may be an independent voltage source 105, or it may include a first voltage regulator. The input terminal of the first voltage regulator is connected to the output terminal of the power conversion unit 101, and its output terminal is connected to the second input terminal of the first comparator 1021.

[0033] When the voltage of the voltage source 105 is greater than the first reference voltage, the first comparator 1021 outputs a high level, and the processor 103 maintains normal interaction with the non-volatile memory 104. When the voltage of the voltage source 105 is less than the first reference voltage, the first comparator 1021 outputs a low level, i.e., a first interrupt signal, and the processor 103 prohibits the write operation of the non-volatile memory 104. The content being written can be completed by the power storage unit 107 connected to the processor 103, which can protect the security of the data in the non-volatile memory 104.

[0034] In this example embodiment, the energy storage unit 107 can be an energy storage capacitor, a rechargeable battery, or it can be customized according to user needs. In this example embodiment, no specific limitation is made. In one example embodiment, the energy storage unit 107 can be connected to the output terminal of the power conversion unit 101 and connected to the processor, so that the power conversion unit 101 can charge the energy storage unit 107.

[0035] In another exemplary embodiment of this disclosure, reference is made to Figure 3 As shown, the voltage comparison unit 102 is also connected to the output terminal of the power conversion unit 101 and is used to send a second interrupt signal to the processor 103 when the voltage at the output terminal of the power conversion unit 101 is less than the second reference voltage.

[0036] In this example implementation, the processor 103 can first determine the time difference between the first interrupt signal and the second interrupt signal, and then the processor 103 can determine the upper limit and lower limit of the time based on the total power consumption of the processor 103 and the non-volatile memory 104.

[0037] In this example implementation, if the time difference is less than the lower time limit, the processor 103 drives the write protection WP of the GPIO non-volatile memory 104 through the general-purpose input / output interface; if the time difference is greater than the lower time limit and less than or equal to the upper time limit, the write operation of the non-volatile memory 104 is prohibited; if the time difference is greater than the upper time limit, the write operation of the non-volatile memory 104 is maintained until the data is written.

[0038] In this example of real-time mode, the above-mentioned upper time limit is greater than the lower time limit. For example, the above-mentioned lower time limit can be 1 millisecond, 2 milliseconds, etc., and the above-mentioned upper time limit can be 4 milliseconds, 5 milliseconds, etc. It can also be customized according to the power consumption of different processors 103 and non-volatile memory 104. In this example implementation, no specific limitation is made.

[0039] In this example implementation, refer to Figure 4 As shown, the voltage comparison unit 102 may further include a second comparator 1022. The first input terminal of the second comparator 1022 is connected to the output terminal of the power conversion unit 101, and the second input terminal of the second comparator 1022 is connected to the second reference voltage source 108. The output of the second reference voltage source 108 is the second reference voltage.

[0040] In one example embodiment of this disclosure, the second reference voltage source 108 may be an independent voltage source 105, or it may include a second voltage regulator. The input terminal of the second voltage regulator is connected to the output terminal of the power conversion unit 101, and its output terminal is connected to the second input terminal of the second comparator 1022.

[0041] In one example embodiment of this disclosure, the values ​​of the first reference voltage and the second reference voltage may be the same. The specific values ​​of the first reference voltage and the second reference voltage can be customized according to user needs, and are not specifically limited in this example embodiment.

[0042] This disclosure also provides a power-down protection method, which can be applied to a power-down protection circuit connected to a non-volatile memory 104. The power-down protection circuit includes a power conversion unit 101, a voltage comparison unit 102, an energy storage unit 107, and a processor 103. The input terminal of the power conversion unit 101 is connected to a voltage source 105, and the output terminal is connected to the processor 103. The energy storage unit 107 is connected to the processor 103. (Refer to...) Figure 5 As shown, the above power failure protection method may include the following steps:

[0043] In step S510, when the voltage of the voltage source is less than the first reference voltage, the voltage comparison unit sends a first interrupt signal to the processor.

[0044] In step S520, the processor controls the communication state with the non-volatile memory according to the first interrupt signal.

[0045] In this example of real-time mode, the power-loss protection circuit has already been described in detail above, so it will not be repeated here.

[0046] The following is a detailed explanation of each of the above steps.

[0047] In step S510, when the voltage of the voltage source is less than the first reference voltage, the voltage comparison unit sends a first interrupt signal to the processor.

[0048] In this example implementation, refer to Figure 2 As shown, the voltage comparison unit 102 may include a first comparator 1021, wherein the first input terminal of the first comparator 1021 is connected to the input terminal of the power conversion unit 101, the second input terminal is connected to the first reference power supply, and the output terminal of the first comparator 1021 is connected to the processor 103.

[0049] When the voltage of the voltage source 105 is greater than the first reference voltage, the first comparator 1021 outputs a high level, and the processor 103 maintains normal interaction with the non-volatile memory 104. When the voltage of the voltage source 105 is less than the first reference voltage, the first comparator 1021 outputs a low level, i.e., a first interrupt signal.

[0050] In step S520, the processor controls the communication state with the non-volatile memory 104 according to the first interrupt signal.

[0051] The processor 103 prohibits write operations to the non-volatile memory. The content being written can be completed by the power storage unit 107 connected to the processor 103, which can protect the data in the non-volatile memory 104.

[0052] In one exemplary embodiment of this disclosure, when the voltage at the output terminal of the power conversion unit 101 is less than the second reference voltage, the voltage comparison unit 102 sends a second interrupt signal to the processor 103. At this time, the processor 103 controlling the communication state with the non-volatile memory 104 according to the first interrupt signal may include the processor 103 controlling the communication state with the non-volatile memory 104 according to both the first and second interrupt signals. (Refer to...) Figure 6 As shown, the specific steps may include:

[0053] Step S610: The processor obtains the time difference between the first interrupt signal and the second interrupt signal;

[0054] Step S620: Determine the upper time limit and the lower time limit based on the total power consumption of the processor and the non-volatile memory;

[0055] Step S630: Determine the communication status based on the time difference, the upper time limit, and the lower time limit.

[0056] The following is an explanation of each of the above steps.

[0057] In step S610, the processor obtains the time difference between the first interrupt signal and the second interrupt signal.

[0058] In this example of real-time mode, the processor can record the time points when the first interrupt signal and the second interrupt signal are received, and then determine the time difference between the first interrupt signal and the second interrupt signal based on the aforementioned time points.

[0059] In step S620, the upper time limit and the lower time limit are determined based on the total power consumption of the processor and the non-volatile memory;

[0060] In this example embodiment, the total power consumption of the processor 103 and the non-volatile memory 104 can be determined first, and the upper and lower time limits can be calculated respectively. The upper time limit represents the time required for the processor 103 and the non-volatile memory 104 to complete the interaction, and the lower time limit represents the time required for the processor 103 and the non-volatile memory 104 to complete the interaction of a minimum unit.

[0061] In step S630, the communication status is determined based on the time difference, the upper time limit, and the lower time limit.

[0062] In this example implementation, if the time difference is less than the lower time limit, the processor 103 drives the write protection WP of the non-volatile memory 104 through the general purpose input / output interface GPIO; if the time difference is greater than the lower time limit and less than or equal to the upper time limit, the write operation of the non-volatile memory 104 is prohibited; if the time difference is greater than the upper time limit, the write operation of the non-volatile memory 104 is maintained.

[0063] The power-down protection circuit and method provided in this disclosure determine whether the voltage of the voltage source 105 can meet the operating requirements of the processor 103 and the non-volatile memory 104 through the voltage comparison unit 102. When the voltage of the voltage source 105 is less than the first reference voltage, a first interrupt signal is sent to the processor 103. That is, when the voltage of the voltage source 105 cannot meet the operating requirements of the processor 103 and the non-volatile memory 104, a signal is sent to the processor 103 so that the processor 103 can control the communication state with the non-volatile memory 104, thus avoiding data loss caused by accidental power failure. Furthermore, when a power failure occurs during data transmission, the energy storage unit 107 connected to the processor 103 can provide the processor 103 and the non-volatile memory 104 with a voltage that meets the conditions, so that the processor 103 and the non-volatile memory 104 can complete the currently executed interaction, further improving data security.

[0064] Furthermore, the interaction state of the processor 103 and the non-volatile memory 104 is determined by the first interrupt signal and the second interrupt signal, respectively. This can protect the data and avoid misoperation. That is, when the power loss time is short, the interaction state of the processor 103 and the non-volatile memory 104 can be maintained, thereby improving the data interaction efficiency.

[0065] This disclosure also provides an electronic device that may include the aforementioned power-off protection circuit. The specific structure of the power-off protection circuit has been described in detail above, and therefore will not be repeated here.

[0066] In this example embodiment, the electronic device described above may include, but is not limited to, a computer, a tablet computer, a mobile phone, a smartwatch, etc.

[0067] The following is based on Figure 7 Taking a mobile terminal 700 as an example, the construction of this electronic device will be described by way of example. Those skilled in the art will understand that, apart from components specifically designed for mobile purposes, Figure 7 The structure can also be applied to fixed types of equipment.

[0068] like Figure 7 As shown, the mobile terminal 700 may specifically include: a processor 701, a memory 702, a bus 703, a mobile communication module 704, an antenna 1, a wireless communication module 705, an antenna 2, a display screen 706, a camera module 707, an audio module 708, a power module 709, and a sensor module 710.

[0069] Processor 701 may include one or more processing units, such as: AP (Application Processor), modem processor, GPU (Graphics Processing Unit), ISP (Image Signal Processor), controller, encoder, decoder, DSP (Digital Signal Processor), baseband processor and / or NPU (Neural-Network Processing Unit), etc.

[0070] The processor 701 can be connected to the memory 702 or other components via the bus 703.

[0071] The memory 702 can be used to store computer executable program code, which includes instructions. The processor 701 executes various functional applications and data processing of the mobile terminal 700 by running the instructions stored in the memory 702. The memory 702 can also store application data, such as images, videos, and other files. Figure 7 The processor 701 in Figure 1 The processor 103 in the text is the same component.

[0072] The communication function of the mobile terminal 700 can be implemented through a mobile communication module 704, antenna 1, a wireless communication module 705, antenna 2, a modem processor, and a baseband processor. Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. The mobile communication module 704 can provide 2G, 3G, 4G, and 5G mobile communication solutions for use on the mobile terminal 700. The wireless communication module 705 can provide wireless communication solutions such as wireless LAN, Bluetooth, and near-field communication for use on the mobile terminal 700.

[0073] The display screen 706 is used to implement display functions, such as displaying the user interface, images, and videos. The camera module 707 is used to implement shooting functions, such as capturing images and videos. The audio module 208 is used to implement audio functions, such as playing audio and capturing voice. The power module 209 is used to implement power management functions, such as charging the battery, supplying power to the device, and monitoring battery status. The sensor module 710 may include a depth sensor 7101, a pressure sensor 7102, a gyroscope sensor 7103, a barometric pressure sensor 7104, etc., to implement corresponding sensing and detection functions.

[0074] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0075] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0076] It should be noted that the computer-readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0077] In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0078] Furthermore, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0079] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0080] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A power-loss protection circuit, applied to a non-volatile memory, characterized in that, include: processor; The power conversion unit has its input terminal connected to a voltage source and its output terminal connected to the processor. A voltage comparison unit, connected between the voltage source and the processor, is used to send a first interrupt signal to the processor when the voltage of the voltage source is less than a first reference voltage; and the voltage comparison unit is also connected to the output terminal of the power conversion unit, used to send a second interrupt signal to the processor when the voltage at the output terminal of the power conversion unit is less than a second reference voltage; An energy storage unit is connected to the processor; The processor is configured to control the communication state with the non-volatile memory based on the first interrupt signal, and to control the communication state with the non-volatile memory based on the first interrupt signal and the second interrupt signal. The processor acquires the time difference between the first interrupt signal and the second interrupt signal, determines an upper time limit and a lower time limit based on the total power consumption of the processor and the non-volatile memory, and determines the communication state based on the time difference, the upper time limit, and the lower time limit. Specifically, if the time difference is less than the lower time limit, the processor drives write protection of the non-volatile memory through a general-purpose input / output interface; if the time difference is greater than the lower time limit but less than or equal to the upper time limit, write operations to the non-volatile memory are prohibited; if the time difference is greater than the upper time limit, write operations to the non-volatile memory are maintained. The processor records the time point when it receives the first interrupt signal and the time point when it receives the second interrupt signal, and determines the time difference based on the two time points; the total power consumption is the sum of the power consumption of the processor and the power consumption of the non-volatile memory; the upper time limit is the time required for the processor and the non-volatile memory to complete one complete data interaction; and the lower time limit is the time required for the processor and the non-volatile memory to complete one smallest data unit interaction.

2. The power-off protection circuit according to claim 1, characterized in that, The voltage comparison unit includes: The first comparator has a first input terminal connected to the input terminal of the power conversion unit, a second input terminal connected to the first reference voltage source, and an output terminal connected to the processor. Wherein, the output voltage of the first reference voltage source is the first reference voltage.

3. The power-off protection circuit according to claim 1, characterized in that, The voltage comparison unit further includes: The second comparator has a first input terminal connected to the input terminal of the power conversion unit, a second input terminal connected to the second reference voltage source, and an output terminal connected to the processor. The output voltage of the second reference voltage source is the second reference voltage.

4. The power-off protection circuit according to claim 1, characterized in that, The energy storage unit is also connected to the output terminal of the power conversion unit.

5. A power-down protection method, applied to a power-down protection circuit connected to a non-volatile memory, the power-down protection circuit including a power conversion unit, a voltage comparison unit, an energy storage unit, and a processor; The input terminal of the power conversion unit is connected to a voltage source, and the output terminal is connected to the processor; The energy storage unit is connected to the processor; the method includes: When the voltage of the voltage source is less than the first reference voltage, the voltage comparison unit sends a first interrupt signal to the processor; when the output voltage of the power conversion unit is less than the second reference voltage, the voltage comparison unit sends a second interrupt signal to the processor. The processor acquires the time difference between the first interrupt signal and the second interrupt signal, wherein the processor records the time point at which the first interrupt signal is received and the time point at which the second interrupt signal is received, and determines the time difference based on the two time points; The upper and lower time limits are determined based on the total power consumption of the processor and the non-volatile memory, wherein the total power consumption is the sum of the power consumption of the processor and the power consumption of the non-volatile memory, the upper time limit is the time required for the processor and the non-volatile memory to complete one complete data interaction, and the lower time limit is the time required for the processor and the non-volatile memory to complete one minimum data unit interaction. The communication state is determined based on the time difference, the upper time limit, and the lower time limit. Specifically, if the time difference is less than the lower time limit, the processor drives write protection of the non-volatile memory via a general-purpose input / output interface; if the time difference is greater than the lower time limit but less than or equal to the upper time limit, write operations to the non-volatile memory are prohibited; and if the time difference is greater than the upper time limit, write operations to the non-volatile memory are maintained. When the processor receives the first interrupt signal, it disables write operations to the non-volatile memory.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the power-down protection method as described in claim 5.

7. An electronic device, characterized in that, include: The claim requires the power-off protection circuit described in any one of claims 1 to 4.

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