Methods for forming semiconductor devices

Abstract

A method for forming a semiconductor device includes: depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming a first spacer on the first mandrel and a second spacer on the second mandrel; and selectively removing the second spacer while masking the first spacer. Masking the first spacer includes covering the first spacer with a capping layer over the second mask and the second mask, wherein the capping layer comprises carbon. The method further includes patterning the first mask and transferring the pattern of the first mask to the target layer. Patterning the first mask includes masking the first mask with the second mandrel, the first mandrel, and the first spacer.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] As semiconductor devices shrink further, various processing techniques (e.g., photolithography) are adapted to manufacture devices of increasingly smaller dimensions. For example, as gate density increases, the fabrication processes for individual components within the device (e.g., interconnect components) are adapted to be compatible with the overall miniaturization of the device components. However, as semiconductor processes have increasingly smaller process windows, the fabrication of these devices has approached and even exceeded the theoretical limits of photolithography equipment. As semiconductor devices continue to shrink, the desired spacing (i.e., pitch) between device elements is smaller than the spacing that can be fabricated using conventional optical masks and photolithography equipment. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor device, comprising: depositing a first mask over a first region of a target layer and a second region of the target layer; forming a plurality of mandrels over the first mask; forming a plurality of spacers on the sidewalls of the plurality of mandrels; depositing a second mask over the plurality of mandrels and the plurality of spacers; forming a capping layer over the second mask, wherein the capping layer comprises carbon; and patterning the second mask and the capping layer to expose a first mandrel of the plurality of mandrels and a first spacer of the plurality of spacers, the first mandrel and the first spacer overlapping the first region of the target layer.

[0004] Other embodiments of this application provide a method for forming a semiconductor device, comprising: depositing a first hard mask over a target layer; forming a first mandrel and a second mandrel over the first hard mask; forming a first spacer on a sidewall of the first mandrel and a second spacer on a sidewall of the second mandrel; depositing an oxide layer over the first mandrel, the second mandrel, the first spacer, and the second spacer; forming a carbon-containing capping layer over the oxide layer; patterning the carbon-containing capping layer to expose the oxide layer; patterning the oxide layer to expose the second mandrel and the second spacer while masking the first spacer and the first mandrel with the carbon-containing capping layer; removing the second spacer; after removing the second spacer, removing the remaining portion of the carbon-containing capping layer and the oxide layer; transferring the pattern of the first spacer, the first mandrel, and the second mandrel to the first hard mask; and using the first hard mask as a mask to pattern the target layer.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming a first spacer on the first mandrel and a second spacer on the second mandrel; selectively removing the second spacer while masking the first spacer, wherein masking the first spacer comprises covering the first spacer with a second mask and a capping layer over the second mask, and wherein the capping layer has at least 30% carbon; patterning the first mask, wherein patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacer; and transferring the pattern of the first mask to the target layer. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 Cross-sectional and perspective views of various intermediate stages in the manufacture of semiconductor devices according to various embodiments are shown.

[0008] Figure 21 , Figure 22 and Figure 23 Cross-sectional and perspective views of various intermediate stages of manufacturing a semiconductor device according to various other embodiments are shown.

[0009] Figure 24 and Figure 25 Cross-sectional and perspective views of various intermediate stages of manufacturing a semiconductor device according to various other embodiments are shown.

[0010] Figure 26 and Figure 27Cross-sectional and perspective views of various intermediate stages of manufacturing a semiconductor device according to various other embodiments are shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] Regarding a specific patterning process, namely self-aligned double patterning (SADP), various embodiments are described, wherein a mandrel is patterned, spacers are formed along the sidewalls of the mandrel, and at least a portion of the mandrel is removed, leaving the spacers to define a pattern at half the spacing of the mandrel. However, the embodiments may be adapted to other patterning processes, such as self-aligned quadruple patterning (SAQP), etc.

[0014] According to some embodiments, semiconductor devices and methods are provided. Specifically, a self-aligned dual patterning process is implemented to pattern components (e.g., semiconductor fins, gate structures, wires, etc.) into a target layer of the semiconductor device. At least some of the patterned components have a pitch of at least half of the minimum pitch achievable using photolithography. The patterned components may include components patterned using mandrels, spacers, and / or combinations thereof described above. Specifically, different combinations of mandrels and spacers may be used to pattern different regions of the target layer to achieve patterned components with different sizes and / or spacings.

[0015] Mandrels and spacers can be selectively removed from different regions above the target layer, depending on the desired resulting part size in the target layer. To achieve selective removal, one or more masks can be deposited over the mandrels and spacers. In various embodiments, a carbon-rich layer can be deposited over the spacers (e.g., between different masks) to reduce etch damage (e.g., spacer material loss) due to selective removal of the mandrels and / or spacers. Therefore, mandrels and spacers of the desired size can be precisely patterned, and critical size control when patterning the target layer can be improved.

[0016] Figures 1 to 19 A cross-sectional view is shown of an intermediate stage in forming components in a target layer 104 of a semiconductor device 100 according to some exemplary embodiments. According to embodiments of the invention, the target layer 104 is a layer in which multiple patterns will be formed. In some embodiments, the semiconductor device 100 is processed as part of a larger wafer. In such embodiments, after the various components of the semiconductor device 100 (e.g., active devices, interconnect structures, etc.) are formed, a dicing process can be applied to a scribe region of the wafer to separate individual semiconductor dies from the wafer (also referred to as dicing).

[0017] In some embodiments, target layer 104 is a semiconductor substrate. The semiconductor substrate may include doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Target layer 104 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate may be patterned using the processes described in the embodiments, and subsequent process steps may be used to form shallow trench isolation (STI) regions in the substrate. Semiconductor fins may protrude from between the formed STI regions. Source / drain regions may be formed in the semiconductor fins, and a gate dielectric layer and a gate electrode layer may be formed over the channel regions of the fins to form a semiconductor device, such as a fin field-effect transistor (finFET).

[0018] In some embodiments, the target layer 104 is a blanket-deposited conductive layer, such as a metal layer or a polysilicon layer. An embodiment patterning process may be applied to the target layer 104 to pattern the semiconductor gate and / or dummy gate of the finFET. By using the embodiment process to pattern the conductive target layer 104, the spacing between adjacent gates can be reduced and the gate density can be increased. In such embodiments, the target layer 104 may be formed over a semiconductor substrate, for example, as described above.

[0019] In some embodiments, the target layer 104 is an intermetallic dielectric (IMD) layer. In such embodiments, for example, the target layer 104 comprises a low-k dielectric material having a dielectric constant (k-value) below 3.8, below about 3.0, or below about 2.5. In alternative embodiments, the target layer 104 is an IMD layer comprising a high-k dielectric material having a k-value above 3.8. Openings can be patterned in the target layer 104 using the processes described in the embodiments, and wires and / or vias can be formed in the openings. In such embodiments, the target layer can be formed over a semiconductor substrate (e.g., as described above), and devices such as transistors, diodes, capacitors, resistors, etc., can be formed in and / or on the active surface of the semiconductor substrate.

[0020] Device 100 includes three regions 100A, 100B, and 100C. Different types of devices and / or devices with different geometries (e.g., dimensions) can be formed in each of the three regions 100A, 100B, and 100C. For example, region 100A can be processed to form a component (e.g., a semiconductor fin) of a first width in target layer 104; region 100B can be processed to form a component of a second width in target layer 104 greater than the first width; and region 100C can be processed to form a component of a third width in target layer 104 greater than the first width but less than the second width. For example, the first width can be less than about 15 nm; the second width can be greater than about 15 nm to about 30 nm; and the third width can be in the range of about 15 nm to about 30 nm. In some embodiments, n-type devices can be formed in regions 100A and 100C, while p-type devices can be formed in region 100B. In other embodiments, devices of other component sizes and / or types can be formed in different regions of device 100. Furthermore, although regions 100A, 100B, and 100C are shown as directly adjacent to each other, any number of intermediate components and / or gaps may be provided between each of regions 100A, 100B, and 100C.

[0021] An adhesive layer 102 is deposited over the target layer 104. The adhesive layer 102 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In some embodiments, the adhesive layer 102 can serve as an adhesive layer and can also serve as an etch stop layer during subsequent fin formation. Although Figure 1 The adhesive layer 102 is shown to be in physical contact with the target layer 104, but any number of interlayers can be disposed between the adhesive layer 102 and the target layer 104.

[0022] The film stack also includes a hard mask layer 106 formed over the adhesive layer 102. The hard mask layer 106 may be formed of a material that can be selectively etched compared to the adhesive layer 102. For example, in embodiments where the adhesive layer 102 comprises an oxide, the hard mask layer 106 may be a nitride, such as silicon nitride. The hard mask layer 106 may be deposited, for example, by PVD, CVD, ALD, etc. In some embodiments, the hard mask layer 106 may have, for example, approximately to approximately The thickness is within the range.

[0023] The film stack also includes a hard mask 108 above the hard mask layer 106. In some embodiments, the hard mask 108 may include a material that can be selectively etched compared to the hard mask layer 106. For example, in embodiments where the hard mask layer 106 comprises a nitride, the multilayer hard mask 108 may comprise an oxide. Specifically, in some embodiments, the hard mask layer 108 includes silicon oxide (e.g., SiO2, etc.), silicon oxynitride (SiON), silicon carbonitride (SiOCN), combinations thereof, etc. For example, the hard mask layer 108 may be deposited by PVD, CVD, ALD, etc.

[0024] The film stack also includes a core layer 112 formed over the hard mask 108. The core layer 112 may include silicon (e.g., amorphous silicon). The core layer 112 can be deposited using any suitable process, such as ALD, CVD, PVD, etc.

[0025] Three layers of photoresist 120 are formed on a film stack above the core layer 112. The three layers of photoresist 120 include a bottom layer 114, an intermediate layer 116 above the bottom layer 114, and an upper layer 118 above the intermediate layer 116. The bottom layer 114 and the upper layer 118 may be formed of a photoresist comprising organic materials (e.g., a photosensitive material). In some embodiments, the bottom layer 114 may also be a bottom antireflective coating (BARC) layer. The intermediate layer 116 may comprise an inorganic material, which may be a nitride (such as silicon nitride), an oxide oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 116 has high etch selectivity relative to the upper layer 118 and the bottom layer 114. The individual layers of the three layers of photoresist 120 may be deposited sequentially using, for example, a spin-coating process. While three layers of photoresist 120 have been discussed herein, in other embodiments, the photoresist 120 may be a single-layer or double-layer (e.g., comprising only the bottom layer 114 and the upper layer 118 without the intermediate layer 116) photoresist. The type of photoresist used (e.g., single-layer, double-layer, or triple-layer) can depend on the photolithography process used to pattern the core layer 112. For example, in advanced extreme ultraviolet (EUV) lithography processes, single-layer or double-layer photoresist 120 can be used.

[0026] In some embodiments, the upper layer 118 is patterned using a photolithography process. Subsequently, the upper layer 118 is used as an etching mask for patterning the intermediate layer 116 (see...). Figure 2 Then the intermediate layer 116 is used as an etch mask for patterning the bottom layer 114, and then the bottom layer 114 is used for patterning the mandrel layer 112 (see...). Figure 3 and Figure 4 It has been observed that by using a three-layer photoresist (e.g., three-layer photoresist 120) to etch a target layer (e.g., a core layer 112), improved clarity of fine-pitch patterns can be achieved in the target layer (e.g., a core layer 112).

[0027] The upper layer 118 is patterned using any suitable photolithography process to form openings 122 therein. As an example of patterning openings 122 in the upper layer 118, a photomask can be placed above the upper layer 118. The upper layer 118 can then be exposed to radiation beams, including ultraviolet (UV) or excimer lasers, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, while the photomask masks areas of the upper layer 118. An immersion lithography system can be used to expose the top photoresist layer to increase resolution and reduce the minimum achievable pitch. A baking or curing operation can be performed to harden the upper layer 118, and a developer can be used to remove exposed or unexposed portions of the upper layer 118, depending on whether a positive or negative resist is used.

[0028] After patterning the upper layer 118, the pattern of the upper layer 118 is transferred to the intermediate layer 116 in an etching process. The etching process is anisotropic, such that the openings 122 in the upper layer 118 extend through the intermediate layer 116 and have approximately the same size in the intermediate layer 116 as they do in the upper layer 118. The resulting structure... Figure 2 As shown in the image.

[0029] Optionally, a trimming process can be implemented to increase the size of the opening 122 in the intermediate layer 116. In an embodiment, the trimming process is an anisotropic plasma etching process using a process gas, including O2, CO2, N2 / H2, H2, etc., combinations thereof, or any other gas suitable for trimming the intermediate layer 116.

[0030] exist Figure 3In this process, an etching process is performed to transfer the pattern of intermediate layer 116 to bottom layer 114, thereby causing openings 122 to extend through bottom layer 114. The etching process of bottom layer 114 is anisotropic, such that the openings 122 in intermediate layer 116 extend through bottom layer 114 and have approximately the same size in intermediate layer 116 as they do in bottom layer 114. As part of etching bottom layer 114, upper layer 118 (see...) can be consumed. Figure 1 and Figure 2 ).

[0031] exist Figure 4 In the middle, an etching process is used to remove the bottom layer 114 (see Figure 3 The pattern is transferred to the mandrel layer 112. The etching process of the mandrel layer 112 is anisotropic, such that the openings 122 in the underlayer 114 extend through the mandrel layer 112. The openings 122 in the mandrel layer 112 have approximately the same width as they in the underlayer 114. The etching can be dry etching (e.g., plasma etching), etc.

[0032] When the mandrel layer 112 is patterned, the layer directly beneath the mandrel layer 112 (e.g., hard mask 108) can be used as an etch stop layer. Specifically, the etching process can use an etchant that selectively etches the mandrel layer 112 without significantly etching the hard mask layer 108. For example, in embodiments where the mandrel layer 112 comprises silicon and the hard mask layer comprises silicon oxide, the etching process can use HBr, CF4, Cl2, NF3, etc., as etchants.

[0033] Therefore, the mandrel 124 is defined by the remainder of the mandrel layer 112 (e.g., the portion of the mandrel layer 112 located between the openings 122). As shown, the mandrel 124 may have varying dimensions in each of regions 100A, 100B, and 100C, which may correspond to the desired dimensions and / or spacing of components subsequently patterned in the target layer 104. For example, mandrels 124A and 124C in regions 100A and 100C may be thinner than mandrel 124B in region 100B. In other embodiments, the mandrel 124 in each of regions 100A, 100B, and 100C may have different relative dimensions. For example, in other embodiments, mandrel 124C in region 100C may be wider than mandrel 124A but thinner than mandrel 100A. During etching of the mandrel layer 112, the intermediate layer 116 is consumed, and the underlying layer 114 may be at least partially consumed.

[0034] In embodiments where the mandrel layer 112 is etched simultaneously without completely consuming the underlayer 114, an ashing process may be performed to remove any remaining residue of the underlayer 114. The ashing process may include oxygen plasma stripping, which exposes the mandrel 124 to oxygen plasma.

[0035] exist Figure 5In this process, a spacer layer 126 is formed above and along the sidewalls of the mandrel 124. The spacer layer 126 may also extend along the top surface of the hard mask 108 within the opening 122. The material of the spacer layer 126 is chosen to have high etch selectivity relative to the hard mask layer 108 and the mandrel 124. For example, the spacer layer 126 may include SiN, SiCON, SiON, metal, metal alloy, etc., and can be deposited using any suitable process such as ALD, CVD, etc. In some embodiments, the deposition process of the spacer layer 126 is conformal, such that the thickness of the spacer layer 126 on the sidewalls of the mandrel 124 is substantially equal to the thickness of the spacer layer 126 on the top surface of the mandrel 124 and the bottom surface of the opening 122 (e.g., within manufacturing tolerances).

[0036] exist Figure 6 In this process, spacer layer 126 is patterned to remove the lateral portions of spacer layer 126 while leaving spacer layer 128 on the sidewalls of mandrel 124. Spacer layer 126 is etched to expose mandrel 124 and portions of the layer located below mandrel 124 (e.g., hard mask 108). Patterning spacer layer 126 may include a dry etching process that selectively etches spacer layer 126 at a rate higher than that of mandrel 124. Exemplary etchants used for etching spacer layer 126 may include fluorine reactive gases such as CF4, NF3, HCl, HBr, etc. Other process gases may be used in combination with etchants, such as oxygen (O2), nitrogen (N2), argon (Ar), combinations thereof, etc. The dry etching process may be anisotropic and etches the exposed, lateral portions of spacer layer 126 while leaving vertical portions of spacer layer 126 (spacer 128) on mandrel 124.

[0037] exist Figure 7 In this process, a mask 150 is formed above and along the sidewalls of the mandrel 124 and spacer 126. The mask 150 may also extend along the top surface of the hard mask 108 within the opening 122. The material of the mask 150 is chosen to provide high etch selectivity for the overlay subsequently formed over the mandrel 124 and spacer 126 (see, for example...). Figure 8 For example, mask 150 may include silicon oxide, etc., and can be deposited using any suitable process such as ALD, CVD, etc.

[0038] The deposition process of mask 150 can be conformal, such that the thickness of spacer layer 126 on the sidewalls of spacer 126 is substantially equal to the thickness of spacer layer 126 on the top surface of mandrel 124 and the bottom surface of opening 122 (e.g., within manufacturing tolerances). In some embodiments, deposition mask 150 may include a first carbon-containing precursor and oxygen (e.g., O2, N2O, CO2, etc.) flowing in an ALD deposition chamber. For example, the first carbon-containing precursor may be bis(diethylamino)silane, SiH4, SiH2Cl2, etc., and the first carbon-containing precursor may be a compound having a carbon-nitrogen ratio of 4:1. For example, the first carbon-containing precursor and oxygen react to form a silicon oxide monolayer on the exposed surface of device 100. The first carbon-containing precursor and oxygen may be cyclically pulsed and purged, with RF power (e.g., in the range of about 200W to 800W) applied between each pulse and purge cycle. The RF power may improve the surface conditions of each atomic monolayer to facilitate the growth of the monolayer during subsequent ALD processes.

[0039] exist Figure 8 In this process, a capping layer 152 is formed on mask 150. Capping layer 152 can be a pure carbon layer or a carbon-rich composite layer (e.g., a SiOCN layer, a SiOC layer, etc.). For example, the carbon concentration of capping layer 152 can be at least 30%, which advantageously allows capping layer 152 to adequately protect the underlying spacer 128 during subsequent processing steps (e.g., subsequent etching steps to selectively remove spacer 128 and / or mandrel 126). It has been observed that a sufficiently high carbon concentration improves etch resistance compared to the material of mask 150. For example, the wet etching rate of capping layer 152 using diluted hydrogen fluoride (dHF) can be two times or more slower than that of mask 150.

[0040] In some embodiments, the cover layer 152 may have a thickness of less than about 2 nm, such as in about to approximately or about to approximately Within this range. It has been observed that advantages can be achieved by forming the cover layer 152 within the above thickness range. For example, forming a thickness of less than approximately The capping layer 152 may provide insufficient protection to the underlying components (e.g., spacer 128) during subsequent etching steps, leading to damage to the underlying components. Furthermore, forming a capping layer 152 with a thickness greater than about 2 nm may increase the difficulty of removing the capping layer 152, especially in areas with small critical dimensions, resulting in unwanted capping layer residues remaining in subsequent processing steps.

[0041] In some embodiments, capping layer 152 is formed in situ with mask 150. For example, capping layer 152 may be formed in the same process chamber as mask 150 without any vacuum interruption. In such embodiments, forming capping layer 152 may include shutting off oxygen flow into the process chamber while a second carbon-containing precursor flows in the deposition chamber to deposit a monolayer of pure carbon or a monolayer of a carbon-rich composite material (e.g., having a carbon concentration greater than 30%). In some embodiments, the second carbon-containing precursor used for depositing capping layer 152 may be the same as the first carbon-containing precursor described above that flows during deposition of mask 150. For example, the second carbon-containing precursor may be bis(diethylamino)silane, SiH4, SiH2Cl2, etc., and the second carbon-containing precursor may be a compound having a carbon-nitrogen ratio of 4:1. In other embodiments, the second carbon-containing precursor may be a different compound from the first carbon-containing precursor used for deposition of mask 150. Furthermore, the second carbon-containing precursor may have a larger carbon-nitrogen ratio than the first carbon-nitrogen precursor. Furthermore, the deposited capping layer 152 may optionally include one or more additional carbon-containing precursors (e.g., tetraethoxysilane (TEOS), methyl orthosilicate, etc.) flowing simultaneously with the second carbon-containing precursor. By controlling the carbon ratio of the second carbon-containing precursor and / or the flow of one or more additional carbon-containing precursors, the carbon concentration of the capping layer 152 can be adjusted to a desired level. In other embodiments, different processes can be used to form the capping layer 152, such as ex-situ deposition processes, wherein the capping layer 152 is formed in a process chamber different from that of the mask 150.

[0042] exist Figure 9 In this process, photoresist 154 is deposited over a capping layer 152 in regions 100A, 100B, and 100C. For example, photoresist 154 can be deposited using a spin-coating process. Although photoresist 154 is shown as a single layer, in some embodiments, photoresist 154 may have a similar structure to that described above. Figure 1 The three-layer structure of the three-layer photoresist 120 described in the paper.

[0043] exist Figure 10In this embodiment, a patterned photoresist 154 and a capping layer 152 are used to expose a mask 150 in region 100C. The patterned photoresist 154 can be implemented using a photolithography process. For example, the photoresist 154 can be exposed and developed to remove the photoresist 154 from region 100C, while leaving the photoresist 154 in regions 100A and 100B. Furthermore, in embodiments where the photoresist 154 has a three-layer structure, the patterned photoresist 154 may also include a suitable etching process as described above with respect to patterned photoresist 120. In some embodiments, removing the photoresist 154 from region 100C may include an O2 ashing process, which further removes the capping layer 152 from region 100C. The remaining portions of the photoresist 154 in regions 100A and 100B may be covered portions of the capping layer 152, such that the capping layer 152 is also retained in regions 100A and 100B.

[0044] exist Figure 11 In this process, mask 150 is selectively removed from region 100C. Patterned mask 150 can be implemented using a wet etching process employing photoresist 154 and capping layer 152 as masks. The wet etching process can use dHF or similar etchants. Therefore, mandrel 124 and spacer 128 are exposed in region 100C. In various embodiments, capping layer 152 protects spacer 128 in regions 100A and 100B while patterning mask 150. For example, a wet etchant (e.g., dHF) used to etch mask 150 tends to penetrate photoresist 154 and etch mask 150 in regions 100A and 100B, resulting in damage to spacer 128 (e.g., material loss). As described above, the capping layer 152 (e.g., a carbon-rich material) is etch-resistant to this etchant (e.g., dHF), and the capping layer 150 provides an additional protective layer in regions 100A and 100B to reduce damage to the spacer 128 (e.g., reduce material loss in the spacer 128). Therefore, patterning accuracy can be improved. Furthermore, in subsequent processing steps, the spacer 128 can be removed from region 100C, and damage to the spacer 128 in region 100C due to the patterning mask 150 does not result in a reduction in patterning control.

[0045] exist Figure 12In this process, the remaining portions of photoresist 154 and capping layer 152 are removed from regions 100A and 100B by etching. Removal of photoresist 154 and capping layer 152 may include a cleaning process using a high-temperature sulfur peroxide mixture (HTSPM), for example, which removes photoresist 154 and capping layer 152. Thus, mask 150 is exposed in regions 100A and 100B. Alternatively, a relatively fast cleaning process using dHF (e.g., a duration of less than 30 seconds) may be implemented to clean the exposed surfaces of mask 150 without damaging the underlying spacer 128. Cleaning can facilitate the removal of residual photoresist 154 from the surface of mask 150.

[0046] exist Figure 13 In this process, a suitable etching process is used to remove spacer 128 from region 100C. This suitable etching process selectively removes spacer 128 without removing mask 150. In some embodiments, H3PO4, ozone, etc., can be used as etchants to remove spacer 128 from region 100C. Spacer 128 in regions 100A and 100C is masked by mask 150 and is not removed.

[0047] exist Figure 14 In this process, mask 150 is removed from regions 100A and 100B by an etching process. In some embodiments, mask 150 (e.g., oxide) can be removed using an etching process that etches mask 150 at a lower rate than the underlying hard mask layer 106 (e.g., nitride layer). For example, the etching process for removing mask 150 uses dHF or the like as an etchant. Other etching processes can be used in other embodiments.

[0048] exist Figure 15 In this embodiment, photoresist 156 is deposited over spacer 138 and mandrel 124 in regions 100A, 100B, and 100C. For example, photoresist 156 can be deposited using a spin-coating process. Although photoresist 156 is shown as a single layer, in some embodiments, photoresist 156 may have a similar structure to that described above. Figure 1 The three-layer structure of the three-layer photoresist 120 described in the text. For example... Figure 15 As further shown, the photoresist 156 can be patterned to expose the spacer 128 and mandrel 124 in region 100A. The patterned photoresist 156 can be implemented using suitable photolithography and / or etching processes as described above (e.g., with regard to patterned photoresist 120).

[0049] exist Figure 16In this process, mandrel 124 is removed from region 100A. An etching process is used to remove mandrel 124. Because mandrel 124 and spacer 128 have etch selectivity with respect to the same etching process, mandrel 124 can be removed without removing spacer 128. Etching mandrel 124 exposes the underlying hard mask 108, which can be used as an etch stop layer. In some embodiments, etching mandrel 124 can reduce the height of spacer 128 without removing spacer 128. Removing mandrel 124 can include a dry etching process similar to that used for patterning mandrel 124, as described above. Figure 4 As described in [the document]. Subsequently, photoresist 156 undergoes an acceptable cleaning and / or O2 ashing process. The resulting structure is [details omitted]. Figure 17 As shown in the image.

[0050] exist Figure 18 In this process, spacers 128 and mandrels 124 are used as etching masks to etch the hard mask 108. Specifically, spacers 128 are used as masks to pattern the hard mask 108 in region 100A; a combination of spacers 128 and mandrels 124 is used as masks to pattern the hard mask 108 in region 100B; and mandrels 124 are used as masks to pattern the hard mask 108 in region 100C. Thus, by using different combinations of spacers 128 and / or mandrels 124, the hard mask 108 can be patterned to have different spacing and part sizes in each of regions 100A, 100B, and 100C.

[0051] In some embodiments, etching the hard mask 108 includes anisotropic dry etching and / or wet etching. For example, the hard mask 108 can be patterned by dry etching (e.g., using CF4, NF3, HCl, HBr, etc.), subsequent wet etching for byproduct removal (e.g., using diluted hydrogen fluoride (DHF), sulfur peroxide mixture (SPM), etc.), and cleaning processes for particle cleaning (e.g., Standard Clean 1 (SC-1), etc.). Etching the hard mask 108 may consume spacer 128.

[0052] Subsequently, Figure 19 In this process, a hard mask 108 is used as an etching mask to pattern openings 140 in the target layer 104, which may define fins 142. Etching the target layer 104 may include anisotropic dry etching and / or wet etching processes. The remainder of the target layer 104 may have [a specific characteristic / feature]. Figure 17 The spacers 128 and mandrel 124 have the same pattern. Because different combinations of spacers 128 and mandrel 124 are used as masks, different sizes and spacings of fins 142 can be achieved in target layers 104 in each of regions 100A, 100B and 100C.

[0053] Additional process steps can be applied to structure 100 to form a FinFET device. Figure 20 A finFET device is shown in a perspective view. In various embodiments, an isolation region can be deposited around fin 142, and the isolation region can then be recessed to expose the upper portion of fin 142. An opening can be patterned in the upper portion of fin 142, and epitaxial source / drain regions can be grown in the opening. Furthermore, a gate structure can be formed above and along the sidewalls of the upper portion of fin 142. The finFET includes fin 142, which can be configured according to the above... Figures 1 to 19 The fin 142 is patterned using the process described herein. The fin 142 is above and protrudes from between adjacent isolation regions 56. A gate dielectric layer 92 is located along the sidewall of the fin 52 and above its top surface, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are disposed on the opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94.

[0054] In the above embodiments, the target layer 104 is a single layer of material. In other embodiments, the target layer 104 may have a multilayer structure or a combination of single-layer / multilayer structures in different regions 100A, 100B or 100C.

[0055] For example, Figure 21 and Figure 22 An embodiment of a multilayer structure having alternating semiconductor layers 104A and 104B is shown. Semiconductor layer 104A may include a first semiconductor material, and semiconductor layer 104B may include a second semiconductor material that can be selectively etched compared to the first semiconductor material. For example, semiconductor layer 104A may include silicon, while semiconductor layer 104B may include silicon-germanium. Semiconductor layer 104B may then be removed, and semiconductor layer 104A may be patterned to form the channel region of a nanostructured transistor device. In some embodiments, the nanostructured transistor may be a nanowire transistor, a nanosheet transistor, an all-around gate transistor, etc.

[0056] Figure 21 It shows something similar to Figure 1 The initial device 200 of device 100, wherein the same reference numerals indicate the same components formed using the same process. Figure 22 This shows the use of the above regarding Figures 1 to 19A similar process is described to pattern the target layer 104 to define the device 200 after the fins 142. For example, different combinations of spacers and / or mandrels are used to define fins 142 of different sizes and spacings in different regions 100A, 100B, and 100C of the device 200. A carbon layer or carbon-rich layer can be used as a capping layer to protect the spacers in regions 100A and 100B while selectively removing the spacers from region 100C. Thus, improved patterning control of the fins 142 can be achieved.

[0057] Additional process steps can be applied to device 200 to form a nanostructured transistor device. For example, an isolation region can be deposited around the fin, and the isolation region can then be recessed to expose the upper part of the fin. An opening can be patterned in the upper part of the fin, and epitaxial source / drain regions can be grown in the opening. Furthermore, semiconductor layer 104A can be removed, and semiconductor layer 104B can be patterned to define a channel region. A gate structure can be formed around the channel region.

[0058] Figure 23 An example of a nanostructured transistor in a three-dimensional view according to some embodiments is shown. The nanostructured transistor includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) located above a fin on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanostructured transistor. The nanostructure 55 can be formed by patterning a semiconductor layer 104A. The nanostructure 55 can include p-type nanostructures, n-type nanostructures, or combinations thereof. An isolation region 68 is disposed between adjacent fins 66, which may be above and protrude from between adjacent isolation regions 68. Although the isolation region 68 is described / shown as separated from the substrate 50, as used herein, the term "substrate" can refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fin 66 is shown as being a single, continuous material with the substrate 50, the bottom of the fin 66 and / or the substrate 50 can include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0059] Figure 24 and Figure 25An alternative embodiment is shown where target layer 104 includes a multilayer structure (e.g., semiconductor layers 104A / 104B) embedded in semiconductor substrate 104C. The multilayer structure may be disposed in region 100B, and the multilayer structure may not extend into regions 100A or 100C. Semiconductor substrate 104C may include doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 104 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Figure 24 and Figure 25 The target layer 104 can be formed, for example, by patterning grooves in the semiconductor substrate 104C in region 100B using a combination of photolithography and etching. Next, semiconductor layers 104A and 104B can be alternately grown in the grooves of the semiconductor substrate 104C. Semiconductor layers 104A and 104B can be similar to those described above. Figure 21 and Figure 22 Those described.

[0060] Figure 24 It shows something similar to Figure 1 The initial device 300 of device 100, wherein the same reference numerals indicate the same components formed using the same process. Figure 25 This shows the use of the above regarding Figures 1 to 19 The described process patterning of target layer 104 to define device 300 after fin 142 is described. For example, different combinations of spacers and / or mandrels are used to define fins 142 of different sizes and spacings in different regions 100A, 100B, and 100C of device 300. A carbon layer or carbon-rich layer can be used as a capping layer to protect the spacers in regions 100A and 100B while selectively removing the spacers from region 100C. Fin 142 may have a monolithic composition in regions 100A and 100C, while fin 142 has a multilayer structure in region 100B (e.g., including semiconductor layers 104A and 104B). Additional process steps as described above can be applied to device 300 to form a nanostructured transistor device in region 100B and a FinFET transistor in regions 100A and 100C.

[0061] Target layer 104 can include a multi-layer structure in any of regions 100A, 100B, or 100C. For example, Figure 26 and Figure 27Device 400 is shown, wherein target layer 104 includes a multilayer structure (e.g., semiconductor layers 104A / 104B) embedded in semiconductor substrate 104C. The multilayer structure may be disposed in regions 100B and 100C, and the multilayer structure may not extend into region 100A.

[0062] Figure 26 It shows something similar to Figure 24 and Figure 25 The initial device 400 of device 300, wherein the same reference numerals indicate the same components formed using the same process. Figure 27 This shows the use of the above regarding Figures 1 to 19 The similar process described above patterns the target layer 104 to define the device 400 after the fin 142. For example, different combinations of spacers and / or mandrels are used to define fins 142 of different sizes and spacings in different regions 100A, 100B, and 100C of the device 400. A carbon layer or carbon-rich layer can be used as a capping layer to protect the spacers in regions 100A and 100B while selectively removing the spacers from region 100C. The fin 142 may have a monolithic composition in regions 100A and 100C, while the fin 142 has a multilayer structure in region 100B (e.g., including semiconductor layers 104A and 104B). Additional process steps as described above can be applied to the device 400 to form nanostructured transistor devices in regions 100B and 100C and a FinFET transistor in region 100A.

[0063] Various embodiments provide a dual patterning method in which spacers are formed on the sidewalls of a mandrel. The mandrel and spacers can be selectively removed from different regions above the target layer, depending on the desired resulting part size in the different regions of the target layer. To achieve selective removal, one or more masks can be deposited over the mandrel and spacers. In various embodiments, a carbon-rich layer can be deposited over the spacers (e.g., between different masks) to reduce etch damage (e.g., spacer material loss) due to selective removal of the mandrel and / or spacers. Therefore, mandrels and spacers of the correct dimensions can be patterned, and critical size control when patterning the target layer can be improved.

[0064] In some embodiments, the method includes: depositing a first mask over a first region of a target layer and a second region of the target layer; forming a plurality of mandrels over the first mask; forming a plurality of spacers on the sidewalls of the plurality of mandrels; depositing a second mask over the plurality of mandrels and the plurality of spacers; forming a capping layer over the second mask, wherein the capping layer comprises carbon; and patterning the second mask and the capping layer to expose a first mandrel among the plurality of mandrels and a first spacer among the plurality of spacers, the first mandrels and the first spacer overlapping the first region of the target layer. In some embodiments, the method further includes: removing the first spacer; after removing the first spacer, removing the remainder of the capping layer and the remainder of the second mask; after removing the remainder of the capping layer and the remainder of the second mask, patterning the first mask, wherein patterning the first mask includes transferring a pattern of the first mandrels to the first mask; and transferring a pattern of the first mask to the target layer. In some embodiments, patterning the first mask includes transferring a pattern of a second spacer to the first mask, wherein the second spacer comprises a plurality of spacers, and wherein the second spacer overlaps the second region of the target layer. In some embodiments, patterning the first mask includes transferring a pattern of a second mandrel to the first mask, wherein the second mandrel is disposed between second spacers. In some embodiments, the capping layer has a carbon concentration of at least 30%. In some embodiments, forming the capping layer includes forming the capping layer in the same process chamber as depositing the second mask. In some embodiments, depositing the second mask includes flowing a first carbon-containing precursor and oxygen over a plurality of spacers and a plurality of mandrels, wherein forming the capping layer includes flowing a second carbon-containing precursor over the second mask without flowing oxygen. In some embodiments, the second carbon-containing precursor is the same compound as the first carbon-containing precursor. In some embodiments, the second carbon-containing precursor is a different compound from the first carbon-containing precursor.

[0065] In some embodiments, the method includes: depositing a first hard mask over a target layer; forming a first mandrel and a second mandrel over the first hard mask; forming a first spacer on a sidewall of the first mandrel and a second spacer on a sidewall of the second mandrel; depositing an oxide layer over the first mandrel, the second mandrel, the first spacer, and the second spacer; forming a carbon-containing capping layer over the oxide layer; patterning the carbon-containing capping layer to expose the oxide layer; patterning the oxide layer to expose the second mandrel and the second spacer while masking the first spacer and the first mandrel with the carbon-containing capping layer; removing the second spacer; and after removing the second spacer, removing the remaining portions of the carbon-containing capping layer and the oxide layer. The pattern of the first spacer, the first mandrel, and the second mandrel is transferred to the first hard mask; and the target layer is patterned using the first hard mask as a mask. In some embodiments, the method further includes: forming a photoresist over the carbon-containing capping layer; and patterning the photoresist, wherein patterning the photoresist includes an ashing process, and wherein patterning the carbon-containing capping layer includes using an ashing process to remove portions of the carbon-containing capping layer that overlap with the second spacer and the second mandrel. In some embodiments, the patterned oxide layer comprises a diluted hydrogen fluoride (dHF) wet etching process. In some embodiments, the carbon-containing capping layer has a carbon concentration of at least 30%. In some embodiments, forming the carbon-containing capping layer comprises forming the carbon-containing capping layer in the same atomic layer deposition (ALD) chamber as the oxide layer. In some embodiments, the carbon-containing capping layer has a... to The thickness is within the range specified. In some embodiments, the deposited oxide layer includes a flowing first carbon-containing precursor, wherein forming the carbon-containing capping layer includes a flowing second carbon-containing precursor, and wherein the first and second carbon-containing precursors are identical. In some embodiments, the deposited oxide layer includes a flowing first carbon-containing precursor, wherein forming the carbon-containing capping layer includes a flowing second carbon-containing precursor, and wherein the second carbon-containing precursor has a higher carbon-to-nitrogen ratio than the first carbon-containing precursor.

[0066] In some embodiments, the method includes: depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming a first spacer on the first mandrel and a second spacer on the second mandrel; selectively removing the second spacer while masking the first spacer, wherein masking the first spacer includes covering the first spacer with an overlay layer over the second and second masks, and wherein the overlay layer has at least 30% carbon; patterning the first mask, wherein patterning the first mask includes masking the first mask with the second mandrel, the first mandrel, and the first spacer; and transferring the pattern of the first mask to the target layer. In some embodiments, the target layer includes a multilayer structure. In some embodiments, the method further includes: forming a third mandrel; forming a third spacer on the third mandrel; and selectively removing the third mandrel after selectively removing the second spacer while masking the first mandrel, the first spacer, and the second mandrel, wherein patterning the first mask further includes masking the first mask with the third spacer.

[0067] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A first mask is deposited over a first region of the target layer and a second region of the target layer; Multiple mandrels are formed above the first mask; Multiple spacers are formed on the sidewalls of the plurality of mandrels; A second mask is deposited over the plurality of mandrels and the plurality of spacers; A cover layer is formed over the second mask, wherein the cover layer comprises carbon; and The second mask and the overlay layer are patterned to expose a first mandrel of the plurality of mandrels and a first spacer of the plurality of spacers, the first mandrel and the first spacer overlapping the first region of the target layer. The second mask is conformally deposited on the sidewalls of the plurality of spacers, the top surface of the plurality of mandrels, and the top surface of the first mask, such that the second mask extends along the top surface of the first mask between the spacers formed on the sidewalls of adjacent mandrels.

2. The method according to claim 1, further comprising: Remove the first spacer; After removing the first spacer, remove the remaining portion of the cover layer and the remaining portion of the second mask; After removing the remaining portion of the overlay and the remaining portion of the second mask, the first mask is patterned, wherein patterning the first mask includes transferring the pattern of the first mandrel to the first mask; as well as The pattern of the first mask is transferred to the target layer.

3. The method of claim 2, wherein, Patterning the first mask includes transferring a pattern of a second spacer to the first mask, wherein the second spacer is composed of the plurality of spacers, and wherein the second spacer overlaps with a second region of the target layer.

4. The method of claim 3, wherein, Patterning the first mask includes transferring a pattern of a second mandrel to the first mask, wherein the second mandrel is disposed between the second spacers.

5. The method of claim 1, wherein, The covering layer has a carbon concentration of at least 30%.

6. The method of claim 1, wherein, Forming the capping layer includes forming the capping layer in the same process chamber as the one used for depositing the second mask.

7. The method of claim 6, wherein, Depositing the second mask includes flowing a first carbon-containing precursor and oxygen over the plurality of spacers and the plurality of mandrels, wherein forming the capping layer includes flowing a second carbon-containing precursor over the second mask without flowing oxygen.

8. The method of claim 7, wherein, The second carbon-containing precursor is the same compound as the first carbon-containing precursor.

9. The method of claim 7, wherein, The second carbon-containing precursor is a compound different from the first carbon-containing precursor.

10. A method of forming a semiconductor device, comprising: Deposit a first hard mask above the target layer; A first mandrel and a second mandrel are formed above the first hard mask; A first spacer is formed on the sidewall of the first mandrel, and a second spacer is formed on the sidewall of the second mandrel; An oxide layer is deposited over the first mandrel, the second mandrel, the first spacer, and the second spacer; A carbon-containing capping layer is formed over the oxide layer; Pattern the carbon-containing capping layer to expose the oxide layer; The oxide layer is patterned to expose the second mandrel and the second spacer, while the first spacer and the first mandrel are masked with the carbon-containing capping layer; Remove the second spacer; After removing the second spacer, remove the remaining portion of the carbon-containing coating and the oxide layer; The patterns of the first spacer, the first mandrel, and the second mandrel are transferred to the first hard mask; as well as The target layer is patterned using the first hard mask as a mask. The oxide layer is conformally deposited on the sidewalls of the first spacer and the second spacer, on the top surfaces of the first mandrel and the second mandrel, and on the top surface of the first hard mask, such that the oxide layer extends along the top surface of the first hard mask between adjacent first spacers and second spacers.

11. The method of claim 10, further comprising: Photoresist is formed over the carbon-containing capping layer; as well as Patterning the photoresist, wherein patterning the photoresist includes an ashing process, and wherein patterning the carbon-containing overlay includes using the ashing process to remove the portion of the carbon-containing overlay that overlaps with the second spacer and the second mandrel.

12. The method according to claim 10, wherein, Patterning the oxide layer includes a diluted hydrogen fluoride wet etching process.

13. The method according to claim 10, wherein, The carbon-containing coating has a carbon concentration of at least 30%.

14. The method of claim 10, wherein, Forming the carbon-containing capping layer involves forming the carbon-containing capping layer in the same atomic layer deposition chamber as the oxide layer.

15. The method according to claim 10, wherein, The carbon-containing coating has a thickness in the range of 5 Å to 15 Å.

16. The method of claim 10, wherein, Depositing the oxide layer includes flowing a first carbon-containing precursor, wherein forming the carbon-containing capping layer includes flowing a second carbon-containing precursor, and wherein the first carbon-containing precursor and the second carbon-containing precursor are the same.

17. The method according to claim 10, wherein, Depositing the oxide layer includes flowing a first carbon-containing precursor, wherein forming the carbon-containing capping layer includes flowing a second carbon-containing precursor, and wherein the second carbon-containing precursor has a higher carbon-nitrogen ratio than the first carbon-containing precursor.

18. A method of forming a semiconductor device, comprising: Deposit a first mask above the target layer; A first mandrel and a second mandrel are formed above the first mask; A first spacer is formed on the first mandrel, and a second spacer is formed on the second mandrel; Selectively remove the second spacer while masking the first spacer, wherein masking the first spacer includes covering the first spacer with a second mask and a covering layer above the second mask, and wherein the covering layer has at least 30% carbon. Patterning the first mask, wherein patterning the first mask includes masking the first mask with the second mandrel, the first mandrel, and the first spacer; and The pattern of the first mask is transferred to the target layer. The step of covering the first spacer with the second mask and the covering layer includes: The second mask is conformally deposited on the sidewalls of the first spacer and the second spacer, on the top surfaces of the first mandrel and the second mandrel, and on the top surface of the first mask, such that the second mask extends along the top surface of the first mask between adjacent first spacers and second spacers.

19. The method according to claim 18, wherein, The target layer comprises a multi-layer structure.

20. The method of claim 18, further comprising: Forming a third mandrel; A third spacer is formed on the third mandrel; as well as After selectively removing the second spacer, the third mandrel is selectively removed while simultaneously masking the first mandrel, the first spacer, and the second mandrel, wherein patterning the first mask further includes masking the first mask with the third spacer.

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