High-aspect ratio semiconductor device planarization method

Abstract

The application provides a high-step semiconductor device planarization method, which comprises the following steps: forming a second material film layer on a first material film layer with a high step, wherein the second material film layer covers at least the recessed area of the first material film layer; etching the protruding area of the first material film layer and the second material film layer by using an etching process with a high selectivity ratio, so that the first material film layer and the second material film layer are in the same plane; and processing the first material film layer and the second material film layer by using a planarization process, so as to remove all the second material film layer and planarize the first material film layer. The technical scheme provided by the application can make the semiconductor device in a state close to a plane before planarization treatment by forming a second material film layer and etching, so as to avoid the occurrence of dishing defects in the semiconductor device in the planarization process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a high-step semiconductor device planarization method. BACKGROUND

[0002] When planarizing a semiconductor device with high steps, if no treatment is performed and planarization is directly performed, the protruding parts need to be subjected to a long time of planarization treatment to eliminate the steps and form a flat surface. However, a long time of planarization treatment can cause the surface of the device to form a dishing defect. To solve the above problem, etching is usually performed on the protruding area to reduce the height of the protruding area and the step difference of the recessed area, thereby reducing the planarization time and avoiding the generation of a dishing defect.

[0003] In the process of implementing the present application, the inventors found that at least the following technical problems exist in the prior art: When etching the protruding area, since the bottom size of the protruding area is slightly larger than the top size, when etching according to the bottom size, a sharp corner will appear at the junction between the original protruding area and the recessed position after etching. In the subsequent planarization process, the sharp corner breaks to form a large particle, which can cause scratches on the surface of the device. SUMMARY

[0004] The high-step semiconductor device planarization method provided by the present application can make the semiconductor device approach a flat state before planarization treatment by forming a second material film layer and an etching process, thereby avoiding the generation of a dishing defect in the planarization process.

[0005] The present application provides a high-step semiconductor device planarization method, comprising:

[0006] forming a second material film layer on a first material film layer with high steps, the second material film layer covering at least the recessed area of the first material film layer;

[0007] using an etching process with high selectivity to etch the protruding area of the first material film layer and the second material film layer, so that the first material film layer and the second material film layer are in the same plane;

[0008] using a planarization process to treat the first material film layer and the second material film layer to remove all the second material film layer and planarize the first material film layer.

[0009] Optionally, the selectivity of the etching process to the first material film layer and the second material film layer is not less than 50:1.

[0010] Optionally, the second material film layer is a spin coating film layer or a photoresist.

[0011] Optionally, the second material film layer covers the raised area and the recessed area of the first material film layer, and the second material film layer thickness of the raised area is less than the second material film layer thickness of the recessed area.

[0012] Optionally, the second material film layer thickness of the recessed area is not more than 500 angstroms, and the second material film layer thickness of the raised area is not more than 100 angstroms.

[0013] Optionally, the etching of the raised area of the first material film layer and the second material film layer by using the etching process with high selectivity ratio comprises:

[0014] etching the entire second material film layer of the raised area and the partial second material film layer of the recessed area to expose the first material film layer of the raised area;

[0015] etching the partial first material film layer and the partial second material film layer of the recessed area to make the exposed first material film layer and the second material film layer in the same plane.

[0016] Optionally, the removal rate ratio of the planarization process to the first material film layer and the second material film layer is 1:1.

[0017] Optionally, the forming of the second material film layer on the first material film layer with high step difference comprises:

[0018] forming the second material with fluidity on the surface of the first material film layer to make the second material naturally flow and form on the surface of the first material film layer;

[0019] hardening the second material to form the second material film layer.

[0020] Optionally, the semiconductor device is a wafer prepared for the integrated circuit with the capacitor as the storage unit, the raised area is the area corresponding to the storage unit, and the recessed area is the area corresponding to the peripheral circuit.

[0021] Optionally, the first material film layer is the oxide dielectric film layer covering the storage unit and the peripheral circuit.

[0022] In the technical solution provided by the present application, the second material film layer is arranged on the surface of the semiconductor device with high step difference, the entire surface of the semiconductor device is etched after the arrangement of the second material film layer is completed, the second material film layer surface of the recessed area and the exposed first material film layer surface are etched to the same surface by controlling the selectivity ratio of the etching, and then the planarization is performed to remove the entire second material film layer and make the surface of the first material film layer form a planarized surface. In the planarization process, the removal amount is small, and the planarization time is short, so that the dish-shaped defect does not occur. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A flowchart of a high step semiconductor device planarization method according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0025] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity of presentation and may omit certain details. The shapes of various regions, layers shown in the diagrams, and their relative sizes and positional relationships are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, relative positions according to actual needs.

[0026] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0027] An embodiment of the present application provides a high step semiconductor device planarization method, as shown in Figure 1 comprising:

[0028] In some embodiments, during the preparation of a semiconductor device, if one portion has a higher height and another portion has a lower height, after the two portions are formed, when the first material film layer is deposited again, the first material film layer is formed to have a higher step. For example, during the manufacture of a DRAM, because the height of the capacitor is higher and the height of the peripheral circuit is lower, after the preparation of the capacitor and the peripheral circuit is completed, when the first material film layer is deposited again, such as the deposition of an oxide dielectric film, the first material film layer with a high step is formed. At this time, in order to facilitate the subsequent processing, the first material film layer needs to be planarized. In some embodiments, in order to facilitate the subsequent planarization process, the second material film layer is formed on the first material film layer, and the second material film layer can only cover the recessed area, or can cover the recessed area with a thicker film layer and cover the protruding area with a thinner film layer. As a preferred embodiment, the second material film layer is a spin-coated film layer or a photoresist. Both of these materials have fluidity before curing, and when the second material film layer is formed, the material can be formed on the first material film layer without any treatment, and the film layer is formed by the fluidity of the material itself.

[0029] The protruding area of the first material film layer and the second material film layer are etched by using an etching process with a high selectivity ratio, so that the first material film layer and the second material film layer are in the same plane. In some embodiments, because the first material film layer has a higher step, during the etching process, the first material film layer of the protruding area needs to be etched in a larger amount. In order to ensure that the exposed first material film layer and the second material film layer are in the same plane after etching, the second material film layer needs to be etched in a smaller amount. Therefore, by using an etching process with a higher selectivity ratio, the first material film layer of the protruding portion has a higher etching efficiency, and the second material film layer has a lower etching efficiency. Thus, after a period of etching, the exposed first material film layer and the second material film layer are in the same plane.

[0030] The first material film layer and the second material film layer are treated by using a planarization process to remove all the second material film layer and planarize the first material film layer. In some embodiments, because the exposed first material film layer and the second material film layer are basically in the same plane, during the planarization process, they are removed at the same rate until all the second material film layer is removed and the first material film layer reaches the target thickness. During the planarization process, the removal amount is small, the planarization process time is short, and no dishing defects occur.

[0031] In the technical scheme provided by the embodiment of the present application, the second material film layer is arranged on the surface of the semiconductor device with high step difference, and after the arrangement of the second material film layer is completed, the whole surface of the semiconductor device is etched, the surface of the second material film layer in the recessed area and the surface of the exposed first material film layer are etched to the same surface by controlling the selection ratio of etching, and then the whole second material film layer is removed by planarization and the surface of the first material film layer is formed into a planar surface. In the planarization process, the removal amount is small, the planarization process time is short, and no dish-shaped defect occurs.

[0032] As an optional embodiment, the selection ratio of the etching process to the first material film layer and the second material film layer is not less than 50:1. In some embodiments, the selection of the etching selection ratio depends on the step difference of the first material film layer. Generally, the higher the step difference, the higher the required etching selection ratio, and the lower the step difference, the lower the required etching selection ratio. For the same step difference, a higher selection ratio can make the exposed first material film layer and the second material film layer quickly reach the same plane, but more removal amount is required in the subsequent planarization process. A lower selection ratio can increase the etching amount, but it will also increase the etching time to make the first material film layer and the second material film layer reach the same plane.

[0033] As an optional embodiment, the second material film layer covers the convex area and the recessed area of the first material film layer, and the thickness of the second material film layer in the convex area is less than the thickness of the second material film layer in the recessed area. In some embodiments, when the second material film layer covers the convex area and the recessed area, the second material film layer in the convex area and the second material film layer in the recessed area are etched synchronously. When the first material film layer in the convex area begins to be exposed, the second material film layer in the recessed area has been removed a part. Therefore, for the whole etching process, the removal amount of the second material film layer in the recessed area will increase, reducing the removal amount of the subsequent planarization process. As a preferred embodiment, the thickness of the second material film layer in the recessed area is not greater than 500 angstroms, and the thickness of the second material film layer in the convex area is not greater than 100 angstroms.

[0034] As an optional implementation, the etching process with high selectivity ratio for the protruding region of the first material film layer and the second material film layer includes: etching the entire second material film layer of the protruding region and part of the second material film layer of the recessed region to expose the first material film layer of the protruding region; etching part of the first material film layer and part of the second material film layer of the recessed region to make the exposed first material film layer and the second material film layer in the same plane. Those skilled in the art should understand that the etching process in this embodiment can be continuously performed, and the etching equipment or etchant can not be replaced during the etching process. During the etching process, the second material film layer of the protruding region and the second material film layer of the recessed region are etched synchronously at first, and the second material film layer of the recessed region can be thinned at the same time of exposing the first material film layer of the protruding region, thereby reducing the removal amount in the subsequent planarization process. After the first material film layer of the protruding region is exposed, the first material film layer of the protruding region is etched at a higher rate until the first material film layer of the protruding region and the second material film layer are in the same plane, i.e., the etching is stopped.

[0035] As an optional implementation, the removal rate ratio of the planarization process for the first material film layer and the second material film layer is 1:1. Since the first material film layer and the second material film layer are basically in the same plane after etching, the planarization process is mainly to further remove the second material film layer and planarize the first material film layer. Therefore, in order to keep the device surface in a planar state, the removal efficiency of the planarization process for the first material film layer and the second material film layer should be kept at 1:1.

[0036] As an optional implementation, forming the second material film layer on the first material film layer with high step difference includes: forming a second material with fluidity on the surface of the first material film layer, so that the second material is naturally formed on the surface of the first material film layer; hardening the second material to form a second material film layer. In some embodiments, the second material with fluidity is formed on the first material film layer, and the second material film layer with thinner protruding region and thicker recessed region is naturally formed by relying on its fluidity, without other process treatment, and the process procedure is simple.

[0037] As an optional embodiment, the semiconductor device is a wafer for manufacturing an integrated circuit with capacitors as storage units, the protruding region is a region corresponding to the storage units, and the recessed region is a region corresponding to the peripheral circuit. In some embodiments, in an integrated circuit with capacitors as storage units, such as in a DRAM, the capacitors usually have a higher height, and the peripheral circuit usually has a lower height. After the capacitors and the peripheral circuit are manufactured, a first material film layer, such as an oxide dielectric layer, is formed again for subsequent processes. When the first material film layer is formed, due to the profile characteristics of the first material film layer during the formation of the first material film layer, the first material film layer forms a protruding region at a position corresponding to the capacitors and forms a recessed region at a position corresponding to the peripheral circuit. As an optional embodiment, the first material film layer is an oxide dielectric film layer covering the storage units and the peripheral circuit.

[0038] In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, and the like with the required shapes can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0039] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A high step semiconductor device planarization method, characterized by, The method comprises the following steps: forming a second material film layer on the first material film layer with high step difference, the second material film layer covering at least the recessed area of the first material film layer; etching the protruding area of the first material film layer and the second material film layer by using an etching process with high selectivity ratio, so that the first material film layer and the second material film layer are in the same plane; processing the first material film layer and the second material film layer by using a planarization process, so as to remove all the second material film layer and planarize the first material film layer; wherein, during the planarization process, the first material film layer and the second material film layer are removed at the same rate until all the second material film layer is removed and the first material film layer reaches the target thickness; wherein the selectivity ratio of the etching process to the first material film layer and the second material film layer is not less than 50:1; wherein the second material film layer covers the protruding area and the recessed area of the first material film layer, the thickness of the second material film layer in the protruding area is less than that in the recessed area; wherein etching the protruding area of the first material film layer and the second material film layer by using an etching process with high selectivity ratio comprises: etching all the second material film layer in the protruding area and part of the second material film layer in the recessed area to expose the first material film layer in the protruding area; etching part of the first material film layer and part of the second material film layer in the recessed area, so that the exposed first material film layer and the second material film layer are in the same plane.

2. The high-aspect-ratio semiconductor device planarization method according to claim 1, wherein The second material film layer is a spin-coated film layer or a photoresist.

3. The high-aspect-ratio semiconductor device planarization method of claim 1, wherein The thickness of the second material film layer in the recessed area is not more than 500 angstroms, and the thickness of the second material film layer in the protruding area is not more than 100 angstroms.

4. The method of claim 1, wherein the planarization of the high aspect ratio semiconductor device is performed by a chemical mechanical polishing process. forming a second material film layer on the first material film layer with high step difference comprises: forming a second material with fluidity on the surface of the first material film layer, so that the second material is naturally formed on the surface of the first material film layer; hardening the second material to form a second material film layer.

5. The method of claim 1, wherein the planarization of the high aspect ratio semiconductor device is performed by a chemical mechanical polishing process. The semiconductor device is a wafer on which an integrated circuit with a capacitor as a storage unit is prepared, the protruding area is a region corresponding to the storage unit, and the recessed area is a region corresponding to the peripheral circuit.

6. The high-aspect-ratio semiconductor device planarization method according to claim 5, wherein The first material film layer is an oxide dielectric film layer covering the storage unit and the peripheral circuit.

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