A fan-out packaging structure and forming method thereof

Abstract

The present invention relates to a fan-out packaging structure, comprising: a first interconnect structure, comprising a plurality of first insulating layers and a plurality of metal redistribution layers located in the plurality of first insulating layers, and the plurality of metal redistribution layers are electrically connected; a second insulating layer, located on the front side of the first interconnect structure; a metal buffer layer, located in the second insulating layer and electrically connected to the metal redistribution layer; a pin, electrically connected to the metal redistribution layer; a third insulating layer, located on the metal buffer layer; an underbump metallization layer, located on the pin; a chip, arranged on the underbump metallization layer; an underfill, arranged between the chip and the third insulating layer; a plastic encapsulation layer, which plastic encapsulates the third insulating layer to the back side of the chip; a metal layer, located on the side and back side of the fan-out packaging structure, and electrically connected to the chip and the metal buffer layer; and a solder ball, arranged on the back side of the first interconnect structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a fan-out packaging structure and a forming method thereof. Background Art

[0002] With the rapid advancement of integrated circuit technology, integrated circuit packaging is constantly improving. Chip feature sizes are gradually miniaturizing to meet the demands of Moore's Law. While chip feature sizes are decreasing, the number of electronic components within a chip is increasing. To realize the functionalities of chips in end-products, packaging technologies with compact dimensions and a large number of output terminals (I / Os) are required. Fan-out packaging technology, with its advantages of high density, lightweight, compact size, excellent heat dissipation, and high-frequency performance, is one of the most promising development directions for heterogeneous integration. Fan-out packaging shares the characteristics of wafer-level packaging and offers the advantages of low cost and high integration density. However, due to the large number of materials involved and complex structure, reliability is a key technical issue that hinders its wider application. During reliability testing or in harsh environments, deformation or stress in the plastic encapsulation area of ​​fan-out packages can cause fractures or failures in the metal redistribution interconnect layer. To improve the reliability of fan-out packaging structures, new research approaches and solutions are needed. Summary of the Invention

[0003] The task of the present invention is to provide a fan-out packaging structure and a method for forming the same, by arranging a whole-surface metal buffer layer on the metal redistribution layer close to the plastic packaging layer, which can improve the reliability of the fan-out packaging structure in reliability testing or harsh environments, thereby avoiding the breakage or failure of the metal redistribution layer caused by deformation or stress, and arranging a metal layer connected to the metal buffer layer on the back of the fan-out packaging structure, so as to facilitate the conduction of the heat of the chip to the back of the packaging structure, thereby improving the heat dissipation performance of the package and providing a good electronic shielding effect.

[0004] In a first aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a fan-out packaging structure, comprising:

[0005] A first interconnect structure includes a plurality of first insulating layers and a plurality of metal redistribution layers located in the plurality of first insulating layers, wherein the plurality of metal redistribution layers are electrically connected;

[0006] a second insulating layer located on a front surface of the first interconnect structure;

[0007] a metal buffer layer, located in the second insulating layer and electrically connected to the metal redistribution layer;

[0008] A pin electrically connected to the metal redistribution layer;

[0009] a third insulating layer, located on the metal buffer layer;

[0010] an under-bump metallization layer located on the pin;

[0011] a chip disposed on the under-bump metallization layer;

[0012] An underfill is arranged between the chip and the third insulating layer;

[0013] a plastic sealing layer, which seals the area between the third insulating layer and the back surface of the chip;

[0014] a metal layer, which is located on the side and back of the fan-out packaging structure and is electrically connected to the chip and the metal buffer layer; and

[0015] Solder balls are arranged on the back side of the first interconnect structure.

[0016] Furthermore, it also includes a plastic filling layer, which is located outside the metal layer.

[0017] Furthermore, the metal buffer layer is a whole metal layer or a mesh metal layer, and has a plurality of blank areas without metal; and

[0018] The pin is located in a blank area of ​​the metal buffer layer, and the second insulating layer is filled between the pin and the metal buffer layer.

[0019] Furthermore, the under bump metallization layer is electrically connected to the pin, and a portion of the under bump metallization layer is located in the third insulating layer.

[0020] Furthermore, the front side of the chip has bumps, and the chip is flip-chip mounted on the under-bump metallization layer by welding the under-bump metallization layer and the bumps.

[0021] In a second aspect of the present invention, in order to solve the problems existing in the prior art, the present invention provides a method for forming a fan-out packaging structure, comprising:

[0022] Applying temporary bonding glue on the slide;

[0023] forming a first interconnect structure on the temporary bonding adhesive, wherein the first interconnect structure comprises a first insulating layer and a plurality of metal redistribution layers located in the plurality of first insulating layers, and the plurality of metal redistribution layers are electrically connected;

[0024] forming a metal buffer layer and a pin on the first interconnect structure;

[0025] forming a third insulating layer on the metal buffer layer, forming an under-bump metallization layer passing through the third insulating layer and electrically connected to the pin, and then forming a solder layer on the under-bump metallization layer;

[0026] Arranging the chip on the under-bump metallization layer and filling underfill between the chip and the third insulating layer;

[0027] Plastic-sealing the first interconnect structure to the chip to form a plastic-sealing layer;

[0028] Thinning the back of the plastic layer to expose the back of the chip;

[0029] forming a through hole at the edge of the plastic packaging layer to expose the side surface of the first interconnect structure, the side surface of the metal buffer layer, the side surface of the third insulating layer, and the temporary bonding glue;

[0030] Electroplating metal on the inner wall of the through hole, the back of the chip and the back of the plastic packaging layer to form a metal layer;

[0031] Performing a second plastic sealing to seal the through hole and the metal layer to form a plastic sealing filling layer;

[0032] Remove the slide through a debonding process;

[0033] disposing solder balls on a backside of the first interconnect structure;

[0034] Thinning the plastic filling layer to expose the metal layer; and

[0035] A single fan-out package structure is formed by cutting through the vias.

[0036] Furthermore, when forming the metal buffer layer and the pins, a second insulating layer is first formed on the first interconnect structure, and then the second insulating layer is etched to form a circuit pattern, and metal is electroplated on the circuit pattern to form the metal buffer layer and the pins.

[0037] Furthermore, the metal buffer layer is a whole metal layer or a mesh metal layer, and has a plurality of blank areas without metal; and

[0038] The pin is located in a blank area of ​​the metal buffer layer, and a second insulating layer is filled between the pin and the metal buffer layer.

[0039] Furthermore, the metal layer is electrically connected to the metal buffer layer and the chip.

[0040] Furthermore, the plastic packaging layer is grooved by mechanical punching or laser punching to form through holes, wherein the through holes are located around the chip.

[0041] The present invention has at least the following beneficial effects: a fan-out packaging structure and a method for forming the same disclosed in the present invention arranges a whole-surface metal buffer layer on the metal redistribution layer close to the plastic packaging layer as a stress buffer layer for the lower metal redistribution layer, which can improve the reliability of the fan-out packaging structure in reliability testing or harsh environments, thereby avoiding the metal redistribution layer from breaking or failing due to deformation or stress. In addition, the number and position of the metal buffer layers can be determined according to actual conditions; a metal layer connected to the metal buffer layer is arranged on the back of the fan-out packaging structure to facilitate the conduction of the chip's heat to the back of the packaging structure, thereby improving the heat dissipation performance of the package and providing a good electronic shielding effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope thereof. In the drawings, for clarity, identical or corresponding parts will be represented by the same or similar reference numerals.

[0043] Figure 1 A schematic diagram showing a fan-out packaging structure according to an embodiment of the present invention; and

[0044] Figures 2A to 2N A cross-sectional schematic diagram of a formation process of a fan-out packaging structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0045] It should be noted that components in the drawings may be shown exaggerated for illustrative purposes and are not necessarily true to scale.

[0046] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0047] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0048] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person skilled in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario.

[0049] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values ​​are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0050] It should also be noted that in the description of the present invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They do not explicitly or implicitly state that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0052] Figure 1 A schematic diagram of a fan-out packaging structure according to an embodiment of the present invention is shown.

[0053] like Figure 1 As shown, a fan-out packaging structure includes a first interconnect structure 101, a second insulating layer 102, a metal buffer layer 103, a pin 104, a third insulating layer 105, an under-bump metallization layer 106, a chip 107, an underfill 108, a plastic layer 109, a metal layer 110, a plastic filling layer 111 and a solder ball 112.

[0054] The first interconnect structure 101 has a front surface and a back surface opposite to the front surface. The first interconnect structure 101 includes a plurality of first insulating layers 1011 and a plurality of metal redistribution layers 1012 located in the plurality of first insulating layers, and the plurality of metal redistribution layers 1012 are electrically connected.

[0055] The second insulating layer 102 is located on the front surface of the first interconnect structure 101 .

[0056] The metal buffer layer 103 is located in the second insulating layer 102 and is electrically connected to the metal redistribution layer 1012. The metal buffer layer 103 is a metal layer with a large area of ​​electroplated metal on one side and has multiple blank areas that do not contain metal. The pin 104 is located in the blank area. The metal buffer layer 103 can be a whole-surface metal layer, or a mesh metal layer with multiple holes. Specifically, when the metal buffer layer 103 is a whole-surface metal layer, except for the blank areas, the remaining areas are electroplated metal layers; when the metal buffer layer 103 is a mesh metal layer, except for the blank areas, the remaining areas are electroplated metal layers with multiple holes. The mesh metal buffer layer 103 can reduce the metal coverage rate and facilitate the electroplating process to produce the metal buffer layer. The number and position of the metal buffer layer can be determined according to actual conditions. For example, the metal buffer layer can be arranged between multiple metal redistribution layers.

[0057] The pin 104 is located in the blank area of ​​the metal buffer layer 103 and is electrically connected to the metal redistribution layer 1012. The pin 104 and the metal buffer layer 103 are coplanar. The gap between the pin 104 and the metal buffer layer 103 is filled by the second insulating layer 102.

[0058] The third insulating layer 105 is located on the metal buffer layer 103 .

[0059] The under bump metallization layer 106 is located on the pin 104 and is electrically connected to the pin 104 . A portion of the under bump metallization layer 106 is located in the third insulating layer 105 .

[0060] Chip 107 is disposed on underbump metallurgy layer 106. Bumps 1071 are provided on the front surface of chip 107. Chip 107 is flip-chip mounted on underbump metallurgy layer 106 by soldering underbump metallurgy layer 106 to bumps 1071. Solder layer 113 is located between bumps 1071 and underbump metallurgy layer 106. Here, there are two chips. In other embodiments of the present invention, there may be fewer or more chips.

[0061] An underfill 108 is disposed between the chip 107 and the third insulating layer 106 . The underfill 108 is used to protect the connection between the bump 1071 and the underbump metallization layer 106 .

[0062] The plastic encapsulation layer 109 encapsulates the area between the third insulating layer 105 and the back surface of the chip 107 .

[0063] Metal layer 110 is located on the side and back of the fan-out package structure and is electrically connected to chip 107 and metal buffer layer 103. Specifically, metal layer 110 is located on the back of chip 107 and plastic layer 109, as well as on the side of plastic layer 109, third insulating layer 105, metal buffer layer 103, and first interconnect structure 101.

[0064] The plastic filling layer 111 is located outside the metal layer 110 .

[0065] The solder balls 112 are arranged on the back side of the first interconnect structure 101 . The solder balls 112 are electrically connected to the metal redistribution layer 1012 located on the back side of the first interconnect structure 101 .

[0066] Figures 2A to 2N A cross-sectional schematic diagram of a formation process of a fan-out packaging structure according to an embodiment of the present invention is shown.

[0067] A method for forming a fan-out packaging structure includes:

[0068] In step 1, if Figure 2A As shown, a temporary bonding glue 302 is coated on a carrier wafer 301 .

[0069] In step 2, if Figure 2B As shown, a first interconnect structure 201 is formed on a temporary bonding adhesive 302. The first interconnect structure 201 includes a first insulating layer 2011 and multiple metal redistribution layers 2012 located within the multiple first insulating layers 2011, and the multiple metal redistribution layers 2012 are electrically connected. The first insulating layer 2011 is formed on the temporary bonding adhesive 302 by coating, deposition, or other methods, and then the first insulating layer is etched to form a circuit pattern. Metal is then electroplated on the circuit pattern to form the metal redistribution layers 2012. The above steps are repeated multiple times to obtain the first interconnect structure 201. The first interconnect structure 201 is located in the middle area of ​​the temporary bonding adhesive 302, with the edges of the temporary bonding adhesive 302 exposed.

[0070] In step 3, if Figure 2CAs shown, a metal buffer layer 203 and a pin 204 are formed on the first interconnect structure 201. The metal buffer layer 203 is located in the second insulating layer 202 and is electrically connected to the metal redistribution layer 2012. The metal buffer layer 203 is a metal layer with a large area of ​​electroplated metal on one side and has multiple blank areas that do not contain metal. The pin 204 is located in the blank area. The metal buffer layer 203 can be a whole-surface metal layer or a mesh metal layer with multiple holes. Specifically, when the metal buffer layer 203 is a whole-surface metal layer, except for the blank areas, the remaining areas are electroplated metal layers; when the metal buffer layer 203 is a mesh metal layer, except for the blank areas, the remaining areas are electroplated metal layers with multiple holes. The mesh metal buffer layer 203 can reduce the metal coverage rate and facilitate the electroplating process to produce the metal buffer layer. The number and position of the metal buffer layer can be determined according to actual conditions. For example, the metal buffer layer can be arranged between multiple metal redistribution layers. Pins 204 are located in the blank areas of metal buffer layer 203 and are electrically connected to metal redistribution layer 2012. The gaps between pins 204 and metal buffer layer 203 are filled with second insulating layer 202. To form metal buffer layer 203 and pins 204, second insulating layer 202 is first formed on first interconnect structure 201 by coating, deposition, or other methods. Second insulating layer 202 is then etched to form a circuit pattern. Metal is then electroplated on the circuit pattern to form metal buffer layer 103 and pins 204.

[0071] In step 4, if Figure 2D As shown, a third insulating layer 205 is formed on the metal buffer layer 203, and an underbump metallurgy layer 206 is formed to electrically connect to the pin 204 through the third insulating layer 205. Then, a solder layer 213 is formed on the underbump metallurgy layer 206. The third insulating layer 205 is first formed on the metal buffer layer 203 by coating, deposition, or other methods. The third insulating layer 205 located on the pin 204 is then removed by etching to form a hole pattern. Metal is then electroplated in the hole pattern to form the underbump metallurgy layer 206. A portion of the underbump metallurgy layer 206 is located within the third insulating layer 205, while another portion is located above the third insulating layer 205.

[0072] In step 5, if Figure 2E As shown, chip 207 is placed on underbump metallization layer 206, and underfill 108 is filled between chip 207 and third insulating layer 205. Chip 207 has bumps 2071 on its front surface. Chip 207 is flip-chip mounted on underbump metallization layer 206 by soldering underbump metallization layer 206 to bumps 2071. Solder layer 213 is located between bumps 2071 and underbump metallization layer 206. Here, the number of chips is two. In other embodiments of the present invention, a smaller or larger number of chips may be used.

[0073] In step 6, if Figure 2F As shown, the first interconnect structure 201 and the chip 207 are plastic-encapsulated to form a plastic layer 209 . The plastic layer 209 is located on the temporary bonding adhesive 302 .

[0074] In step 7, if Figure 2G As shown, the back side of the plastic encapsulation layer 209 is thinned to expose the back side of the chip 207 .

[0075] In step 8, if Figure 2H As shown, through holes 214 are formed at the edges of the plastic layer 209, exposing the side surfaces of the first interconnect structure 201, the metal buffer layer 203, the third insulating layer 205, and the temporary bonding adhesive 302. The plastic layer 209 is grooved by mechanical punching or laser drilling to form the through holes 214. The through holes 214 are located around the chip 207.

[0076] In step 9, if Figure 2I As shown, metal is electroplated on the inner wall of the through hole 213, the back surface of the chip 207, and the back surface of the plastic encapsulation layer 209 to form a metal layer 210. The metal layer 210 is electrically connected to the metal buffer layer 203 and the chip 207, facilitating heat transfer from the chip 207 to the back surface of the package structure, thereby improving the heat dissipation performance of the package and providing a good electron shielding effect.

[0077] In step 10, if Figure 2J As shown, a second plastic sealing is performed to seal the through hole 213 and the metal layer 210 to form a plastic sealing filling layer 211 .

[0078] In step 11, if Figure 2K As shown, the carrier 301 is removed by a debonding process.

[0079] In step 12, if Figure 2L As shown, solder balls 212 are arranged on the back side of the first interconnect structure 201 through a ball planting process. The solder balls 212 are electrically connected to the metal redistribution layer 2012 located on the back side of the first interconnect structure 201.

[0080] In step 13, if Figure 2M As shown, the plastic filling layer 211 is thinned to expose the metal layer 210 .

[0081] In step 14, if Figure 2N As shown, a single fan-out package structure is formed by cutting at the through hole 213 .

[0082] The present invention has at least the following beneficial effects: a fan-out packaging structure and a method for forming the same disclosed in the present invention arranges a whole-surface metal buffer layer on the metal redistribution layer close to the plastic packaging layer as a stress buffer layer for the lower metal redistribution layer, which can improve the reliability of the fan-out packaging structure in reliability testing or harsh environments, thereby avoiding the metal redistribution layer from breaking or failing due to deformation or stress. In addition, the number and position of the metal buffer layers can be determined according to actual conditions; a metal layer connected to the metal buffer layer is arranged on the back of the fan-out packaging structure to facilitate the conduction of the chip's heat to the back of the packaging structure, thereby improving the heat dissipation performance of the package and providing a good electronic shielding effect.

[0083] Although certain embodiments of the present invention have been described in this application, those skilled in the art will appreciate that these embodiments are provided by way of example only. Numerous variations, alternatives, and modifications will be contemplated by those skilled in the art in light of the teachings of this disclosure without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and are intended to encompass methods and structures within the scope of these claims and their equivalents.

Claims

1. A fan-out packaging structure, comprising: A first interconnect structure includes a plurality of first insulating layers and a plurality of metal redistribution layers located in the plurality of first insulating layers, wherein the plurality of metal redistribution layers are electrically connected; a second insulating layer located on a front surface of the first interconnect structure; a metal buffer layer located in the second insulating layer and electrically connected to the metal redistribution layer; the metal buffer layer is a full-surface metal layer or a mesh metal layer and has a plurality of blank areas that do not contain metal; A pin electrically connected to the metal redistribution layer; the pin is located in a blank area of ​​the metal buffer layer, and the second insulating layer is filled between the pin and the metal buffer layer; a third insulating layer, located on the metal buffer layer; an under-bump metallization layer located on the pin; a chip disposed on the under-bump metallization layer; An underfill is arranged between the chip and the third insulating layer; a plastic sealing layer, which seals the area between the third insulating layer and the back surface of the chip; a metal layer, which is located on the side and back of the fan-out packaging structure and is electrically connected to the chip and the metal buffer layer; as well as Solder balls are arranged on the back side of the first interconnect structure.

2. The fan-out packaging structure according to claim 1, wherein: It also includes a plastic filling layer, which is located outside the metal layer.

3. The fan-out packaging structure according to claim 1, wherein: The under-bump metallization layer is electrically connected to the pin, and a portion of the under-bump metallization layer is located in the third insulating layer.

4. The fan-out packaging structure according to claim 1, wherein: The front side of the chip is provided with bumps, and the chip is flip-mounted on the under-bump metallization layer by welding the under-bump metallization layer and the bumps.

5. A method for forming a fan-out packaging structure, comprising: Applying temporary bonding glue on the slide; forming a first interconnect structure on the temporary bonding adhesive, wherein the first interconnect structure comprises a first insulating layer and a plurality of metal redistribution layers located in the plurality of first insulating layers, and the plurality of metal redistribution layers are electrically connected; A metal buffer layer and a pin are formed on the first interconnect structure; the metal buffer layer is a full-surface metal layer or a mesh metal layer and has a plurality of blank areas without metal; the pin is located in the blank area of ​​the metal buffer layer, and a second insulating layer is filled between the pin and the metal buffer layer; forming a third insulating layer on the metal buffer layer, forming an under-bump metallization layer passing through the third insulating layer and electrically connected to the pin, and then forming a solder layer on the under-bump metallization layer; Arranging the chip on the under-bump metallization layer and filling underfill between the chip and the third insulating layer; Plastic-sealing the first interconnect structure to the chip to form a plastic-sealing layer; Thinning the back of the plastic layer to expose the back of the chip; forming a through hole at the edge of the plastic packaging layer to expose the side surface of the first interconnect structure, the side surface of the metal buffer layer, the side surface of the third insulating layer, and the temporary bonding glue; Electroplating metal on the inner wall of the through hole, the back of the chip and the back of the plastic packaging layer to form a metal layer; Performing a second plastic sealing to seal the through hole and the metal layer to form a plastic sealing filling layer; Remove the slide through a debonding process; disposing solder balls on a backside of the first interconnect structure; Thinning the plastic filling layer to expose the metal layer; and A single fan-out package structure is formed by cutting through the vias.

6. The method for forming a fan-out package structure according to claim 5, wherein: When forming the metal buffer layer and the pins, a second insulating layer is first formed on the first interconnect structure, and then the second insulating layer is etched to form a circuit pattern, and metal is electroplated on the circuit pattern to form the metal buffer layer and the pins.

7. The method for forming a fan-out package structure according to claim 5, wherein: The metal layer is electrically connected to the metal buffer layer and the chip.

8. The method for forming a fan-out package structure according to claim 5, wherein: The plastic packaging layer is grooved by mechanical punching or laser punching to form through holes, wherein the through holes are located around the chip.

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