Test structure and test method

Abstract

The application discloses a test structure and a test method. The test structure comprises a first doped region, a second doped region and a third doped region formed in a substrate, an STI structure is formed in the third doped region; a floating gate is formed above the substrate and is located between the STI structures in the lateral direction, a gate dielectric layer is formed between the floating gate and the substrate; a control gate is formed on the floating gate; a plurality of floating gates and a plurality of control gates are located in the third doped region, the floating gate and the control gate are in the shape of a strip; a first metal layer and a second metal layer are further formed in the third doped region, the first metal layer and the second metal layer are located on both sides of the area occupied by the plurality of floating gates and the plurality of control gates, and the two ends of the plurality of control gates are connected with the first metal layer and the second metal layer respectively; a third metal layer and a fourth metal layer are further formed on the substrate, the third metal layer is connected with the second metal layer, the fourth metal layer is connected with the second doped region and does not contact the third doped region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a test structure and a test method. BACKGROUND

[0002] With the continuous development of semiconductor integrated circuit manufacturing technology, the critical dimension (CD) of semiconductor devices is also continuously reduced.

[0003] In the process of manufacturing a flash memory device, in the process of forming a float gate (FG), due to the reduction of the size of the device, the width of the float gate is also reduced, thereby causing a certain probability of defects such as holes and gaps in the formed float gate.

[0004] Therefore, it is urgent to provide a test method for monitoring the defects of the float gate of the flash memory device. SUMMARY

[0005] The present application provides a test structure and a test method, which can solve the problem of holes and gap defects caused by the float gate forming method provided in the related art.

[0006] In one aspect, the present application provides a test structure for detecting the defects of the float gate of a flash memory device, the test structure being formed on a substrate, the test structure comprising:

[0007] a doped region, the doped region being formed in the substrate, the doped region comprising a first doped region, a second doped region and a third doped region from bottom to top, the substrate being doped with a first type of impurity, the first doped region being doped with a second type of impurity, the second doped region being doped with the first type of impurity, the third doped region being doped with the second type of impurity, and an STI structure being formed in the third doped region;

[0008] a float gate, the float gate being formed between the substrate and the STI structure above the substrate, and a gate dielectric layer being formed between the float gate and the substrate;

[0009] a control gate, the control gate being formed on the float gate;

[0010] From a top view, a plurality of the float gates and a plurality of the control gates are located in the third doped region, the float gates and the control gates are in strip shape, the float gates and the control gates are perpendicular to each other, the spacing between the plurality of float gates is the same, and the spacing between the plurality of control gates is the same;

[0011] The third doped region further has a first metal layer and a second metal layer formed therein, the first metal layer and the second metal layer are located on both sides of the area occupied by the plurality of floating gates and the plurality of control gates, and the two ends of the plurality of control gates are connected with the first metal layer and the second metal layer respectively.

[0012] The area of the second doped region is larger than that of the third doped region, and the substrate further has a third metal layer and a fourth metal layer formed thereon, the third metal layer is connected with the second metal layer, and the fourth metal layer is connected with the second doped region and does not contact the third doped region.

[0013] In some embodiments, the first doped region is a drift region of the flash memory device, the second doped region is a well region of the flash memory device, and the third doped region is a threshold voltage adjusting region of the flash memory device.

[0014] In some embodiments, the substrate further includes a cell region for integrating the flash memory device, the floating gates of the flash memory device and the floating gates of the test structure have the same critical dimension, and the distance between the floating gates of the flash memory device is the same as the distance between the floating gates in the test structure.

[0015] In some embodiments, when detecting the floating gate defect of the flash memory device through the test structure, a high level is input through the third metal layer and a low level is input through the fourth metal layer.

[0016] In some embodiments, the flash memory device is a NOR flash memory device.

[0017] In another aspect, the embodiments of the present application provide a test method, which is executed by the test structure as described above, and the test method comprises:

[0018] A high level is input through the third metal layer of the test structure and a low level is input through the fourth metal layer of the test structure;

[0019] The current of the second doped region of the test structure is measured;

[0020] Whether the flash memory device has the floating gate defect is determined according to the current of the second doped region.

[0021] In some embodiments, whether the flash memory device has the floating gate defect is determined according to the current of the second doped region, comprising:

[0022] Whether the current of the second doped region is higher than a target current is detected;

[0023] If the current of the second doped region is higher than the target current, it is determined that the flash memory device has the floating gate defect.

[0024] The technical scheme of the present application has at least the following advantages:

[0025] By forming the test structure on the substrate integrated with the flash memory device, inputting a high level to the third metal layer of the test structure, inputting a low level to the fourth metal layer of the test structure, measuring the current of the second doped region of the test structure, and determining whether the flash memory device has a floating gate defect according to the current of the second doped region, the floating gate defect of the flash memory device can be monitored, and the reliability and yield of the product are improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art of the present application, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 is a cross-sectional view of the test structure provided by an exemplary embodiment of the present application;

[0028] Figure 2 is a top view of the test structure provided by an exemplary embodiment of the present application;

[0029] Figure 3 is a flowchart of the test method provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical scheme in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present application, it needs to be explained that unless explicitly defined and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal connection of two elements, it can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0034] Reference Figure 1 which shows a cross-sectional schematic view of a test structure provided by an exemplary embodiment of the present application; reference Figure 2 which shows a top view schematic view of a test structure provided by an exemplary embodiment of the present application, Figure 1 For Figure 2 the cross-sectional view in AA' direction.

[0035] The test structure is used for detecting floating gate defects of a flash memory device, which is formed on a substrate, and the flash memory device (not shown in the figure) is integrated on the substrate, such as Figure 1 and Figure 2 which can be a NOR flash memory device), as shown in the figure, the test structure comprises: Figure 1

[0036] The doped region is formed in the substrate 110, which comprises a first doped region 101, a second doped region 102 and a third doped region 103 from bottom to top, and the STI structure 140 is formed in the third doped region 103.

[0037] Wherein, the first type of impurity is doped in the substrate 110, the second type of impurity is doped in the first doped region 101, the first type of impurity is doped in the second doped region 102, and the second type of impurity is doped in the third doped region 103.

[0038] In some embodiments, the first doped region 101 is a drift region of a flash memory device, the second doped region 102 is a well region of the flash memory device, and the third doped region 103 is a cell threshold voltage (CVT) region of the flash memory device.

[0039] In the embodiments of the present application, if the first type of impurity is N (negative) type impurity, the second type of impurity is P (positive) type impurity; if the first type of impurity is P type impurity, the second type of impurity is N type impurity.​

[0040] floating gates 131 formed above the substrate 110 and laterally between the STI structures 140, and a gate dielectric layer 120 is formed between the floating gates 131 and the substrate 110.

[0041] control gates 132 formed on the floating gates 131.

[0042] As viewed from the top, as shown in Figure 2 , the plurality of floating gates 131 and the plurality of control gates 132 are located within the third doped region 103, and the floating gates 131 and the control gates 132 are in the shape of strips.

[0043] The first metal layer 151 and the second metal layer 152 are also formed within the third doped region 103, and the first metal layer 151 and the second metal layer 152 are located on both sides of the area occupied by the plurality of floating gates 131 and the plurality of control gates 132, and the two ends of the plurality of control gates 132 are connected to the first metal layer 151 and the second metal layer 152, respectively.

[0044] The third metal layer 153 and the fourth metal layer 154 are also formed on the substrate 110, the third metal layer 153 is connected to the second metal layer 152, and the fourth metal layer 154 is connected to the second doped region 102 and does not contact the third doped region 103.

[0045] When the floating gate defect of the flash memory device is detected by the test structure, a high level is input through the third metal layer 153, and a low level is input through the fourth metal layer 154.

[0046] In the embodiments of the present application, the substrate further includes a cell region (not shown in Figure 1 and Figure 2 ), the cell region is used to integrate the flash memory device, the key size of the floating gate of the flash memory device is the same as that of the test structure, and the distance between the floating gates of the flash memory device is the same as that between the floating gates in the test structure. In some embodiments, the key size of the control gate of the flash memory device is the same as that of the control gate of the test structure, and the distance between the control gates of the flash memory device is the same as that between the floating gates in the test structure.

[0047] Referring to Figure 3 , a flowchart of a test method provided by an exemplary embodiment of the present application is shown, the method is performed by the test structure described above, as shown in Figure 3 , the test method includes:

[0048] Step S1, a high level is input through the third metal layer of the test structure, and a low level is input through the fourth metal layer of the test structure.

[0049] Step S2, the current of the second doped region of the test structure is measured.

[0050] For example, the test structure can be connected with the probes on the probe card, a high level is input to the third metal layer through the probes, a low level is input to the fourth metal layer through the probes, and the current of the second doped region is measured through the probes.

[0051] In step S3, whether the flash memory device has the floating gate defect is determined according to the current of the second doped region.

[0052] For example, step S3 includes but is not limited to: detecting whether the current of the second doped region is higher than a target current (the target current can be determined by experience and / or simulation); if the current of the second doped region is higher than the target current, it is determined that the flash memory device integrated on the substrate has the floating gate defect (on the contrary, if the current of the second doped region is not higher than the target current, it is determined that the flash memory device integrated on the substrate does not have the floating gate defect).

[0053] In summary, in the embodiments of the present application, by forming a test structure on a substrate integrated with a flash memory device, inputting a high level to the third metal layer of the test structure and a low level to the fourth metal layer of the test structure, and measuring the current of the second doped region of the test structure, whether the flash memory device has the floating gate defect is determined according to the current of the second doped region, so that the floating gate defect of the flash memory device can be monitored, and the reliability and yield of the product are improved.

[0054] Obviously, the above embodiments are only examples for clear illustration, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments do not need to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A test structure, characterized in that, The test structure is used to detect floating gate defects in flash memory devices. The test structure is formed on a substrate and includes: The doped region is formed in the substrate and includes a first doped region, a second doped region and a third doped region from bottom to top. The substrate is doped with a first type of impurity, the first doped region is doped with a second type of impurity, the second doped region is doped with the first type of impurity, the third doped region is doped with the second type of impurity, and an STI structure is formed in the third doped region. A floating gate is formed above the substrate and between the STI structure, and a gate dielectric layer is formed between the floating gate and the substrate; A control gate, the control gate being formed on the floating gate; Viewed from above, the multiple floating gates and the multiple control gates are located within the third doping region. The floating gates and the control gates are strip-shaped and perpendicular to each other. The spacing between the multiple floating gates is the same, and the spacing between the multiple control gates is the same. A first metal layer and a second metal layer are also formed in the third doped region. The first metal layer and the second metal layer are located on both sides of the region occupied by the plurality of floating gates and the plurality of control gates. The two ends of the plurality of control gates are respectively connected to the first metal layer and the second metal layer. The area of ​​the second doped region is larger than the area of ​​the third doped region. A third metal layer and a fourth metal layer are also formed on the substrate. The third metal layer is connected to the second metal layer, and the fourth metal layer is connected to the second doped region but does not contact the third doped region.

2. The test structure according to claim 1, characterized in that, The first doped region is the drift region of the flash memory device, the second doped region is the well region of the flash memory device, and the third doped region is the threshold voltage adjustment region of the flash memory device.

3. The test structure according to claim 2, characterized in that, The substrate also includes a cell region for integrating the flash memory device. The floating gates of the flash memory device and the floating gates of the test structure have the same critical dimensions, and the distance between the floating gates of the flash memory device is the same as the distance between the floating gates in the test structure.

4. The test structure according to claim 3, characterized in that, When the floating gate defect of the flash memory device is detected through the test structure, a high level is input through the third metal layer and a low level is input through the fourth metal layer.

5. The test structure according to any one of claims 1 to 4, characterized in that, The flash memory device is a NOR flash memory device.

6. A testing method, characterized in that, The method is performed using the test structure as described in any one of claims 1 to 5, and the test method includes: A high level is input through the third metal layer of the test structure, and a low level is input through the fourth metal layer of the test structure. Measure the current in the second doped region of the test structure; The presence of a floating gate defect in the flash memory device is determined based on the current in the second doped region.

7. The method according to claim 6, characterized in that, The step of determining whether a flash memory device has a floating gate defect based on the current in the second doped region includes: Detect whether the current in the second doped region is higher than the target current; If the current in the second doped region is higher than the target current, then the flash memory device is determined to have a floating gate defect.

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