A fan-out package structure of a chip and a method of manufacturing the same

Abstract

The application discloses a fan-out packaging structure of a chip, which comprises a chip encapsulating layer, a rewiring layer and a conductive connecting piece arranged in sequence, the chip encapsulating layer comprises a silicon substrate provided with a plurality of grooves on one side close to the rewiring layer and a chip fixed in the grooves, the chip is electrically connected with the conductive connecting piece through the rewiring layer, and the sidewall of the chip is connected with the sidewall of the groove through a silicon-based alloy layer. The application further discloses a preparation method of the fan-out packaging structure of the chip. The application has good heat dissipation effect, high reliability, can prevent warping and is low in material cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip packaging, and particularly relates to a fan-out packaging structure of a chip and a preparation method thereof. BACKGROUND

[0002] In the prior art, the fan-out packaging structure of a chip is mechanically supported by a carrier for the packaging process of the chip, and the carrier is removed by a bonding-unbonding process. In a Die-First fan-out packaging process, the pins of the chip are connected to the pads on the multi-layer wiring layer. In order to reduce the displacement between the pin conductive pillars and the pads caused by the CTE mismatch of the packaging materials of the chip and the welding defects, the pin conductive pillars of the chip are usually filled with bottom glue liquid by capillary action, and the mechanical stress caused by the CTE mismatch of various packaging materials is redistributed. In addition, the chip is encapsulated with a resin substrate to provide reliable protection against the external environment. However, the CTE of the resin substrate is usually inconsistent with that of other packaging materials, which can easily exacerbate the warping of the chip and increase the risk of reliability testing and failure during the service period of the chip. Moreover, the poor thermal conductivity of the encapsulation layer of the resin substrate is not conducive to the heat dissipation of the chip. SUMMARY

[0003] In view of the deficiencies in the prior art, the application provides a fan-out packaging structure of a chip and a preparation method thereof, which has good heat dissipation effect, high reliability and is not prone to warping.

[0004] In a first aspect, a fan-out packaging structure of a chip includes a chip encapsulation layer, a redistribution layer and a conductive connecting member arranged in sequence. The chip encapsulation layer includes a silicon substrate with a plurality of grooves on a side close to the redistribution layer and a chip fixed in the grooves. The chip is electrically connected to the conductive connecting member through the redistribution layer. The sidewall of the chip is connected to the sidewall of the groove through a silicon-based alloy layer.

[0005] Preferably, the silicon-based alloy layer is formed by high-temperature sintering of the silicon material of the sidewall of the chip, the silicon material of the sidewall of the groove and a metal paste.

[0006] Preferably, the bottom surface of the chip is adhered to the bottom surface of the groove through a glue film layer.

[0007] Further, the glue film layer is formed by pressing the glue film on the bottom surface of the groove in a molten state.

[0008] Preferably, the grooves are prepared by a wet etching or dry etching process.

[0009] In a second aspect, a preparation method of a fan-out packaging structure of a chip includes the following steps:

[0010] Prepare a silicon substrate and fabricate several grooves on the silicon substrate;

[0011] Prepare a passive chip with an adhesive film attached to its surface, and place the chip in the groove;

[0012] The adhesive film is heated and melted to fill the bottom surface of the groove;

[0013] A silicon-based alloy layer is formed by filling the groove with metal paste and sintering it.

[0014] Grind the upper surface of the silicon substrate until the chip surface is exposed;

[0015] A redistribution layer and electrical connectors are fabricated on the surface of the chip.

[0016] The silicon substrate is thinned and the chip packaging structure is segmented.

[0017] Preferably, the groove is formed by a wet etching process or a dry etching process.

[0018] Furthermore, in the wet etching process, the fabrication of several grooves on the silicon substrate includes the following steps:

[0019] A chemical etching resistant film is prepared on the bottom surface and around the periphery of the silicon substrate;

[0020] A protective film is prepared on the top surface of the silicon substrate;

[0021] Remove the portion of the protective film corresponding to the groove etching area;

[0022] The groove is prepared by wet etching of the groove etching area, forming the bottom surface and sidewalls of the groove.

[0023] Preferably, the step of heating and melting the adhesive film to fill the bottom surface of the groove includes the following steps:

[0024] The adhesive film is melted by negative pressure heating treatment;

[0025] The molten adhesive film flows into the recess at the bottom of the groove to form an adhesive film layer;

[0026] Pressing down the chip causes the adhesive film layer to be tightly bonded to the back of the chip.

[0027] Preferably, the step of filling the groove with metal paste and sintering to form a silicon-based alloy layer includes the following steps:

[0028] Metal paste is filled in the gap between the chip sidewall and the groove sidewall, as well as in the active surface of the chip.

[0029] The chip is placed under high-temperature sintering conditions, and the organic components in the metal paste are volatilized and / or cracked off, forming a silicon-based alloy layer between the silicon material of the chip side wall and the silicon material of the groove side wall.

[0030] Compared with the prior art, the present application has the following beneficial effects:

[0031] 1. By using a silicon substrate as the packaging material, the silicon packaging material has the characteristics of low chemical reactivity and high reliability compared with the conventional resin-based packaging layer, and the CTE of the silicon packaging layer is consistent with the silicon substrate of the chip, which can reduce the warping degree caused by the CTE mismatch between various packaging materials in the prior art;

[0032] 2. By forming a silicon-based alloy layer between the chip side wall and the silicon substrate side wall, a heat dissipation channel of chip side wall-silicon-based alloy layer-silicon substrate is formed between the chip and the external environment, and the silicon-based alloy layer with high thermal conductivity is used in the heat dissipation channel, which is beneficial to the heat dissipation of the chip;

[0033] 3. In the prior art, the carrier board provides mechanical support for the chip packaging process, and after the debonding step, the carrier board is usually not reusable, which increases the material cost caused by the carrier board, especially the glass carrier board commonly used in existing industrial production, and the cost of the glass carrier board is about 10 times that of the silicon substrate. In the present application, the silicon substrate is directly used as the packaging material to provide mechanical support for the chip packaging process, which can greatly reduce the material cost;

[0034] 4. Since the present application does not require a bonding-debonding process, the process yield is improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0036] Figure 1 It is a structural schematic diagram of a fan-out packaging structure of a chip according to the present application;

[0037] Figure 2 It is another structural schematic diagram of a fan-out packaging structure of a chip according to the present application;

[0038] Figure 3 It is a flowchart of a preparation method of a fan-out packaging structure of a chip according to the present application based on wet etching;

[0039] Figures 4 to 10Respectively, the structural state schematic diagram of steps S101-S107 of the chip fan-out packaging structure preparation method based on wet etching is shown in the figure;

[0040] Figure 11 The fan-out packaging structure prepared based on wet etching of the chip fan-out packaging structure preparation method is shown in the figure;

[0041] Figure 12 The flow chart of the chip fan-out packaging structure preparation method based on dry etching is shown in the figure;

[0042] Figures 13 to 17 Respectively, the structural state schematic diagram of steps S201-S106 of the chip fan-out packaging structure preparation method based on dry etching is shown in the figure;

[0043] Figure 18 The fan-out packaging structure prepared based on dry etching of the chip fan-out packaging structure preparation method is shown in the figure.

[0044] Wherein:

[0045] 1 silicon substrate;

[0046] 2a chemical etching resistant film;

[0047] 3a protective film;

[0048] 4a groove etching area;

[0049] 5, 5a, 5b grooves; 51a, 51b groove bottom surfaces; 52a, 52b groove sidewalls;

[0050] 6, 6a, 6b silicon-based alloy layers;

[0051] 7, 7a, 7b dielectric layers;

[0052] 8, 8a, 8b metal wiring layers;

[0053] 9, 9a, 9b solder balls;

[0054] 10a, 10b separation channels;

[0055] 11, 11a', 11b' adhesive film layers; 11a, 11b adhesive films;

[0056] 12a, 12b built-in pads. DETAILED DESCRIPTION

[0057] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0058] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0059] In a first aspect, the present application discloses a fan-out package structure of a chip, comprising a chip encapsulation layer, a redistribution layer and a conductive connecting member arranged in sequence, the chip encapsulation layer comprises a silicon substrate 1 provided with a plurality of grooves 5 on one side close to the redistribution layer and a chip fixed in the grooves 5, and the chip is electrically connected with the conductive connecting member through the redistribution layer; the sidewall of the chip is connected with the sidewall of the groove 5 through a silicon-based alloy layer 6.

[0060] In the embodiment, as shown in Figure 1 , Figure 2 The redistribution layer comprises a dielectric layer 7 and a metal trace layer 8. The conductive connecting member comprises a solder pad (not shown in the figure) and a solder ball 9. As an embodiment, the silicon-based alloy layer can be formed by silicon material of the sidewall of the chip, silicon material of the sidewall of the groove 5 and metal paste through high-temperature sintering. Compared with the prior art, the silicon material of the silicon substrate is used to encapsulate the chip in the embodiment, and the encapsulation material of the encapsulation layer is used to replace the traditional plastic encapsulation material. In addition, the groove can be made by a wet etching or dry etching process.

[0061] The silicon-based alloy layer 6 is used to conduct the Joule heat generated by the chip in the embodiment, and the silicon material provided by the silicon substrate 1 is used for encapsulating the chip, which provides reliable protection for the chip (compared with the traditional plastic encapsulation material, the silicon material has high stable covalent bond, which can provide good reliable protection for the chip) and avoids warping. In addition, the cost of the silicon material is much lower than that of the commonly used plastic encapsulation material (such as EMC4511). In summary, the fan-out package structure of the chip in the embodiment has good heat dissipation effect, high reliability and low material cost.

[0062] In an embodiment, the bottom surface of the chip is bonded to the bottom surface of the groove 5 through an adhesive film layer 11.

[0063] The adhesive film layer 11 is formed by pressing an adhesive film located on the bottom surface of the groove (or the bottom surface of the chip) in a molten state, thereby achieving a tight connection between the bottom surface of the chip and the bottom surface of the groove 5. The silicon material of the silicon substrate 1, the silicon-based alloy layer 6, and the adhesive film layer 11 together encapsulate the chip.

[0064] Secondly, this invention also discloses a method for fabricating a fan-out packaging structure for a chip, which can be based on a wet chemical etching process or a dry etching process, as detailed below:

[0065] Wet process embodiment: A method for fabricating a fan-out packaging structure for a chip, such as... Figure 3 As shown, it includes the following steps:

[0066] S101: Prepare a silicon substrate, the bottom and sides of which have anti-chemical etching films, and the top surface has a protective film; remove a portion of the protective film corresponding to the groove etching area.

[0067] In this step, such as Figure 4 As shown, a silicon substrate 1a is prepared, and an anti-chemical etching film 2a is prepared on the bottom surface and around the periphery of the silicon substrate 1a. A protective film 3a is prepared on the top surface of the silicon substrate 1a. The portion of the protective film 3a corresponding to the groove etching area 4a is removed.

[0068] The chemical etch-resistant film 2a can be prepared as a silicon nitride film or a chemically etch-resistant wax film using a deposition method; the protective film 3a can be made of the same material as the chemical etch-resistant film 2a. The preparation of the chemical etch-resistant film and the protective film is to provide protection for the area outside the etched groove 5a in subsequent steps, and the materials used for the chemical etch-resistant film and the protective film are not limited to silicon nitride or wax. Furthermore, the portion of the protective film 3a corresponding to the etched area 4a of the groove can be removed using dry etching, laser ablation, or other methods.

[0069] S102: The groove is prepared using a wet etching process.

[0070] In this step, such as Figure 5 As shown, a silicon substrate 1a is placed in a wet chemical etching tank, and chemical reagents are used to wet etch the groove etching area 4a to prepare the groove 5a, forming the bottom surface 51a and the sidewall 52a of the groove.

[0071] The chemical reagent can be an alkaline wet etching reagent or an acidic wet etching reagent; the alkaline wet etching reagent can be a KOH-H2O system or a NaOH-H2O system; the acidic wet etching reagent can be an HNO3-HF-H2O system.

[0072] S103: Prepare a chip with an adhesive film attached to its passive surface, and place the chip in the groove.

[0073] In this step, such as Figure 6 As shown, the adhesive film 11a is in contact with the bottom surface 51a of the groove, and there is a gap between the chip 100 and the side wall 52a of the groove. The bottom surface of the chip 100 is covered with the adhesive film 11a, and the chip has an internal solder pad 12a.

[0074] S104: Heat and melt the adhesive film to fill the bottom surface of the groove, and press the chip tightly; fill the groove with metal paste and sinter to form a silicon-based alloy layer.

[0075] In this step, such as Figure 7 As shown, the silicon substrate 1a is first subjected to negative pressure heating to melt the adhesive film 11a. The molten adhesive film flows into the corresponding pit on the bottom surface 51a of the groove (forming the adhesive film layer 11a'). An airbag is used to press down on the chip 100 to make the contact between the flowing adhesive film and the passive surface of the chip tighter. Next, metal paste is filled into the active surface and gaps of the chip 100. Finally, the chip is placed under high-temperature conditions for metal sintering to volatilize and / or decompose the organic components in the metal paste, forming a silicon-based alloy layer 6a between the silicon material on the chip sidewall, the gap, and the silicon material on the groove sidewall.

[0076] The metal paste can be a metal paste obtained by the preparation method disclosed in CN107921533B, or a metal paste commonly used in the electronics industry, used to sinter with silicon materials to form a silicon-based alloy layer.

[0077] S105: Grind the upper surface of the silicon substrate until the chip surface is exposed.

[0078] In this step, such as Figure 8 As shown, the silicon-based alloy layer 6a corresponding to the active surface of the chip 100 is removed by grinding until the silicon material on the surface of the chip 100 is exposed.

[0079] S106: Prepare a redistribution layer and electrical connectors on the surface of the chip.

[0080] In this step, such as Figure 9 As shown, a redistribution layer of a fan-out package structure is fabricated on the base surface corresponding to the active surface of the chip 100. The redistribution layer includes a dielectric layer 7a and a metal trace layer 8a. Electrical connections are fabricated on the metal trace layer, and the electrical connections may be external solder balls 9a.

[0081] S107: Thin the silicon substrate and divide it into chip packaging structures.

[0082] In this step, such asFigure 10 As shown, the lower surface of the silicon substrate 1a is thinned, and the chip 100 is cut along the separation channel 10a to obtain a chip package as shown in Figure 11 The chip package structure.

[0083] Dry method embodiment: a preparation method of a fan-out package structure of a chip, as shown in Figure 12 The method comprises the following steps:

[0084] S201: prepare a silicon substrate, and prepare a groove on the silicon substrate by using a dry etching process.

[0085] In this step, as shown in Figure 13 A silicon substrate 1b is prepared, and a groove 5b is etched by a dry etching process to form a groove bottom surface 51b and a groove sidewall 52b.

[0086] S202: prepare a chip with a glue film attached to the passive surface, and place the chip in the groove.

[0087] In this step, as shown in Figure 14 The glue film 11b is in contact with the groove bottom surface 51b, and there is a gap between the chip 200 and the groove sidewall 52b. The bottom surface of the chip 200 is attached with a glue film 11b, and the chip has a built-in pad 12b.

[0088] S203: heat and melt the glue film to fill the groove bottom surface and compress the chip; fill the groove with metal paste and sinter to form a silicon-based alloy layer.

[0089] In this step, as shown in Figure 15 The silicon substrate 1b is subjected to negative pressure heating treatment to melt the glue film 11b, and the molten glue film liquid flows into the corresponding recess of the groove bottom surface 51b (to form a glue film layer 11b′), and the air bag is used to press down the chip 200 to make the flowing glue film liquid and the passive surface of the chip more closely. Then fill the metal paste at the active surface of the chip 200 and the gap. Finally, place the chip in a high temperature condition for metal sintering, so that the organic components in the metal paste volatilize and / or crack, and a silicon-based alloy layer 6b is formed between the silicon material of the chip sidewall and the silicon material of the gap-groove sidewall.

[0090] The metal paste can be obtained by the preparation method disclosed in CN107921533B, or a general metal paste used in the electronic industry, which is used for sintering with silicon material to form a silicon-based alloy layer.

[0091] S204: grind the upper surface of the silicon substrate to expose the surface of the chip.

[0092] In this step, as shown in Figure 16As shown, the corresponding silicon-based alloy layer 6b on the active surface of the chip 200 is removed by grinding until the silicon material on the surface of the chip 200 is exposed.

[0093] S205: preparing a redistribution layer and electrical connectors on the surface of the chip.

[0094] In this step, as shown, a redistribution layer of the fan-out package structure is prepared on the surface corresponding to the active surface of the chip 200, and the redistribution layer includes a dielectric layer 7b and a metal trace layer 8b. Electrical connectors, which can be external solder balls 9b, are prepared on the metal trace layer. Figure 17

[0095] S206: thinning the silicon substrate and separating the chip package structure.

[0096] In this step, as shown, the lower surface of the silicon substrate 1b is thinned, and the chip 200 is cut along the separation channel 10b to obtain a chip package structure as shown. Figure 17 Figure 18

[0097] The above-described embodiments only express several embodiments of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of protection of the present application.​​​

Claims

1. A fan-out package structure of a chip, comprising a chip encapsulation layer, a redistribution layer and a conductive connecting member arranged in sequence, characterized in that, The chip encapsulation layer comprises a silicon substrate provided with a plurality of grooves on one side close to the redistribution layer and a chip fixed in the grooves, and the chip is electrically connected with the conductive connecting piece through the redistribution layer; The sidewall of the chip and the sidewall of the groove are connected through a silicon-based alloy layer, and the silicon-based alloy layer is formed by the silicon material of the sidewall of the chip, the silicon material of the sidewall of the groove and metal paste through high-temperature sintering; The bottom surface of the chip is adhered to the bottom surface of the groove through a glue film layer.

2. The fan-out package structure of a chip according to claim 1, characterized in that: The glue film layer is formed by pressing the glue film on the bottom surface of the groove in a molten state.

3. The fan-out package structure of a chip according to claim 1, characterized in that: The groove is prepared by a wet etching or dry etching process.

4. A method for fabricating a fan-out packaging structure for a chip, characterized in that, The method comprises the following steps: Preparation of a silicon substrate, a plurality of grooves are prepared on the silicon substrate; Preparation of a passive surface with a glue film, the chip is placed in the groove; Melting the glue film to fill the groove bottom surface, the bottom surface of the chip is adhered to the bottom surface of the groove through a glue film layer; Filling metal paste in the groove and sintering to form a silicon-based alloy layer, the sidewall of the chip and the sidewall of the groove are connected through a silicon-based alloy layer, and the silicon-based alloy layer is formed by the silicon material of the sidewall of the chip, the silicon material of the sidewall of the groove and metal paste through high-temperature sintering; Grinding the upper surface of the silicon substrate to expose the surface of the chip; Preparation of a redistribution layer and an electrical connecting piece on the surface of the chip; Thinning the silicon substrate and dividing out the chip package structure.

5. The method for preparing a fan-out package structure of a chip according to claim 4, characterized in that: The groove is prepared by a wet etching or dry etching process.

6. The method for preparing a fan-out package structure of a chip according to claim 5, characterized in that: In the wet etching process, the preparation of a plurality of grooves on the silicon substrate comprises the following steps: Preparation of a chemical etching-resistant film on the bottom surface and the periphery of the silicon substrate; Preparation of a protective film on the top surface of the silicon substrate; Removing the protective film corresponding to the groove etching area; Wet etching of the groove etching area to prepare the groove, forming the groove bottom surface and the groove sidewall.

7. The method of claim 4, wherein the method further comprises: forming a plurality of redistribution layers on the plurality of dielectric layers; and forming a plurality of redistribution lines on the plurality of redistribution layers. The melting of the glue film to fill the groove bottom surface comprises the following steps: Melting the glue film by negative pressure heating treatment; Let the molten glue film flow into the groove bottom surface, forming a glue film layer; Pressing the chip to make the glue film layer tightly connected with the back surface of the chip.

8. The method of claim 4, wherein the method further comprises: forming a plurality of redistribution layers on the plurality of dielectric layers; and forming a plurality of redistribution lines on the plurality of redistribution layers. The filling of metal paste in the groove and sintering to form a silicon-based alloy layer comprises the following steps: Filling metal paste in the gap between the sidewall of the chip and the sidewall of the groove and on the active surface of the chip; Placing the chip in a high-temperature sintering condition, and making the organic components in the metal paste volatilize and / or crack, so as to form a silicon-based alloy layer between the silicon material of the sidewall of the chip and the silicon material of the sidewall of the groove.

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