Double-layer stacked 3D fan-out package structure and its packaging method

Abstract

The present invention provides a double-layer stacked 3D fan-out package structure and a preparation method thereof. The structure includes: a first semiconductor chip, a molding material layer, a metal connection column, a first redistribution layer, a second redistribution layer, a second semiconductor chip, solder bump, and an underfill layer. The formed package structure can package two layers of fan-out wafers in the three-dimensional direction. After cutting, a single package body has two layers of semiconductor chips in the three-dimensional direction, and the electrical signals of all semiconductor chips in the single package body are controlled by setting the first redistribution layer, the metal connection column, and the second redistribution layer, so that more chips can be packaged in a single package body, improving the integration of the package and reducing the package volume at the same time. Moreover, packaging multiple chips in the same package body can also effectively improve the performance of a single chip. Finally, the preparation method also provides the possibility of packaging more than three layers of fan-out wafers in a single package body.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a double-layer stacked 3D fan-out package structure and a packaging method thereof. Background Art

[0002] Lower cost, higher reliability, faster speed, and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will improve the integration density of various electronic components by continuously reducing the minimum feature size. Currently, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip, Package on Package (POP), and so on.

[0003] Fan-Out Wafer Level Package is a wafer-level processed embedded chip packaging method and is one of the current advanced packaging methods with a relatively large number of input / output ports (I / O) and good integration flexibility. Fan-Out Wafer Level Package has its unique advantages compared with conventional wafer-level packaging: ① The I / O pitch is flexible and does not depend on the chip size; ② Only effective dies are used, improving the product yield; ③ It has a flexible 3D packaging path, that is, any array of patterns can be formed on the top; ④ It has good electrical and thermal performance; ⑤ High-frequency applications; ⑥ It is easy to achieve high-density wiring in the redistribution layer (RDL).

[0004] Currently, most Fan-Out Wafer Level Packages are single-layer packages, that is, a layer of fan-out chip wafers is packaged on a carrier. The conventional process includes: providing a carrier, forming an adhesive layer on the surface of the carrier; mounting the semiconductor chip face up on the surface of the adhesive layer; coating a dielectric layer; lithography and electroplating to form the redistribution layer (RDL); using an injection molding process to encapsulate the semiconductor chip in a molding material layer; grinding and opening the molding; lithography and electroplating to form the under-bump metal layer; performing ball mounting and reflow to form a solder ball array; removing the carrier. The wafer package formed by this packaging method contains only one chip in the single chip package formed after cutting. Under the current higher density circuit requirements, the circuit interconnection between multiple chips needs to package multiple already packaged chip packages again, resulting in low integration, large packaging volume, and affecting the performance of a single chip at the same time. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a double-layer stacked 3D fan-out package structure and its packaging method, which are used to solve the problems of low integration, large package volume, and influence on the performance of a single chip in the prior art fan-out wafer-level packaging form.

[0006] To achieve the above and other related purposes, the present invention provides a double-layer stacked 3D fan-out package structure, and the package structure includes:

[0007] A first semiconductor chip;

[0008] A plastic encapsulation material layer, including an opposite first surface and a second surface, and the plastic encapsulation material layer encapsulates the periphery of the first semiconductor chip;

[0009] Metal connection posts, located within the plastic encapsulation material layer and penetrating through the plastic encapsulation material layer vertically;

[0010] A first redistribution layer, located on the first surface of the plastic encapsulation material layer and electrically connected to the first semiconductor chip and the metal connection posts;

[0011] A second redistribution layer, located on the second surface of the first plastic encapsulation material and electrically connected to the metal connection posts, so as to realize electrical connection between the first redistribution layer and the second redistribution layer through the metal connection posts, and the first semiconductor chip is bonded to the second redistribution layer;

[0012] A second semiconductor chip, located on the surface of the second redistribution layer away from the first semiconductor chip and electrically connected to the second redistribution layer;

[0013] Solder bump pads, located on the surface of the first redistribution layer away from the first semiconductor chip and electrically connected to the first redistribution layer;

[0014] An underfill layer, located between the second semiconductor chip and the second redistribution layer and in the lower peripheral area of the second semiconductor chip.

[0015] Optionally, the first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.

[0016] Optionally, the bare chip includes contact pads, a dielectric layer is formed on the bare chip, metal pillars penetrating the dielectric layer are formed in the dielectric layer, one end of the metal pillar is connected to the contact pad, and the other end is connected to the first redistribution layer or the second redistribution layer; the packaged chip includes contact pads, a solder connection structure is formed on the packaged chip, the solder connection structure includes metal pillars and solder balls, one end of the metal pillar is connected to the contact pad, the other end is connected to the solder ball, and the solder ball is further connected to the first redistribution layer or the second redistribution layer.

[0017] Optionally, the first redistribution layer and the second redistribution layer include: a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer; the material of the wiring dielectric layer includes one or a combination of two or more selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium.

[0018] Optionally, the encapsulation material layer includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer; the underfill layer includes an epoxy resin layer.

[0019] Optionally, the material of the solder bump is one material or a combined material of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium.

[0020] The present invention also provides a method for manufacturing a double-layer stacked 3D fan-out package structure, the manufacturing method including:

[0021] Providing a first support substrate and forming a separation layer on the first support substrate;

[0022] Forming a second redistribution layer on the separation layer;

[0023] Forming metal connection pillars on the second redistribution layer, the metal connection pillars being electrically connected to the second redistribution layer;

[0024] Providing a first semiconductor chip and bonding it to the second redistribution layer;

[0025] Forming an encapsulation material layer on the surface of the second redistribution layer, the encapsulation material layer filling the gap between the first semiconductor chip and the metal connection pillars and encapsulating the first semiconductor chip and the metal connection pillars; the encapsulation material layer includes an opposite first surface and a second surface, the second surface of the encapsulation material layer is in contact with the second redistribution layer, and the first surface of the encapsulation material layer exposes the metal connection pillars;

[0026] A first redistribution layer is formed on the first surface of the encapsulation material layer, and the first redistribution layer is electrically connected to the first semiconductor chip and the metal connection posts;

[0027] Solder bump protrusions are formed on the surface of the first redistribution layer away from the first semiconductor chip and are electrically connected to the first redistribution layer;

[0028] A second support substrate is provided and bonded to the first redistribution layer;

[0029] The first support substrate and the separation layer are removed to expose the second redistribution layer;

[0030] A second semiconductor chip is provided and electrically connected to the second redistribution layer;

[0031] An underfill layer is formed between the second semiconductor chip and the second redistribution layer and in the lower peripheral region of the second semiconductor chip;

[0032] The second support substrate is removed.

[0033] Optionally, the first support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, the second support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, the separation layer includes a polymer layer or an adhesive layer, and the polymer layer or the adhesive layer is first coated on the surface of the support substrate by a spin coating process and then cured and formed by an ultraviolet curing or thermal curing process.

[0034] Optionally, the first redistribution layer and the second redistribution layer include: a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer; the material of the wiring dielectric layer includes one or a combination of two or more selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium.

[0035] Optionally, the steps of forming the first redistribution layer and the second redistribution layer include:

[0036] A dielectric layer is formed by a chemical vapor deposition process or a physical vapor deposition process, and the dielectric layer is etched to form the wiring dielectric layer;

[0037] A metal layer is formed on the surface of the wiring dielectric layer by using a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or an electroless plating process, and the metal layer is etched to form the metal wiring layer, and the metal connection column is electrically connected to the metal wiring layer.

[0038] Optionally, the first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.

[0039] Optionally, the bare chip includes contact pads, a dielectric layer is formed on the bare chip, and metal pillars penetrating the dielectric layer are formed in the dielectric layer. One end of the metal pillar is connected to the contact pad, and the other end is connected to the first redistribution layer or the second redistribution layer; the packaged chip includes contact pads, and a solder connection structure is formed on the packaged chip. The solder connection structure includes a metal pillar and a solder ball. One end of the metal pillar is connected to the contact pad, and the other end is connected to the solder ball, and the solder ball is further connected to the first redistribution layer or the second redistribution layer.

[0040] As described above, the double-layer stacked 3D fan-out package structure and the preparation method thereof according to the present invention form a double-layer stacked 3D fan-out package structure that can package two layers of fan-out wafers in the three-dimensional direction (i.e., the thickness direction). After cutting, the formed single package body has two layers of semiconductor chips in the three-dimensional direction, and the electrical signals of all semiconductor chips in the single package body are controlled by setting the first redistribution layer, the metal connection column and the second redistribution layer, so that more chips can be packaged in a single package body, improving the integration of the fan-out wafer-level package and reducing the package volume at the same time; furthermore, packaging multiple chips in the same package body can also effectively improve the performance of a single chip; finally, the preparation method also provides the possibility of packaging more than three layers of fan-out wafers in a single package body. Description of the Drawings

[0041] Figure 1 It shows a schematic flow chart of the preparation method of the double-layer stacked 3D fan-out package structure according to Embodiment 1 of the present invention.

[0042] Figures 2 to 16 It shows a schematic structural diagram presented by each step in the preparation method of the double-layer stacked 3D fan-out package structure according to Embodiment 1 of the present invention, wherein Figure 16 It also shows a schematic structural diagram of the double-layer stacked 3D fan-out package structure according to Embodiment 2 of the present invention.

[0043] Description of Component Labels

[0044] 10 First support substrate

[0045] 11, 22 Separation layer

[0046] 12 Second Rewiring Layer

[0047] 121, 161 Wiring Dielectric Layers

[0048] 122, 162 Metal Wiring Layers

[0049] 123 Etching Window

[0050] 13 Metal Connecting Posts

[0051] 14 First Semiconductor Chip

[0052] 141, 191 Contact Pads

[0053] 142 Dielectric Layer

[0054] 143, 192 Metal Posts

[0055] 15 Encapsulation Material Layer

[0056] 16 First Rewiring Layer

[0057] 17 Solder Ball Bumps

[0058] 18 Second Support Substrate

[0059] 19 Second Semiconductor Chip

[0060] 193 Solder Balls

[0061] 20 Underfill Layer

[0062] 21 Adhesive Layer

[0063] Steps S1 to S12 Detailed Implementation Manner

[0064] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] Please refer to Figures 1 to 16 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be changed according to actual needs, and the component layout type may also be more complex.

[0066] Example 1

[0067] As Figure 1 shown, this embodiment provides a method for manufacturing a double-layer stacked 3D fan-out package structure. The double-layer stacked 3D fan-out package structure formed by using this manufacturing method can package two layers of fan-out wafers in the three-dimensional direction (i.e., the thickness direction). Each single package formed after cutting has two layers of semiconductor chips along the three-dimensional direction, and the electrical signals of all semiconductor chips in the single package are controlled by setting a first redistribution layer, metal connection posts, and a second redistribution layer, so that more chips can be packaged in a single package, improving the integration of the fan-out wafer-level package and reducing the package volume at the same time. Moreover, packaging multiple chips in the same package can also effectively improve the performance of a single chip. Finally, this manufacturing method also makes it possible to package more than three layers of fan-out wafers in a single package.

[0068] Specifically, as Figures 2 to 16 shown in [FIGURE], the structural schematic diagrams presented in each step of the method for manufacturing the double-layer stacked 3D fan-out package structure in this embodiment are illustrated. For ease of understanding, only one chip is shown for each layer of wafer in the presentation of each step, but those skilled in the art can understand that the number of chips on each layer of fan-out wafer is not less than one, generally several, that is, more than two.

[0069] As Figures 1 to 3 shown, first, step S1 is performed to provide a first support substrate 10 (as Figure 2 shown) and form a separation layer 11 (as Figure 3 shown) on the first support substrate 10.

[0070] As Figure 2 shown, as an example, the first support substrate 10 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the first support substrate 10 is selected as a glass substrate, which has a low cost, is easy to form a separation layer 11 on its surface, and can reduce the difficulty of the subsequent peeling process. The shape of the first support substrate 10 can be circular, square, or any other desired shape. In this embodiment, the first support substrate 10 is used to prevent problems such as cracking, warping, and breaking of semiconductor chips during the subsequent manufacturing process.

[0071] As Figure 3As shown, the separation layer 11 serves as a separation layer between the subsequently formed second redistribution layer 12 and other structures located on the second redistribution layer 12 and the first support substrate 10 in subsequent processes. It is preferably made of an adhesive material with a smooth surface. It must have a certain bonding force with the second redistribution layer 12 to ensure that the second redistribution layer 12 does not move or the like in subsequent processes. In addition, it should also have a strong bonding force with the first support substrate 10. Generally speaking, its bonding force with the first support substrate 10 needs to be greater than its bonding force with the second redistribution layer 12. As an example, the separation layer 11 includes a polymer layer or an adhesive layer. The polymer layer or the adhesive layer is first coated on the surface of the first support substrate 10 by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process.

[0072] In this embodiment, the polymer layer includes an LTHC photothermal conversion layer. When the first support substrate 10 is peeled off subsequently, the LTHC photothermal conversion layer can be heated based on a laser so that the second redistribution layer 12 and the first support substrate 10 are separated from each other at the LTHC photothermal conversion layer.

[0073] As Figure 1 and Figure 4 shown, then step S2 is performed to form the second redistribution layer 12 on the separation layer 11.

[0074] As Figure 4 shown, as an example, the second redistribution layer 12 includes a wiring dielectric layer 121 and a metal wiring layer 122 located in the wiring dielectric layer 121; the material of the wiring dielectric layer 121 includes one or a combination of two or more selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer 122 includes one or a combination of two or more selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium.

[0075] As an example, forming the second redistribution layer 12 includes the following steps: First, a dielectric layer is formed on the surface of the separation layer 11 by a chemical vapor deposition process or a physical vapor deposition process, and the dielectric layer is etched to form the wiring dielectric layer 121; then a metal layer is formed on the surface of the wiring dielectric layer 121 by a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or an electroless plating process, and the metal layer is etched to form the metal wiring layer 122. It should be noted here that the materials, layers, and distribution morphologies of the wiring dielectric layer 121 and the metal wiring layer 122 can be set according to the specific situation of the semiconductor chip and are not limited herein.

[0076] AsFigure 1 and Figure 5 As shown in Figure 5 , then step S3 is performed to form metal connection posts 13 on the second redistribution layer 12, and the metal connection posts 13 are electrically connected to the second redistribution layer 12.

[0077] As Figure 5 shown, as an example, when the second redistribution layer 12 includes a wiring dielectric layer 121 and a metal wiring layer 122 located within the wiring dielectric layer 121, the metal connection posts 13 are electrically connected to the second redistribution layer 12 by contacting the metal wiring layer 122.

[0078] As an example, the metal connection posts 13 include one or a combination of gold wire, silver wire, copper wire, and aluminum wire; the metal connection posts 13 may also include one or a combination of gold posts, silver posts, copper posts, and aluminum posts; the method for forming the metal connection posts 13 includes one or a combination of wire bonding, electroplating, and electroless plating.

[0079] Specifically, the metal connection posts 13 can use copper wire and be prepared by a wire bonding process, such as one or a combination of a thermocompression wire bonding process, an ultrasonic wire bonding process, and a thermocompression ultrasonic wire bonding process. The type and preparation method of the metal connection posts 13 can also be selected according to needs and are not limited here.

[0080] . As Figure 1 and Figure 6 shown, then step S4 is performed to provide a first semiconductor chip 14 and bond it to the second redistribution layer 12.

[0081] As an example, the form of the first semiconductor chip 14 is not limited, that is, the first semiconductor chip 14 can be a bare chip without encapsulation or a packaged chip, and in this fan-out type wafer, the forms of the first semiconductor chips 14 can be the same or different, which are specifically set according to actual needs. As Figure 6 shown, the first semiconductor chip 14 is a bare chip, the bare chip includes contact pads 141, a dielectric layer 142 is formed on the bare chip, and metal posts 143 penetrating through the dielectric layer 142 are formed in the dielectric layer 142. One end of the metal post 143 is connected to the contact pad 141, and the other end is connected to a subsequent first redistribution layer 16.

[0082] As Figure 6As shown, by way of example, the first semiconductor chip 14 can be bonded to the second redistribution layer 12 through an adhesive layer 21 to ensure that the first semiconductor chip 14 does not move during subsequent processes and use. The material of the adhesive layer 21 can be a tape with adhesiveness on both sides or an adhesive made by a spin coating process, etc., but is not limited thereto, as long as the adhesive layer 21 has the required adhesive properties.

[0083] As Figure 1 and Figure 7 , Figure 8 shown, then step S5 is carried out to form a molding compound layer 15 on the surface of the second redistribution layer 12. The molding compound layer 15 fills the gap between the first semiconductor chip 14 and the metal connection posts 13 and encapsulates the first semiconductor chip 14 and the metal connection posts 13; the molding compound layer 15 includes an opposite first surface and a second surface. The second surface of the molding compound layer 15 is in contact with the second redistribution layer 12, and the first surface of the molding compound layer 15 exposes the metal connection posts 13.

[0084] By way of example, the molding compound layer 15 includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer; the method for forming the molding compound layer 15 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating.

[0085] Specifically, first, a layer of molding compound layer 15 is formed on the surface of the second redistribution layer 12 (as Figure 7 shown), and then a grinding or polishing method is applied to the upper surface of the molding compound layer 15 to provide a flat molding compound layer 15 (as Figure 8 shown), improving the product quality.

[0086] In another example, the molding compound layer 15 can also be formed according to the height of the metal connection posts 13 such that the height of the formed molding compound layer 15 is exactly the same as the height of the metal connection posts 13, that is, the first surface of the molding compound layer 15 is flush with the surface of the metal connection posts 13. In this way, the step of grinding the molding compound layer 15 can be omitted, thus simplifying the process steps.

[0087] As Figure 1 and Figure 9As shown, then step S6 is carried out to form a first redistribution layer 16 on the first surface of the encapsulation material layer 15, and the first redistribution layer 16 is electrically connected to the first semiconductor chip 14 and the metal connection posts 13. After this step, the electrical signals of the first semiconductor chip 14 are controlled by the first redistribution layer 16, and the electrical signals of the subsequently formed second semiconductor chip 19 are controlled by the first redistribution layer 16 through the second redistribution layer 12 and the metal connection posts 13, that is, both the first semiconductor chip 14 and the subsequently formed second semiconductor chip 19 are controlled by the first redistribution layer 16.

[0088] As Figure 9 shown, as an example, the first redistribution layer 16 includes a wiring dielectric layer 161 and a metal wiring layer 162 located within the wiring dielectric layer 161; the material of the wiring dielectric layer 161 includes one or a combination of two or more selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer 162 includes one or a combination of two or more selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium.

[0089] As an example, forming the first redistribution layer 16 includes the following steps: First, a dielectric layer is formed on the surface of the encapsulation material layer 15 by chemical vapor deposition or physical vapor deposition, and the dielectric layer is etched to form the wiring dielectric layer 161; then, a metal layer is formed on the surface of the wiring dielectric layer 161 by chemical vapor deposition, physical vapor deposition, sputtering, electroplating, or electroless plating, and the metal layer is etched to form the metal wiring layer 162. It should be noted here that the materials, number of layers, and distribution morphology of the wiring dielectric layer 161 and the metal wiring layer 162 can be set according to the specific situation of the semiconductor chip, and are not limited herein.

[0090] As Figure 1 and Figure 10 shown, then step S7 is carried out to form solder bump 17 on the surface of the first redistribution layer 16 away from the first semiconductor chip 14 and make it electrically connected to the first redistribution layer 16.

[0091] As an example, the material of the solder bump 17 is one material or a combined material of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium, and the solder bump 17 can be formed by a ball placement reflow process.

[0092] As Figure 1 and Figure 11 shown, then step S8 is carried out to provide a second support substrate 18 and bond it to the first redistribution layer 16.

[0093] As shown Figure 11 in the figure, by way of example, the second support substrate 18 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the second support substrate 18 is selected as a glass substrate, which has a low cost, is easy to form a separation layer 22 on its surface, and can reduce the difficulty of subsequent peeling processes. The shape of the second support substrate 18 can be a wafer shape, a square shape, or any other desired shape. In this embodiment, the second support substrate 18 is used to prevent problems such as cracking, warping, and breaking of the semiconductor chip during subsequent manufacturing processes.

[0094] As shown Figure 11 in the figure, by way of example, the bonding between the second support substrate 18 and the first redistribution layer 16 can be achieved by providing a separation layer 22 therebetween. By way of example, the separation layer 22 includes a polymer layer or an adhesive layer.

[0095] As shown Figure 1 and Figure 12 in the figure, then step S9 is performed to remove the first support substrate 10 and the separation layer 11 to expose the second redistribution layer 12.

[0096] By way of example, when the separation layer 11 includes an adhesive layer, an exposure method can be used to reduce the adhesiveness of the adhesive to achieve its separation from the second redistribution layer 12; when the separation layer 11 includes an LTHC photothermal conversion layer, the LTHC photothermal conversion layer is heated based on a laser to cause the second redistribution layer 12 and the first support substrate 10 to separate from each other at the LTHC photothermal conversion layer.

[0097] As shown Figure 1 and Figure 13 , Figure 14 in the figure, then step S10 is performed to provide a second semiconductor chip 19 and electrically connect it to the second redistribution layer 12. After this step, the second semiconductor chip 19 is electrically connected to the second redistribution layer 12, and the second redistribution layer 12 is electrically connected to the first redistribution layer 16 through the metal connection posts 13, thereby achieving electrical connection between the first redistribution layer 16 and the second redistribution layer 12.

[0098] By way of example, the form of the second semiconductor chip 19 is not limited, that is, the second semiconductor chip 19 can be a bare chip without encapsulation or a packaged chip. And in this fan-out wafer, the forms of the second semiconductor chips 19 can be the same or different, which is specifically set according to actual needs. As shown Figure 14As shown, the second semiconductor chip 19 is a packaged chip. The packaged chip includes contact pads 191. A solder connection structure is formed on the packaged chip. The solder connection structure includes metal pillars 192 and solder balls 193. One end of the metal pillar 192 is connected to the contact pad 191, and the other end is connected to the solder ball 193. The solder ball 193 is then connected to the second redistribution layer 12. As Figure 13 shown, first, a laser etching, such as infrared laser etching, is used to form an etching window 123 in the wiring dielectric layer 121 of the second redistribution layer 12, and the etching window 123 exposes the metal wiring layer 122; as Figure 14 shown, then, the electrical connection between the second semiconductor chip 19 and the second redistribution layer 12 is realized through the solder ball 193.

[0099] As Figure 1 and Figure 15 shown, then, step S11 is performed. An underfill layer 20 is formed between the second semiconductor chip 19 and the second redistribution layer 12 and in the lower region on the periphery of the second semiconductor chip 19. Setting the underfill layer 20 can improve the bonding strength between the second semiconductor chip 19 and the second redistribution layer 12 and protect the second redistribution layer 12. Based on this, the material particles of the underfill layer 20 are relatively small compared to the encapsulation material layer, so the bonding strength of the underfill layer 20 is better and it can effectively protect the second redistribution layer 12, and it can be achieved by only one-step underfill process. The process is simple, can meet most of the packaging requirements, and has a lower cost.

[0100] As an example, the underfill layer is an epoxy resin layer, but it can also be other filling materials with relatively small particles. The method for forming the underfill layer 20 includes, but is not limited to, one or more of inkjet printing, dispensing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating.

[0101] As Figure 1 and Figure 16 shown, finally, step S12 is performed to remove the second support substrate 18.

[0102] As an example, when the second support substrate 18 is adhered to the first redistribution layer 16 through the separation layer 22; in the first case, when the separation layer 22 includes an adhesive layer, an exposure method can be used to reduce the viscosity of the adhesive to achieve its separation from the first redistribution layer 16; when the separation layer 22 includes an LTHC photothermal conversion layer, the LTHC photothermal conversion layer is heated based on a laser to cause the first redistribution layer 16 and the second support substrate 18 to be separated from each other at the LTHC photothermal conversion layer.

[0103] Embodiment 2

[0104] This embodiment provides a double-layer stacked 3D fan-out package structure. This package structure can be fabricated using the manufacturing method of the first embodiment above, but is not limited to the manufacturing method described in the first embodiment, as long as the double-layer stacked 3D fan-out package structure can be formed. For the beneficial effects that can be achieved by this double-layer stacked 3D fan-out package structure, please refer to the first embodiment, which will not be elaborated here.

[0105] As shown in Figure 16 , the double-layer stacked 3D fan-out package structure includes:

[0106] A first semiconductor chip 14;

[0107] A molding material layer 15, including a first surface and a second surface opposite to each other, and the molding material layer 15 is molded around the first semiconductor chip 14;

[0108] A metal connection post 13, located within the molding material layer 15 and penetrating the molding material layer 15 vertically;

[0109] A first redistribution layer 16, located on the first surface of the molding material layer 15 and electrically connected to the first semiconductor chip 14 and the metal connection post 13;

[0110] A second redistribution layer 12, located on the second surface of the first molding material 15 and electrically connected to the metal connection post 13, so as to electrically connect the first redistribution layer 16 and the second redistribution layer 12 through the metal connection post 13, and the first semiconductor chip 14 is bonded to the second redistribution layer 12;

[0111] A second semiconductor chip 19, located on the surface of the second redistribution layer 12 away from the first semiconductor chip 14 and electrically connected to the second redistribution layer 12;

[0112] A solder bump 17, located on the surface of the first redistribution layer 16 away from the first semiconductor chip 14 and electrically connected to the first redistribution layer 16;

[0113] An underfill layer 20, located between the second semiconductor chip 19 and the second redistribution layer 12 and in the lower region on the periphery of the second semiconductor chip.

[0114] As an example, the first semiconductor chip 14 is a bare chip or a packaged chip, and the second semiconductor chip 19 is a bare chip or a packaged chip. As shown in Figure 16As shown, the first semiconductor chip 14 is a bare chip, and the second semiconductor chip 19 is a packaged chip. Further, the bare chip includes contact pads 141, a dielectric layer 142 is formed on the bare chip, and metal posts 143 penetrating the dielectric layer 142 are formed in the dielectric layer 142. One end of the metal post 143 is connected to the contact pad 141, and the other end is connected to the first redistribution layer 16; the packaged chip includes contact pads 191, and a solder connection structure is formed on the packaged chip. The solder connection structure includes a metal post 192 and a solder ball 193. One end of the metal post 192 is connected to the contact pad 191, and the other end is connected to the solder ball 193, and the solder ball 193 is further connected to the second redistribution layer 12.

[0115] As an example, the first redistribution layer 16 and the second redistribution layer 12 include: wiring dielectric layers 121, 161 and metal wiring layers 122, 162 located in the wiring dielectric layers 121, 161; the materials of the wiring dielectric layers 121, 161 include one or a combination of two or more selected from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the materials of the metal wiring layers 122, 162 include one or a combination of two or more selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium.

[0116] As an example, the encapsulation material layer 15 includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer; the underfill layer 20 includes an epoxy resin layer.

[0117] As an example, the material of the solder bump 17 is one material or a combined material of two or more materials selected from copper, aluminum, nickel, gold, silver, and titanium.

[0118] In summary, the present invention provides a double-layer stacked 3D fan-out package structure and a preparation method thereof. The formed double-layer stacked 3D fan-out package structure can package two layers of fan-out wafers in the three-dimensional direction (i.e., the thickness direction). Each single package formed after cutting has two semiconductor chips along the three-dimensional direction, and the electrical signals of all semiconductor chips in a single package are controlled by setting the first redistribution layer, metal connection posts, and the second redistribution layer, so that more chips can be packaged in a single package, improving the integration of the fan-out wafer-level package and reducing the package volume at the same time. Moreover, packaging multiple chips in the same package can effectively improve the performance of a single chip. Finally, this preparation method also provides the possibility of packaging more than three layers of fan-out wafers in a single package. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0119] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A preparation method of a double-layer stacked 3D fan-out package structure, characterized in that, The preparation method includes: providing a first support substrate and forming a separation layer on the first support substrate; forming a second redistribution layer on the separation layer; forming metal connection posts on the second redistribution layer, and the metal connection posts are electrically connected to the second redistribution layer; providing a first semiconductor chip and bonding it to the second redistribution layer; forming a molding compound layer on the surface of the second redistribution layer, the molding compound layer filling the gap between the first semiconductor chip and the metal connection posts and encapsulating the first semiconductor chip and the metal connection posts; the molding compound layer includes an opposite first surface and a second surface, the second surface of the molding compound layer is in contact with the second redistribution layer, and the first surface of the molding compound layer exposes the metal connection posts; forming a first redistribution layer on the first surface of the molding compound layer, and the first redistribution layer is electrically connected to the first semiconductor chip and the metal connection posts; forming solder bump protrusions on the surface of the first redistribution layer away from the first semiconductor chip and making them electrically connected to the first redistribution layer; providing a second support substrate and bonding it to the first redistribution layer; removing the first support substrate and the separation layer to expose the second redistribution layer; providing a second semiconductor chip and electrically connecting it to the second redistribution layer; forming an underfill layer between the second semiconductor chip and the second redistribution layer and in the lower peripheral region of the second semiconductor chip; removing the second support substrate.

2. The method for preparing the double-layer stacked 3D fan-out package structure according to claim 1, wherein: The first support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, the second support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, the separation layer includes a polymer layer or an adhesive layer, the polymer layer or the adhesive layer is first coated on the surface of the support substrate by a spin coating process and then cured and formed by an ultraviolet curing or thermal curing process.

3. The manufacturing method of the double-layer stacked 3D fan-out package structure according to claim 1, characterized in that: The first redistribution layer and the second redistribution layer include: a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer; the material of the wiring dielectric layer includes one or a combination of two or more selected from the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium.

4. The method for manufacturing a double-layer stacked 3D fan-out package structure according to claim 3, wherein, The steps of forming the first redistribution layer and the second redistribution layer include: forming a dielectric layer by a chemical vapor deposition process or a physical vapor deposition process and etching the dielectric layer to form the wiring dielectric layer; forming a metal layer on the surface of the wiring dielectric layer by a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or a chemical plating process and etching the metal layer to form the metal wiring layer, and the metal connection posts are electrically connected to the metal wiring layer.

5. The manufacturing method of the double-layer stacked 3D fan-out package structure according to claim 1, characterized in that: The first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.

6. The preparation method of the double-layer stacked 3D fan-out package structure according to claim 5, wherein: The bare chip includes contact pads, and a dielectric layer is formed on the bare chip. Metal pillars penetrating the dielectric layer are formed in the dielectric layer. One end of the metal pillar is connected to the contact pad, and the other end is connected to the first redistribution layer or the second redistribution layer; the packaged chip includes contact pads, and a solder connection structure is formed on the packaged chip. The solder connection structure includes metal pillars and solder balls. One end of the metal pillar is connected to the contact pad, and the other end is connected to the solder ball, and the solder ball is further connected to the first redistribution layer or the second redistribution layer.

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