A method for reducing dark current and white pixels of CMOS image sensor

Abstract

The application provides a method for reducing dark current and white pixels of a CMOS image sensor, which comprises the following steps: forming a dielectric protective layer on the surface of a semiconductor substrate, etching the dielectric protective layer and the semiconductor substrate to form a groove in the semiconductor substrate; forming a liner layer on the inner surface of the groove; performing a preset number of dielectric layer filling and etching back processes; and etching back the gap on the top of the dielectric layer deposited in the groove to enlarge the gap and make the groove below the gap be filled with the remaining dielectric layer without gap. By performing the preset number of dielectric layer filling and etching back processes first and then depositing a covering layer to form the required STI structure, the number of cycles of the dielectric layer filling and etching back processes can be reduced, the etching back time in each cycle of the dielectric layer filling and etching back processes can be reduced, the method for reducing metal impurity pollution can be improved, and the product yield can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the CIS (CMOS Image sensor) manufacturing technical field, and particularly relates to a method for reducing dark current and white pixel of a CMOS image sensor. BACKGROUND

[0002] In the silicon wafer manufacturing, due to the requirements of high temperature resistance, corrosion resistance, hardness and the like, some metal-containing parts have to be used in the production equipment, and these parts will inevitably affect the metal impurity content of the silicon wafer itself in the silicon wafer process, but the most important defect of the wafer is often caused by the metal impurities. In the ideal production condition, when no light energy is absorbed, the dark current of the CIS (CMOS Image sensor) device is very small, but after being polluted by the metal impurities, since the metal ions carry charges, if the metal ions pass through the photodiode in the migration process, the dark current of the pixel will become large, and the main reason is that the energy level of the metal impurities is high, so the phenomenon of hot carrier recombination is easily caused. When the metal impurities are activated, the dark field current instantaneously becomes large, and thus the white pixel peak appears, as shown in Fig. (1a). The specific performance on the terminal electronic product is that when the photograph is taken, there will be a white point in the photograph, which is also called white pixel (WP), and this condition will greatly affect the imaging quality, as shown in Fig. (1b).

[0003] For example, the shallow trench isolation (STI) filling of the existing 55nm CIS (CMOS Image sensor) platform adopts the high density plasma chemical vapor deposition (HDP CVD) filling mode, and silicon dioxide is generated by the reaction of SiH4 and N2O in the plasma state, and the specific reaction equation is: SiH4+2N2O→SiO2+2H2+N2, and the reaction cavity structure is shown in Fig. (2a). When the silicon wafer works in the reaction cavity, since the reaction gas enters the reaction cavity from the top of the cavity, the metal pollution caused by the HDP CVD process causes the silicon wafer failure area to be in the shape of outward diffusion from the center, as shown in Fig. (2b).

[0004] In addition, the operation mode of the reaction chamber will also lead to the "ten-wafer effect" (the first wafer is the worst, then it gradually improves, and the last five wafers tend to be stable). This is strongly correlated with the rule of cleaning the chamber wall once every ten wafers in the reaction chamber, as shown in Figure (1c). Especially in the early stage of machine PM (preventive maintenance), the metal content in the chamber reaches its peak. During this period, the number of white pixel (WP) failures is the highest. However, as the number of wafers in subsequent operations increases, it will dilute the metal content in the chamber. At present, in order to ensure the yield, the CIS platform controls this process by increasing the number of wafers shipped for large pixel size and sensitive products. Generally, the number of wafers shipped is >1200pcs. For other products, under normal PM conditions, the shipment is 600 / 6+5 (600 wafers shipped with 6 control wafers + 5 product wafers) or 1200 / 1+10. Summary of the Invention

[0005] The purpose of this invention is to provide a method for reducing dark current and white pixels in CMOS image sensors, thereby solving the problem of metal impurity contamination.

[0006] To address the aforementioned technical problems, this invention provides a method for reducing dark current and white pixels in a CMOS image sensor, comprising the following steps:

[0007] A dielectric protective layer is formed on the surface of a semiconductor substrate, and the dielectric protective layer and the semiconductor substrate are etched to form a trench in the semiconductor substrate;

[0008] A liner layer is formed on the inner surface of the trench;

[0009] Perform a preset number of dielectric layer filling and back etching processes. Each round of the dielectric layer filling and back etching process includes: first, filling the trench with a dielectric layer using a high-density plasma chemical vapor deposition process; then, back etching the gap at the top of the dielectric layer deposited in the trench to increase the gap and make the trench below the gap filled with the remaining and gapless dielectric layer.

[0010] A capping layer is deposited on the trench and the medium layer to form a shallow trench isolation structure in the trench, and the deposition thickness of the capping layer is related to the depth of the trench and the preset number of rounds.

[0011] Preferably, the preset number of rounds is 2 to 6 rounds.

[0012] Preferably, each round of the process parameters of the medium layer filling and etching back process is the same, or at least one process parameter of at least two rounds of the medium layer filling and etching back process is different; the process parameters include process bias power, deposition time, and etching back time.

[0013] Preferably, the etching back rate is at least The medium deposition rate in the trench is at least

[0014] Preferably, the ratio of the thickness of the medium layer after etching back to the deposition thickness of the newly deposited medium layer before etching back is 0.15.

[0015] Preferably, the medium protection layer includes an isolation oxide layer and a nitride layer stacked on the semiconductor substrate; the material of the isolation oxide layer includes silicon oxide, and the material of the nitride layer includes silicon nitride.

[0016] Preferably, the cover layer and the medium layer are planarized by a chemical mechanical polishing process until the top surface of the medium protection layer is exposed to form a shallow trench isolation structure with a flat top surface.

[0017] Preferably, the total thickness of the cover layer and the medium layer filled in the trench is at least

[0018] Preferably, the material of the liner layer includes silicon oxide, and the material of the cover layer includes an oxide layer.

[0019] Preferably, after the cover layer and the medium layer are planarized, the medium protection layer is also removed.

[0020] The scheme of the present application, in the STI HDP filling process, a preset number of medium layer filling and etching back processes are first performed, and then a cover layer is deposited to form a required STI structure. Compared with the prior art, the number of cycles of the medium layer filling and etching back process can be reduced, the etching back time in each round of the medium filling and etching back process can be reduced, the method for reducing metal impurity pollution can be improved, the product yield can be improved, and finally the device performance can be improved, which can reduce the dark current of the pixel and the generation of WP.

[0021] Further, since the deposition thickness of the cover layer is related to the depth of the trench and the preset number of rounds, the deposition thickness of the cover layer can be reduced, the process time can be further reduced, the purpose of capacity expansion can be achieved, and in the case of large cargo volume, the product shipment and yield can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1ais a plot of pixel dark current versus white pixel;

[0023] Figure 1b is a white pixel schematic;

[0024] Figure 1c is a plot of white pixel versus die number;

[0025] Figure 2a is a HDP reaction chamber schematic;

[0026] Figure 2b is a wafer white pixel failure plot;

[0027] Figure 3 is a flow chart of one embodiment of the present invention;

[0028] Figure 4 is a device cross-sectional structure schematic of one embodiment of the present invention;

[0029] Figure 5 is a device cross-sectional structure schematic of one embodiment of the present invention;

[0030] Figures 6a-6b is a device cross-sectional structure schematic of one embodiment of the present invention during a first round of cycles;

[0031] Figures 7a-7b is a device cross-sectional structure schematic of one embodiment of the present invention during a second round of cycles;

[0032] Figure 8 is a device cross-sectional structure schematic of one embodiment of the present invention after a cap layer formation process;

[0033] Figure 9 is a device cross-sectional structure schematic of one embodiment of the present invention after chemical mechanical polishing;

[0034] Figure 10 is a device cross-sectional structure schematic of one embodiment of the present invention after nitride removal;

[0035] Figure 11 is a data table for two NMOS transistors on a wafer for a first round of experiments;

[0036] Figure 12 is a data table for two NMOS transistors on a wafer for a second round of experiments;

[0037] Figure 13a is the total thickness of the cap layer and the dielectric layer for Pre-CMP total thickness under the condition that the thickness of the cap layer is 1000 A;

[0038] Figure 13bThe total thickness of the capping layer and dielectric layer is Total thickness of Post CMP under certain conditions;

[0039] Figure 14a The total thickness of the capping layer and dielectric layer is The total thickness before oxidation under the specified conditions;

[0040] Figure 14b The total thicknesses of the capping layer and the dielectric layer are respectively Total thickness distribution under Post CMP conditions;

[0041] Figure 15a The total thickness of the capping layer and dielectric layer is Nitride thickness under the given conditions;

[0042] Figure 15b The total thickness of the capping layer and dielectric layer is Nitride thickness under certain conditions.

[0043] The numbers in the diagram are as follows:

[0044] 1. Padding layer; 2. Isolation oxide layer; 3. Nitrided layer; 4. Dielectric layer; 5. Covering layer. Detailed Implementation

[0045] The method for reducing dark current and white pixels in CMOS image sensors proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0046] The inventors discovered that, taking a product manufactured on the CIS platform as an example, the required trench depth for the STI process is [insert depth here]. Not only is the groove depth greater than that of typical BSI (Back-side-illumination) products (e.g., The film layer deposited on the periphery of the trenches due to the HDP process is shallow, and it typically needs to be removed by a CMP process (i.e., STI CMP process), with a removal thickness generally being [thickness value missing]. Therefore, the difference in film thickness (bias) between the product before (Pre-STI CMP) and after (Post-STI CMP) the STI CMP process is: Moreover, etching step is the largest metal source in HDP filling process, if the cycle number is reduced, the metal can be effectively reduced, thus the capacity expansion can be achieved by reducing the number of etching cycles in HDP and the final thickness.

[0047] As shown in Table 1, the current product adopts 6 cycles of HDP process, wherein the processes of cycles 1-5 are the same, the power during deposition and etching is the same, the sixth cycle is only longer than the previous five cycles, and the operation power parameters in each cycle are shown in the following table.

[0048]

[0049] Table 1: Cycle parameters of current technology

[0050] Based on this, the core idea of the present application is that in the STI HDP filling process, a predetermined number of medium layer filling and back etching processes are first performed, and then a cover layer is deposited to form the required STI structure. Compared with the prior art, the number of cycles of medium layer filling and back etching processes can be reduced, and the back etching time in each cycle of medium filling and back etching process can be reduced, thereby reducing metal impurity pollution, improving product yield, and ultimately reflecting on device performance, reducing dark current and white pixel of pixels.

[0051] Please refer to Figures 3-10 , which is a schematic diagram of an embodiment of the present application. As shown in Figure 3 , an embodiment of the present application provides a method for reducing dark current and white pixel of CMOS image sensor, which comprises sequentially performing the following steps:

[0052] S1, forming a medium protection layer on the surface of a semiconductor substrate (not labeled), and etching the medium protection layer and the semiconductor substrate to form a trench in the semiconductor substrate, wherein the medium protection layer comprises a separation oxide 2 and a nitride layer 3 stacked on the semiconductor substrate, wherein the material of the separation oxide 2 comprises silicon oxide, and the material of the nitride layer 3 comprises silicon nitride.

[0053] S2, forming a liner layer 1 on the inner surface of the trench, wherein the material of the liner layer 1 comprises silicon oxide.

[0054] S3, performing a preset number of cycles of the medium layer 4 filling and etching back process, each cycle of the medium layer 4 filling and etching back process including: first, filling the trench with the medium layer 4 by a high-density plasma chemical vapor deposition process, wherein, due to the effect of the trench, the top of the medium layer 4 formed by the deposition process will form a recess (i.e. gap) in the central axis region of the trench; and then, etching back the gap in the top of the medium layer 4 deposited in the trench to increase the gap and cause the trench below the gap to be filled with the remaining medium layer 4 without a gap, and the total thickness of the medium layer 4 and the cap layer 5 filled in the trench is at least The etching back rate is at least The medium deposition rate in the trench is at least The ratio of the thickness of the medium layer 4 etched back to the deposition thickness of the newly deposited medium layer 4 before etching back is 0.15.

[0055] The preset number of cycles is 2-6, each cycle of the medium layer 4 filling and etching back process has the same process parameters, or at least one process parameter of at least two cycles of the medium layer 4 filling and etching back process is different; the process parameters include process bias power, deposition time, and etching back time.

[0056] S4, after completing the last cycle of the preset number of cycles of the medium layer 4 filling and etching back process, depositing a cap layer 5 on the trench and the medium layer 4, at this time, the cap layer 5 fills the opening in the top of the medium layer 4 and is generally higher than the top of the trench, and more importantly, the deposition thickness of the cap layer 5 is related to the depth of the trench and the preset number of cycles, at this time, the deposition thickness of the cap layer 5 is appropriate, not too thin to cause the trench not to be filled, nor too thick to cause the subsequent CMP process to be too long. The material of the cap layer 5 includes an oxide layer.

[0057] S5, planarizing the cap layer 5 and the medium layer 4 by a chemical mechanical polishing (CMP) process until the top surface of the nitride layer 3 and the isolation oxide 2 in the medium protection layer is exposed to form a shallow trench isolation structure with a flat top surface. Further, after planarizing the cap layer 5 and the medium layer 4, the nitride layer 5 of the medium protection layer can also be removed by an etching process, or both the nitride layer 3 and the isolation oxide 2 can be removed.

[0058] It is to be noted that the preset number of times of the medium layer 4 filling and etching back process in step S3 is related to the depth of the trench formed in the semiconductor substrate, and therefore, the correlation between the preset number of times of the medium layer 4 filling and etching back process and the depth of the trench formed in the semiconductor substrate can be obtained by analyzing historical data at any suitable step node before step S3, and then the depth of the trench to be formed in the present application or the actual depth of the trench formed in step S1 is substituted into the correlation to determine the preset number of times of the medium layer 4 filling and etching back process required in step S3 of the present application.

[0059] In addition, the deposition thickness of the cover layer 5 in step S4 is related to the preset number of times of the medium layer 4 filling and etching back process in step S3 and the depth of the trench formed in the semiconductor substrate in step S1, and the remaining depth of the trench after the medium layer 4 is filled can be obtained by measuring after the preset number of times of the medium layer 4 filling and etching back process is completed (i.e. after step S3 is completed), and then the deposition process parameters of the cover layer 5 in step S4 are determined according to the remaining depth, so that the final deposition thickness of the cover layer 5 is sufficient to fill the trench and ensure that the top height of the formed STI structure meets the requirements. Alternatively, the correlation between the preset number of times of the medium layer 4 filling and etching back process and the deposition thickness of the cover layer 5 can be obtained in advance by historical data at any suitable step node before step S4 is performed, and then the deposition process parameters of the cover layer 5 in step S4 are determined according to the correlation, so that the final deposition thickness of the cover layer 5 is sufficient to fill the trench and ensure that the top height of the formed STI structure meets the requirements.

[0060] The scheme of the present application can advantageously reduce the deposition thickness of the cover layer 5 and the overall process time, thereby achieving the purpose of increasing the production capacity.

[0061] In an example, as shown in Figures 6a-6b and Figures 7a-7b , the cycle is performed for 2 rounds, in the first round, the trench is filled with the medium layer 4, as shown in Figure 6a , and then the medium layer 4 after deposition is etched back to open the gap on the top of the medium layer 4, as shown in Figure 6b , and then the trench is filled with a new medium layer 4, as shown in Figure 7a , and then the medium layer 4 is etched back again to reopen the gap, and finally, the cover layer 5 is deposited on the opened gap to completely fill the trench.

[0062] As shown in Table 2, two cycles of experiments were performed on the wafer, and in the first experiment (i.e. Test 1 in Table 2), the medium layer deposition + etching back process was performed for 2 rounds, although no premature sealing of the trench was found, but the trench was not completely filled, and the corresponding test values are shown in Figure 11Therefore, it can be concluded that the phenomenon of the trench being prematurely sealed by the dielectric layer 4 and the appearance of a hollow can be avoided by two rounds of dielectric layer deposition + etching back process, which meets the current process requirements. The relevant experimental values are shown in Table 3.

[0063]

[0064] Table 2: Two-cycle experiment

[0065] Therefore, the process parameters are fine-tuned for the second experiment (i.e., Test 2 in Table 2), and the corresponding test values after two rounds of dielectric deposition + etching back process are shown in Table 3. Figure 12 It can be concluded that two rounds of dielectric layer deposition + etching back process can completely fill the trench without a hollow. Under the condition of two rounds of dielectric layer deposition + etching back process, the etching time is as low as 5 min, which can effectively reduce metal impurities, thereby reducing the white pixels of the CIS device. In the second experiment, the ratio of the etching thickness to the deposition thickness of the dielectric layer 4 can reach 0.15, which reduces the ratio of the etching thickness to the deposition thickness and is beneficial to reducing the risk of metal contamination.

[0066]

[0067] Table 3: Experimental data of Test 1 and Test 2

[0068] In another example, the process parameters of each round of dielectric layer deposition + etching back process are the same or different, and the process parameters of the dielectric layer deposition + etching back process of the next round can be adjusted according to the filling rate, filling time of the dielectric, and etching rate, etching time of the previous round of trench filling.

[0069] In actual production, two rounds of dielectric layer deposition + etching back process can reduce the total process time and improve productivity. To further improve productivity, the total thickness of the cover layer 5 and the dielectric layer 4 is reduced, and the next two experiments (i.e., Test 3 and Test 4 in Table 2) are performed. The total thickness of the cover layer 5 and the dielectric layer 4 in Test 3 and Test 4 is and

[0070] Figure 13a The total thickness of the cover layer 5 and the dielectric layer 4 is The total thickness of the cover layer 5 and the dielectric layer 4 is Figure 13b The total thickness of the cover layer 5 and the dielectric layer 4 is The total thickness of the cover layer 5 and the dielectric layer 4 is Figure 13a and Figure 13bFull Pre Ox1 is the total thickness before the first oxidation (the total thickness of the dielectric layer 4 and the cap layer 5 deposited in the channel), Full Pre Ox2 is the total thickness before the second oxidation, Pre Oxide BSL (BSL, Baseline, current platform production condition) is the total thickness before oxidation under the BSL process condition; Full Post Ox1 is the total thickness after the first oxidation, Full Post Ox2 is the total thickness after the second oxidation, Pre Oxide BSL (BSL, Baseline, current platform production condition) is the total thickness after oxidation under the BSL process condition.

[0071] Figure 14a The total thickness of the cap layer 5 and the dielectric layer 4 is The total thickness before oxidation under the condition, Figure 14b The total thickness after Post CMP (after chemical mechanical polishing) is Figure 13b And Figure 14b It can be concluded that the total thickness after Post CMP (after chemical mechanical polishing) is Under the condition and Under the condition, the distribution of various values tends to be the same, wherein, in Figure 14a Cost Pre Ox1 and Cost Pre Ox2 are the thickness consumed before the first oxidation and the thickness consumed before the second oxidation, respectively, in Figure 14b Cost Post Ox1 and Cost Post Ox2 are the thickness consumed after the first oxidation and the thickness consumed after the second oxidation, respectively, and Post Oxide BSL is the total thickness after oxidation under the BSL process condition.

[0072] Wherein, in Figure 15a Full PostNit1 and Full PostNit2 are the thickness after the first nitridation (the thickness of nitride) and the thickness after the second nitridation (the thickness of nitride), respectively, and PostNitirde BSL is the total thickness of nitride after nitridation under the BSL process condition; in Figure 15b Cost PostNit1 and Cost Post Nit2 are the thickness after the first nitridation (the thickness of nitride) and the thickness after the second nitridation (the thickness of nitride), respectively, and Post Nitirde BSL is the thickness of nitride after nitridation under the BSL process condition.

[0073] Further, the nitride content of the wafer in Test 3 and Test 4 experiments is compared, as Figure 15a And Figure 15b The total thickness of the cap layer 5 and the dielectric layer 4 is and The nitride content under the condition can be obviously seen from the figure that the value distribution of both converges, thus the purpose of further improving yield can be achieved by reducing the total thickness of the cover layer 5 and the medium layer 4.

[0074] As can be seen from the above, in the method for reducing dark current and white pixels of the CMOS image sensor provided by the embodiment of the present application, the processes of medium layer filling and back etching for a preset number of rounds are performed first, and then the cover layer is deposited to form the required STI structure, which can reduce the cycle number of the processes of medium layer filling and back etching, and can be beneficial to reduce the back etching time in each round of medium layer filling and back etching processes, and thus can reduce the method of metal impurity pollution.

[0075] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for reducing dark current and white pixels in a CMOS image sensor, characterized in that, Includes the following steps: A dielectric protective layer is formed on the surface of a semiconductor substrate, and the dielectric protective layer and the semiconductor substrate are etched to form a trench in the semiconductor substrate; A liner layer (1) is formed on the inner surface of the trench. The correlation between the preset number of rounds of the filling and back etching process of the dielectric layer (4) and the trench depth formed in the semiconductor substrate is calculated, and the trench depth is substituted into the correlation relationship to obtain the preset number of rounds of the filling and back etching process of the dielectric layer (4). Perform a preset number of rounds of dielectric layer (4) filling and back etching process. Each round of dielectric layer (4) filling and back etching process includes: first, filling the trench with dielectric layer (4) by high density plasma chemical vapor deposition process; then, back etching the gap at the top of the dielectric layer (4) deposited in the trench to increase the gap and make the trench below the gap filled with the remaining and gapless dielectric layer (4); A capping layer (5) is deposited on the trench and the medium layer (4) to form a shallow trench isolation structure in the trench, and the deposition thickness of the capping layer (5) is related to the depth of the trench and the preset number of rounds; The ratio of the thickness of the etched dielectric layer (4) to the deposition thickness of the newly deposited dielectric layer (4) before the etch is 0.

15.

2. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, The preset number of rounds is 2 to 6 rounds.

3. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, The process parameters of the dielectric layer (4) filling and back etching process are the same in each round, or at least one process parameter of the dielectric layer (4) filling and back etching process is different in at least two rounds. The process parameters include process bias power, deposition time, and etch-back time.

4. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, The etching rate is at least 26.7 Å / min, and the dielectric deposition rate in the trench is at least 32.5 Å / min.

5. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, The dielectric protective layer includes an isolation oxide (2) and a nitride layer (3) stacked on the semiconductor substrate; the isolation oxide (2) is made of silicon oxide, and the nitride layer (3) is made of silicon nitride.

6. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, Also includes: The capping layer (5) and the dielectric layer (4) are planarized by chemical mechanical polishing until the top surface of the dielectric protective layer is exposed, so as to form a shallow trench isolation structure with a flat top surface.

7. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, The total thickness of the cover layer (5) and the dielectric layer (4) filling the trench is at least 3500 Å.

8. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 1, characterized in that, The material of the padding layer (1) includes silicon oxide; the material of the cover layer (5) includes an oxide layer.

9. The method for reducing dark current and white pixels in a CMOS image sensor as described in claim 6, characterized in that, After planarizing the cover layer (5) and the dielectric layer (4), the dielectric protective layer is also removed.

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