High Electron Mobility Transistor and Method of Fabricating the Same

Abstract

A high electron mobility transistor, wherein a semiconductor channel layer and a semiconductor barrier layer are disposed on a substrate. A patterned semiconductor protection layer is disposed on the semiconductor barrier layer, and a patterned semiconductor cap layer is disposed between the patterned semiconductor protection layer and the semiconductor barrier layer. An interlayer dielectric layer covers the patterned semiconductor cap layer and the patterned semiconductor protection layer, and the interlayer dielectric layer includes a gate contact hole. A gate electrode is disposed in the gate contact hole and electrically connected to the patterned semiconductor cap layer, wherein a patterned semiconductor protection layer exists between the gate electrode and the patterned semiconductor cap layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor cap layer and the resistivity of the interlayer dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of transistors, and particularly to a high electron mobility transistor and a manufacturing method thereof. Background Art

[0002] In semiconductor technology, III-V semiconductor compounds can be used to form various integrated circuit devices, such as high-power field effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a type of transistor having a two-dimensional electron gas (2DEG), and the 2DEG is adjacent to the junction surface (i.e., hetero-junction surface) between two materials with different energy gaps. Since a HEMT does not use a doped region as the carrier channel of the transistor, but uses a 2DEG as the carrier channel of the transistor, compared with the existing metal-oxide-semiconductor field effect transistor (MOSFET), a HEMT has various attractive characteristics, such as a high electron mobility and the ability to transmit signals at a high frequency. For an existing HEMT, it may include a compound semiconductor channel layer, a compound semiconductor barrier layer, a P-type compound semiconductor cap layer, a metal cap layer, and a gate electrode stacked in sequence. By applying a bias voltage to the P-type compound semiconductor cap layer using the gate electrode, the concentration of the two-dimensional electron gas in the compound semiconductor channel layer located below the P-type compound semiconductor cap layer can be adjusted, thereby adjusting the switching of the HEMT.

[0003] For the metal cap layer disposed between the P-type compound semiconductor cap layer and the gate electrode, the step of manufacturing this metal cap layer usually includes a wet side etching process. However, since the etching degree of the side etching process is difficult to be precisely controlled, the metal cap layers of the HEMTs have different widths, thereby reducing the consistency of the electrical performance of the HEMTs. Summary of the Invention

[0004] In view of this, it is necessary to provide an improved high electron mobility transistor to improve the defects existing in the existing high electron mobility transistor.

[0005] According to an embodiment of the present invention, a high electron mobility transistor is provided, including a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor protection layer, a patterned semiconductor capping layer, an interlayer dielectric layer, and a gate electrode. The semiconductor channel layer and the semiconductor barrier layer are disposed on a substrate. The patterned semiconductor protection layer is disposed on the semiconductor barrier layer, and the patterned semiconductor capping layer is disposed between the patterned semiconductor protection layer and the semiconductor barrier layer. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and the interlayer dielectric layer includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically connected to the patterned semiconductor capping layer, wherein there is a patterned semiconductor protection layer between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

[0006] According to another embodiment of the present invention, a method for manufacturing a high electron mobility transistor is provided, including: providing a substrate, on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor capping layer, and a semiconductor protection layer are sequentially disposed; etching the semiconductor capping layer and the semiconductor protection layer to form a patterned semiconductor capping layer and a patterned semiconductor protection layer; forming an interlayer dielectric layer to cover the patterned semiconductor capping layer and the patterned semiconductor protection layer; forming a gate contact hole in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protection layer and is separated from the patterned semiconductor capping layer; and forming a gate electrode in the gate contact hole, wherein there is a part of the patterned semiconductor protection layer between the gate electrode and the patterned semiconductor capping layer, wherein the resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

[0007] According to the embodiment of the present invention, since the resistivity of the patterned semiconductor protection layer is higher than the resistivity of the upper gate electrode, even if the side surface of the patterned semiconductor protection layer is not subjected to lateral etching, the side surface of the patterned semiconductor protection layer is not likely to generate tip discharge, thereby avoiding unnecessary gate leakage current. Furthermore, since when forming the gate contact hole, the bottom surface of the gate contact hole does not penetrate the patterned semiconductor protection layer, the etching agent can be prevented from contacting the patterned semiconductor capping layer, and the original electrical characteristics of the patterned semiconductor capping layer can be maintained. Description of the Drawings

[0008] In order to make the following text easier to understand, the drawings and their detailed descriptions can be referred to simultaneously when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail, and the working principles of the specific embodiments of the present invention are expounded. In addition, for clarity, the features in the drawings may not be drawn according to the actual proportions, so the sizes of some features in some drawings may be deliberately enlarged or reduced.

[0009] Figure 1 It is a schematic cross-sectional view of a high electron mobility transistor (HEMT) shown according to an embodiment of the present invention.

[0010] Figure 2 It is an enlarged schematic cross-sectional view of a partial region of a high electron mobility transistor shown according to an embodiment of the present invention.

[0011] Figure 3 It is an enlarged schematic cross-sectional view of a partial region of a high electron mobility transistor shown according to a variant embodiment of the present invention.

[0012] Figure 4 It is a schematic cross-sectional view of a high electron mobility transistor shown according to a variant embodiment of the present invention.

[0013] Figure 5 It is a schematic cross-sectional view of manufacturing a high electron mobility transistor shown according to an embodiment of the present invention, which includes semiconductor layers stacked in sequence.

[0014] Figure 6 It is a schematic cross-sectional view of manufacturing a high electron mobility transistor shown according to an embodiment of the present invention, which includes a patterned semiconductor capping layer, a patterned semiconductor protection layer, and a shielding layer.

[0015] Figure 7 It is a schematic cross-sectional view of manufacturing a high electron mobility transistor shown according to an embodiment of the present invention, which includes a gate contact hole disposed in an interlayer dielectric layer.

[0016] Figure 8 It is a schematic cross-sectional view of manufacturing a high electron mobility transistor shown according to an embodiment of the present invention, which includes a gate electrode.

[0017] Figure 9 It is a schematic cross-sectional view of manufacturing a high electron mobility transistor shown according to an embodiment of the present invention, which includes a source / drain contact hole disposed in an interlayer dielectric layer.

[0018] Figure 10 It is a flowchart of manufacturing a high electron mobility transistor according to an embodiment of the present invention.

[0019] Among them, the reference numerals are explained as follows:

[0020] 10-1... High electron mobility transistor

[0021] 10-2... High electron mobility transistor

[0022] 10-3... High electron mobility transistor

[0023] 20... Semiconductor structure

[0024] 102… Substrate

[0025] 104… Buffer layer

[0026] 106… Semiconductor channel layer

[0027] 106a… Two-dimensional electron gas region

[0028] 106b… Two-dimensional electron gas truncation region

[0029] 108… Semiconductor barrier layer

[0030] 109… Semiconductor capping layer

[0031] 110… Patterned semiconductor capping layer

[0032] 111… Semiconductor protective layer

[0033] 110S… Side

[0034] 110T… Top

[0035] 120… Patterned semiconductor protective layer

[0036] 120B… Bottom

[0037] 120S… Side

[0038] 122… First part

[0039] 124… Second part

[0040] 124T… Top

[0041] 126… Groove

[0042] 126B… Bottom

[0043] 126S… Side

[0044] 128… Shielding layer

[0045] 130… Interlayer dielectric layer

[0046] 132… Gate contact hole

[0047] 134… Opening

[0048] 140… Gate electrode

[0049] 140C… Bottom corner

[0050] 142… First conductive layer

[0051] 144… Second conductive layer

[0052] 150… Interlayer dielectric layer

[0053] 152…Source / drain contact hole

[0054] 152B…Bottom surface

[0055] 154…Source / drain electrode

[0056] 156…Source / drain electrode

[0057] 160…Passivation layer

[0058] 200…Method

[0059] 202…Step

[0060] 204…Step

[0061] 206…Step

[0062] 208…Step

[0063] 210…Step

[0064] A…Region

[0065] D1…Width

[0066] D2…Width

[0067] D3…Width

[0068] D4…Width

[0069] T1…Thickness

[0070] T2…Thickness Detailed implementation manners

[0071] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity in description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description of "the first feature is formed on or above the second feature" hereinafter may mean that "the first feature is in direct contact with the second feature", or it may mean that "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present invention may use repeated reference symbols and / or literal notations. The use of these repeated reference symbols and notations is for the purpose of making the description more concise and clear, rather than indicating the relevance between different embodiments and / or configurations.

[0072] In addition, with regard to the spatial-related narrative terms mentioned in the present invention, such as: "under", "low", "below", "above", "on", "beneath", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or more) element or feature in the drawings. In addition to the orientation shown in the drawings, these spatial-related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotating 90 degrees or other orientations), the spatial-related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0073] Although the present invention uses terms such as first, second, third, etc. to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not imply or represent any previous ordinal number of the element itself, nor the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to by the term of the second element, component, region, layer, or section.

[0074] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "about" or "substantially", the meaning of "about" or "substantially" may still be implied.

[0075] In the present invention, a "group III-V semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. Among them, the group III element can be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element can be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, the "III-V semiconductor" can include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), its analogs, or combinations of the above compounds, but not limited thereto. In addition, according to requirements, dopants can also be included in the III-V semiconductor, and it is a III-V semiconductor with a specific conductivity type, such as an N-type or P-type III-V semiconductor.

[0076] Although the present invention is described below through specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and these omitted details belong to the knowledge scope of ordinary technical personnel in the technical field.

[0077] The present invention relates to a high electron mobility transistor (HEMT), which can be used as a power switching transistor for voltage converter applications. Compared with silicon power transistors, due to the wider bandgap of III-V HEMTs, they have the characteristics of low on-state resistance and low switching loss.

[0078] Figure 1 is a cross-sectional schematic diagram of a high electron mobility transistor (HEMT) shown according to an embodiment of the present invention. As Figure 1As shown, according to an embodiment of the present invention, a high electron mobility transistor 10-1, such as an enhancement-mode high electron mobility transistor, is disposed on a substrate 102, and a semiconductor channel layer 106, a semiconductor barrier layer 108, a patterned semiconductor capping layer 110, a patterned semiconductor protection layer 120, and an interlayer dielectric layer 130 may be sequentially disposed on the substrate 102, and a gate electrode 140 may be disposed in the interlayer dielectric layer 130. Among them, the resistivity of the patterned semiconductor protection layer 120 is between the resistivity of the patterned semiconductor capping layer 110 and the resistivity of the interlayer dielectric layer 130. According to an embodiment of the present invention, the interlayer dielectric layer 130 may cover the patterned semiconductor capping layer 110 and the patterned semiconductor protection layer 120, and a gate contact hole 132 is disposed in the interlayer dielectric layer 130 for accommodating the gate electrode 140. There is a part of the patterned semiconductor protection layer 120 between the gate electrode 140 and the patterned semiconductor capping layer 110.

[0079] According to an embodiment of the present invention, a selective buffer layer 104 may be disposed between the substrate 102 and the semiconductor channel layer 106. An interlayer dielectric layer 150 may be selectively disposed above the interlayer dielectric layer 130. At least two source / drain contact holes 152 may penetrate through the interlayer dielectric layers 130 and 150 respectively for accommodating at least two source / drain electrodes 154 and 156.

[0080] According to an embodiment of the present invention, the above-mentioned substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, but is not limited thereto. In another embodiment, the substrate 102 further includes a single or multiple layers of insulating material layers and / or other suitable material layers (such as semiconductor layers) and a core layer. The insulating material layer may be an oxide, a nitride, a nitrogen oxide, or other suitable insulating materials. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), zinc oxide (ZnO), or gallium oxide (Ga2O3), or other suitable ceramic materials. In one embodiment, the single or multiple layers of insulating material layers and / or other suitable material layers cover the core layer.

[0081] The buffer layer 104 can be used to reduce the degree of stress or lattice mismatch existing between the substrate 102 and the semiconductor channel layer 106. According to an embodiment of the present invention, the buffer layer 104 can include a plurality of sub-semiconductors, and its overall resistance value will be higher than that of other layers on the substrate 102. Specifically, the proportion of some elements in the buffer layer 104, such as metal elements, will gradually change from the substrate 102 towards the semiconductor channel layer 106. For example, for the case where the substrate 102 and the semiconductor channel layer 106 are a silicon substrate and an i-GaN layer (intrinsic GaN layer) respectively, the buffer layer 104 can be aluminum gallium nitride (Al x Ga (1-x) N) with a gradually changing composition ratio, and along the direction from the substrate 102 towards the semiconductor channel layer 106, the X value will decrease from 0.9 to 0.15 in a continuous or stepwise manner.

[0082] The above semiconductor channel layer 106 can include one or more III-V semiconductor layers. The composition of the III-V semiconductor layer can be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. In addition, the semiconductor channel layer 106 can also be one or more doped III-V semiconductor layers, such as a P-type III-V semiconductor layer. For a P-type III-V semiconductor layer, its dopant can be C, Fe, Mg, or Zn, or is not limited thereto. The above semiconductor barrier layer 108 can include one or more III-V semiconductor layers, and its composition will be different from that of the III-V semiconductor layer of the semiconductor channel layer 106. For example, the semiconductor barrier layer 108 can include AlN, Al y Ga (1-y) N (0 < y < 1) or a combination thereof. According to an embodiment, the semiconductor channel layer 106 can be an undoped GaN layer, and the semiconductor barrier layer 108 can be an essentially N-type AlGaN layer. Due to the discontinuous energy gap between the semiconductor channel layer 106 and the semiconductor barrier layer 108, by stacking the semiconductor channel layer 106 and the semiconductor barrier layer 108 on top of each other, electrons will be accumulated at the heterointerface between the semiconductor channel layer 106 and the semiconductor barrier layer 108 due to the piezoelectric effect, thus generating a thin layer with high electron mobility, that is, a two-dimensional electron gas (2DEG) region 106a. In contrast, for the region covered by the patterned semiconductor cap layer 110, since a two-dimensional electron gas will not be formed, it can be regarded as a two-dimensional electron gas truncated region 106b.

[0083] The patterned semiconductor cap layer 110 disposed above the semiconductor barrier layer 108 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layer may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. The patterned semiconductor cap layer 110 may be one or more doped III-V semiconductor layers, for example, a P-type III-V semiconductor layer. For a P-type III-V semiconductor layer, the dopant may be C, Fe, Mg, or Zn, but is not limited thereto. According to an embodiment of the present invention, the patterned semiconductor cap layer 110 may be a P-type GaN layer.

[0084] The patterned semiconductor protection layer 120 may substantially completely cover the underlying patterned semiconductor cap layer 110, such that its sides may be flush with the underlying patterned semiconductor cap layer 110, or slightly retracted or protruded (the length of the retraction or protrusion of each side may be 1-10 nm, but is not limited thereto). The composition of the patterned semiconductor protection layer 120 is a semiconductor different from that of the patterned semiconductor cap layer 110. According to an embodiment of the present invention, the composition of the patterned semiconductor protection layer 120 may include a silicon-containing semiconductor, such as silicon, silicon carbide, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, metal silicide, or a combination of the foregoing, and the crystalline state of the patterned semiconductor protection layer 120 may be single crystalline, polycrystalline, or amorphous. For example, the patterned semiconductor protection layer 120 may be low temperature polysilicon. The resistivity of the patterned semiconductor protection layer 120 may be higher than that of the underlying patterned semiconductor cap layer 110, for example, 10 to 1000 Ω·m, and its longitudinal resistance may be 1x10 4 to 1x10 6 Ω, for example, 1x10 4 Ω, 1x10 5 Ω, or 1x10 6 Ω, but is not limited thereto.

[0085] The gate electrode 140 can be electrically connected to the underlying patterned semiconductor capping layer 110 by a Schottky contact, and the bottom of the gate electrode 140 can be embedded in the patterned semiconductor protection layer 120, but is still longitudinally separated from the underlying patterned semiconductor capping layer 110. Thus, the patterned semiconductor protection layer 120 can include a first portion 122 at the periphery and a second portion 124 in the middle. According to an embodiment of the present invention, the gate electrode 140 can be a single-layer or multi-layer structure, for example, a double-layer structure including a first conductive layer 142 and a second conductive layer 144. Among them, the first conductive layer 142 can directly contact the patterned semiconductor protection layer 120, and its composition includes Schottky contact metal. Among them, the Schottky contact metal refers to a metal, alloy or its stacked layer that can form a Schottky contact with a semiconductor layer, such as TiN, W, Pt, Ni or Ni, but is not limited thereto. The composition of the second conductive layer 144 can include Ti, Al, Au, Mo, but is not limited thereto. According to an embodiment of the present invention, the first conductive layer 142 can include a metal nitride containing a refractory metal, and the refractory metal can be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, technetium, rhenium, ruthenium, osmium, rhodium and iridium.

[0086] The interlayer dielectric layers 130, 150 can be sequentially disposed on the semiconductor barrier layer 108, and their materials can be independently selected from Si3N4, AlN, Al2O3, SiO2, or a combination of the foregoing, but are not limited thereto. The interlayer dielectric layers 130, 150 can cover the patterned semiconductor protection layer 120, the patterned semiconductor capping layer 110, the semiconductor barrier layer 108, and the semiconductor channel layer 106. Among them, the resistivity of the interlayer dielectric layers 130, 150 can be higher than the resistivity of the patterned semiconductor protection layer 120. For example, the resistivity of the interlayer dielectric layers 130, 150 can be 1x10 10 to 1x10 16 Ω·m, such as 1x10 13 Ω·m, but is not limited thereto.

[0087] The source / drain electrodes 154, 156 can each penetrate the interlayer dielectric layers 130, 150 and be electrically connected to the underlying semiconductor barrier layer 108 and semiconductor channel layer 106. According to an embodiment of the present invention, the gate electrode 140 can be a single-layer or multi-layer structure, and its composition can include ohmic contact metal. Among them, the ohmic contact metal refers to a metal, alloy or its stacked layer that can form an ohmic contact with a semiconductor layer, such as Ti, Ti / Al, Ti / Al / Ti / TiN, Ti / Al / Ti / Au, Ti / Al / Ni / Au or Ti / Al / Mo / Au, but is not limited thereto.

[0088] Figure 2 is an enlarged cross-sectional schematic view of a local area of a high electron mobility transistor according to an embodiment of the present invention, which can correspond to Figure 1 the area A shown in the embodiment. As Figure 2 shown, the bottom surface 120B of the patterned semiconductor protection layer 120 can coincide with the top surface 110T of the patterned semiconductor cover layer 110. And the side surface 120S of the patterned semiconductor protection layer 120 can be substantially flush with the side surface 110S of the patterned semiconductor cover layer 110, so that the lateral dimensions of the patterned semiconductor protection layer 120 and the patterned semiconductor cover layer 110, such as the width D2, can be substantially equal to each other. According to an embodiment of the present invention, a groove 126 can be provided on the surface of the patterned semiconductor protection layer 120, so that the bottom surface 126B and the side surface 126S of the groove 126 can coincide with the surface of the patterned semiconductor protection layer 120. The lateral dimension of the groove 126, such as the width D1, can be smaller than the width D2 of the patterned semiconductor cover layer 110, so that the first part 122 of the patterned semiconductor protection layer 120 can be adjacent to the periphery of the groove 126, and the second part 124 of the patterned semiconductor protection layer 120 can be disposed directly below the groove 126. Among them, the lateral dimensions of each first part 122 located around the groove 126, such as the width, can be the widths D3 and D4 respectively. For example, the widths D3 and D4 can be 20 to 350 nm, and the widths D3 and D4 can be the same or different from each other, but are not limited thereto. In addition, the thickness T1 of the first part 122 can be greater than the thickness T2 of the second part 124. For example, the thickness T2 can be 10 to 100 nm, but is not limited thereto. The lower part of the gate electrode 140 can fill the groove 126 and have a width D1, and at least one bottom corner 140C of the gate electrode 140 can directly contact the patterned semiconductor protection layer 120, or can be further covered by the patterned semiconductor protection layer 120.

[0089] According to an embodiment of the present invention, since the resistivity of the patterned semiconductor protection layer 120 is higher than that of the upper gate electrode 140, even if the side surface 120S of the patterned semiconductor protection layer 120 is not subjected to lateral etching, the patterned semiconductor protection layer 120 will not generate corona discharge, so unnecessary gate leakage current can be avoided. Furthermore, since the width D2 of the patterned semiconductor protection layer 120 can be substantially the same as the width D2 of the patterned cover layer, even for semiconductor elements produced in different batches, good electrical consistency can still be maintained among the semiconductor elements. In addition, since the bottom corner 140C of the gate electrode 140 can be covered by the patterned semiconductor protection layer 120 with a relatively high resistivity, the patterned semiconductor protection layer 120 can be used to buffer the high-voltage electric field from the bottom corner 140C of the gate electrode 140, so the stability of the semiconductor element can be improved.

[0090] Figure 3 It is an enlarged cross-sectional schematic diagram of a partial region of a high electron mobility transistor according to a variant embodiment of the present invention. Figure 3 The high electron mobility transistor 10-2 shown in the embodiment is substantially the same as Figure 2 the high electron mobility transistor 10-1 shown in the embodiment. The main difference between the two is that the bottom surface of the gate electrode 140 of the high electron mobility transistor 10-2 is not buried in the patterned semiconductor protection layer 120. Therefore, for the thickness T1 of the patterned semiconductor layer 120, whether it is around or directly below the gate electrode 140, the thickness T1 of the patterned semiconductor layer 120 can be maintained fixed. In addition, since the distance between the gate electrode 140 and the patterned semiconductor cover layer 110 is equal to the thickness T1 of the patterned semiconductor layer 120, in order to avoid an excessive resistance value between the gate electrode 140 and the patterned semiconductor cover layer 110, the thickness T1 of the patterned semiconductor layer 120 can be 10 to 100 nm.

[0091] Figure 4 It is a cross-sectional schematic diagram of a high electron mobility transistor according to a variant embodiment of the present invention. Figure 4 The high electron mobility transistor 10-3 shown in the embodiment is substantially the same as Figure 1 the high electron mobility transistor 10-1 shown in the embodiment. The main difference between the two is that an anisotropic passivation layer 160 is additionally provided between the interlayer dielectric layer 130 and the semiconductor barrier layer 108, the patterned semiconductor cover layer 110, and the patterned semiconductor protection layer 120 of the high electron mobility transistor 10-3. The passivation layer 160 can be used to eliminate or reduce surface defects existing on the top surface of the semiconductor barrier layer 108, the side surface 110S of the patterned semiconductor cover layer 110, and the side surface 120S of the patterned semiconductor protection layer 120, thereby improving the electrical performance of the high electron mobility transistor 10-3. According to an embodiment of the present invention, the resistivity of the passivation layer 160 is higher than the resistivity of the patterned semiconductor protection layer 120, and the composition of the passivation layer 160 can be silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), or silicon dioxide (SiO2), but is not limited thereto.

[0092] In order to enable those of ordinary skill in the art to implement the content of the present invention, the following further specifically describes the manufacturing method of the high electron mobility transistor of the present invention.

[0093] Figure 5 It is a cross-sectional schematic diagram of manufacturing a high electron mobility transistor according to an embodiment of the present invention, which includes sequentially stacked semiconductor layers. Figure 10It is a flowchart of manufacturing a high electron mobility transistor according to an embodiment of the present invention. According to an embodiment of the present invention, step 202 of manufacturing method 200 can be implemented to provide a substrate, and a semiconductor channel layer, a semiconductor barrier layer, a semiconductor cap layer, and a semiconductor protection layer are sequentially disposed on the substrate. As Figure 5 shown, a buffer layer 104, a semiconductor channel layer 106, a semiconductor barrier layer 108, a semiconductor cap layer 109, and a semiconductor protection layer 111 can be sequentially disposed on the substrate 102 in the semiconductor structure 20. Each stack layer on the substrate 102 can be formed by any suitable method, such as molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods.

[0094] Figure 6 It is a cross-sectional schematic diagram of manufacturing a high electron mobility transistor according to an embodiment of the present invention, including a patterned semiconductor cap layer, a patterned semiconductor protection layer, and a shielding layer. According to an embodiment of the present invention, in Figure 5After the steps shown in the embodiments, a photolithography and etching process may be performed to form the shielding layer 128 with a characteristic pattern. Subsequently, step 204 is performed to etch the semiconductor cover layer and the semiconductor protection layer to form a patterned semiconductor cover layer and a patterned semiconductor protection layer. For example, the shielding layer 128 can be used as an etching mask to perform an etching process to sequentially remove the semiconductor protection layer 111 and the semiconductor cover layer 109 exposed to the shielding layer 128, thereby forming the patterned semiconductor protection layer 120 and the patterned semiconductor cover layer 110. According to an embodiment of the present invention, since the characteristic pattern defined by the shielding layer 128 is transferred to the underlying semiconductor protection layer 111 and semiconductor cover layer 109 through vertical anisotropic etching, the shielding layer 128, the patterned semiconductor protection layer 120, and the patterned semiconductor cover layer 110 can have substantially the same lateral dimension, such as the width D2. Therefore, the side surface 128S of the shielding layer 128, the side surface 110S of the patterned semiconductor cover layer 110, and the side surface 120S of the patterned semiconductor protection layer 120 can be substantially flush with each other. In addition, for the region not covered by the patterned semiconductor cover layer 110, due to the piezoelectric effect generated between the semiconductor channel layer 106 and the semiconductor barrier layer 108, a two-dimensional electron gas can be formed in the two-dimensional electron gas region 106a. In contrast, for the region covered by the patterned semiconductor cover layer 110, since no two-dimensional electron gas is formed, it can be regarded as a two-dimensional electron gas truncation region 106b.

[0095] After the patterned semiconductor protection layer 120 and the patterned semiconductor cover layer 110 are obtained, the shielding layer 128 can be removed to expose the top surface of the patterned semiconductor protection layer 120.

[0096] Figure 7 FIG. is a cross-sectional schematic diagram of manufacturing a high electron mobility transistor according to an embodiment of the present invention, including a gate contact hole disposed in the interlayer dielectric layer. According to an embodiment of the present invention, step 206 is performed to form an interlayer dielectric layer to cover the patterned semiconductor cover layer and the patterned semiconductor protection layer. For example, an interlayer dielectric layer 130 can be formed through a suitable deposition process to completely cover the patterned semiconductor protection layer 120, the patterned semiconductor cover layer 110, the semiconductor barrier layer 108, and the semiconductor channel layer 106. Among them, before removing the shielding layer 128 and after forming the interlayer dielectric layer 130, the width D2 of the patterned semiconductor protection layer 120 can be maintained fixed, so that the side surface 110S of the patterned semiconductor cover layer 110 and the side surface 120S of the patterned semiconductor protection layer 120 can be substantially flush with each other. The material of the interlayer dielectric layer 130 can be Si3N4, AlN, Al2O3, or SiO2, but is not limited thereto.

[0097] Next, step 208 is performed to form a gate contact hole in the interlayer dielectric layer, where the bottom surface of the gate contact hole exposes the patterned semiconductor protection layer and is separated from the patterned semiconductor capping layer. For example, by performing photolithography and etching processes, an opening 134 can be sequentially formed in the interlayer dielectric layer 130, and a groove 126 can be formed on the surface of the patterned semiconductor protection layer 120. Among them, the opening 134 and the groove 126 can constitute the gate contact hole 132. Therefore, the patterned semiconductor protection layer 120 can be exposed from the gate contact hole 126. Among them, the width D1 of the gate contact hole 126 can be smaller than the width D2 of the patterned semiconductor protection layer 120. The bottom surface 126B of the gate contact hole 126 can be located within the patterned semiconductor protection layer 120 and separated from the patterned semiconductor capping layer 110. Therefore, the top surface 122T of the first portion 122 of the patterned semiconductor protection layer 120 can be higher than the top surface 124T of the second portion 124. According to an embodiment of the present invention, the etching process for forming the gate contact hole 132 can include a dry etching process, such as a plasma etching process. Since the bottom surface of the gate contact hole 132 does not penetrate the patterned semiconductor protection layer 120 during the etching process, high-energy etchants (such as plasma etchants) can be avoided from contacting the patterned semiconductor capping layer 110, thereby maintaining the original electrical characteristics of the patterned semiconductor capping layer 110.

[0098] Figure 8 is a cross-sectional schematic diagram of manufacturing a high electron mobility transistor according to an embodiment of the present invention, which includes a gate electrode. According to an embodiment of the present invention, after Figure 7 the steps shown in the embodiment, step 210 can be performed to form a gate electrode in the gate contact hole, where there is a partial patterned semiconductor protection layer between the gate electrode and the patterned semiconductor capping layer. For example, a suitable deposition process can be performed to form a single-layer or multi-layer conductive layer (not shown in the figure) on the top surface of the interlayer dielectric layer 130 and within the gate contact hole 132. Then, photolithography and etching processes are performed to pattern the conductive layer to form the gate electrode 140. According to an embodiment of the present invention, for the gate contact hole 132 with a small opening area, the gate electrode 140 may completely fill the gate contact hole 132, but it is not limited thereto. According to an embodiment of the present invention, the gate electrode 140 can also be disposed only along the inner wall of the gate contact hole 132 without filling the gate contact hole 132. Then, an additional interlayer dielectric layer or a passivation layer, such as the interlayer dielectric layer 150, is formed on the interlayer dielectric layer 130 to cover the gate electrode 140.

[0099] Figure 9 is a cross-sectional schematic diagram of manufacturing a high electron mobility transistor according to an embodiment of the present invention, which includes source / drain contact holes disposed in the interlayer dielectric layer. As Figure 9As shown, at least one source / drain contact hole, such as two source / drain contact holes 152 separated from each other, can be formed on both sides of the gate electrode 140 by performing photolithography and etching processes. When the etching process is completed, the bottom surface 152B of each source / drain contact hole 152 can be located in the semiconductor barrier layer 108 or further extend into the semiconductor channel layer 106 to expose the semiconductor channel layer 106. In addition, since the bottom surface 152B of the source / drain contact hole 152 can be located in the semiconductor channel layer 108 or the semiconductor channel layer 106, a two-dimensional electron gas truncation region 106b is correspondingly formed below each source / drain contact hole 152.

[0100] Next, a suitable deposition process can be performed to form a single-layer or multi-layer conductive layer (not shown in the figure) on the top surface of the interlayer dielectric layer 150 and within the source / drain contact holes 152. Then, photolithography and etching processes are performed to pattern the conductive layer to form source / drain electrodes 154, 156 similar to those Figure 1 shown.

[0101] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, Comprising: A semiconductor channel layer and a semiconductor barrier layer, disposed on a substrate; A patterned semiconductor protective layer, disposed on the semiconductor barrier layer, the composition of the patterned semiconductor protective layer being a silicon-containing semiconductor; A patterned semiconductor capping layer, disposed between the patterned semiconductor protective layer and the semiconductor barrier layer; An interlayer dielectric layer, covering the patterned semiconductor capping layer and the patterned semiconductor protective layer, wherein the interlayer dielectric layer includes a gate contact hole; and A gate electrode, disposed in the gate contact hole and electrically connected to the patterned semiconductor capping layer, wherein a portion of the patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor capping layer, Wherein, the resistivity of the patterned semiconductor protective layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

2. The high electron mobility transistor according to claim 1, characterized in that, The side surface of the patterned semiconductor protective layer is flush with the side surface of the patterned semiconductor capping layer.

3. The high electron mobility transistor according to claim 1, wherein The width of the gate contact hole is smaller than the width of the patterned semiconductor protective layer.

4. The high electron mobility transistor according to claim 1, characterized in that, The electrical connection between the gate electrode and the semiconductor capping layer is formed by Schottky contact.

5. The high electron mobility transistor according to claim 1, characterized in that, The resistivity of the patterned semiconductor protective layer is higher than the resistivity of the gate electrode.

6. The high electron mobility transistor according to claim 1, wherein The gate electrode directly contacts the patterned semiconductor protective layer.

7. The high electron mobility transistor according to claim 6, wherein The gate electrode includes a bottom corner, and the bottom corner directly contacts the patterned semiconductor protective layer.

8. The high electron mobility transistor according to claim 1, wherein: The composition of the patterned semiconductor capping layer is a P-type III-V semiconductor; and The composition of the gate electrode includes a metal.

9. The high electron mobility transistor according to claim 1, wherein The surface of the patterned semiconductor protective layer includes a groove, and the gate electrode fills the groove.

10. The high electron mobility transistor according to claim 9, characterized in that, The patterned semiconductor protective layer includes at least a first portion and a second portion, the at least one first portion is disposed on the periphery of the groove, the second portion is disposed below the groove, and the thickness of the at least one first portion is greater than the thickness of the second portion.

11. The high electron mobility transistor according to claim 1, characterized in that, Further comprising a passivation layer, disposed conformally on the top surface of the semiconductor barrier layer, the side surface of the patterned semiconductor capping layer, and the side surface and top surface of the patterned semiconductor protective layer.

12. A manufacturing method of a high electron mobility transistor, characterized in that, Comprising: Providing a substrate, on which a semiconductor channel layer, a semiconductor barrier layer, a semiconductor capping layer, and a semiconductor protective layer are sequentially disposed, the composition of the semiconductor protective layer being a silicon-containing semiconductor; etching the semiconductor capping layer and the semiconductor protective layer to form a patterned semiconductor capping layer and a patterned semiconductor protective layer; Forming an interlayer dielectric layer to cover the patterned semiconductor capping layer and the patterned semiconductor protective layer; Forming a gate contact hole in the interlayer dielectric layer, wherein the bottom surface of the gate contact hole exposes the patterned semiconductor protective layer and is separated from the patterned semiconductor capping layer; And Forming a gate electrode in the gate contact hole, wherein a portion of the patterned semiconductor protective layer exists between the gate electrode and the patterned semiconductor capping layer, Among them, the resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor cover layer and the resistivity of the interlayer dielectric layer.

13. The manufacturing method of the high electron mobility transistor according to claim 12, wherein Before etching the semiconductor cover layer and the semiconductor protection layer, it further includes forming a shielding layer on the semiconductor protection layer, and when etching the semiconductor cover layer and the semiconductor protection layer, the exposed semiconductor cover layer and semiconductor protection layer outside the shielding layer are removed.

14. The manufacturing method of the high electron mobility transistor according to claim 13, characterized in that, Before forming the interlayer dielectric layer, it further includes removing the shielding layer, wherein before removing the shielding layer and after forming the interlayer dielectric layer, the width of the patterned semiconductor protection layer remains fixed.

15. The manufacturing method of the high electron mobility transistor according to claim 14, wherein Before removing the shielding layer and after forming the interlayer dielectric layer, the side surface of the patterned semiconductor protection layer is flush with the side surface of the patterned semiconductor cover layer.

16. The manufacturing method of a high electron mobility transistor according to claim 12, characterized in that, The step of forming the gate contact hole in the interlayer dielectric layer includes performing a photolithography and etching process.

17. The manufacturing method of a high electron mobility transistor according to claim 12, characterized in that, The resistivity of the patterned semiconductor protection layer is higher than the resistivity of the gate electrode.

18. The manufacturing method of the high electron mobility transistor according to claim 12, characterized in that, The gate electrode directly contacts the patterned semiconductor protection layer.

19. The manufacturing method of a high electron mobility transistor according to claim 12, characterized in that, After forming the gate electrode, the surface of the patterned semiconductor protection layer includes a groove, and the gate electrode fills the groove.

20. The manufacturing method of the high electron mobility transistor according to claim 19, characterized in that, After forming the gate electrode, the patterned semiconductor protection layer includes at least a first part and a second part, the at least one first part is disposed around the groove, the second part is disposed below the groove, and the thickness of the at least one first part is greater than the thickness of the second part.

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