Fluorine incorporation method of nanosheets

Abstract

A method of fluorine incorporation of nanosheets includes the steps of forming a plurality of nanostructures on a substrate; etching the nanostructures to form recesses; forming source / drain regions in the recesses; removing a first nanostructure of the nanostructures, leaving a second nanostructure of the nanostructures; depositing a gate dielectric layer over and around the second nanostructure; depositing a protective material on the gate dielectric layer; fluorine treating the protective material; removing the protective material; depositing a first conductive material on the gate dielectric layer; and depositing a second conductive material on the first conductive material.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of fluorine incorporation for nanosheets. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning each material layer using lithography to form circuit components and elements on the material layers.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the smallest feature size. However, as the smallest feature size is reduced, other problems arise. SUMMARY

[0004] According to some embodiments of the present disclosure, a method of fluorine incorporation for nanosheets includes the following steps. Forming a plurality of nanostructures on a substrate; etching the nanostructures to form a plurality of recesses; forming a plurality of source / drain regions in the recesses; removing a first plurality of the nanostructures, leaving a second plurality of the nanostructures; depositing a gate dielectric layer over and around the second plurality of the nanostructures; depositing a protective material over the gate dielectric layer; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric layer; and depositing a second conductive material over the first conductive material.

[0005] According to some embodiments of the present disclosure, a method of fluorine incorporation for nanosheets includes the following steps. Forming a plurality of nanostructures on a substrate; forming a first dielectric layer over the substrate and around the nanostructures; forming a second dielectric layer over the first dielectric layer; depositing a first conductive material over the second dielectric layer; forming a fluorine-containing layer over the first conductive material; diffusing fluorine from the fluorine-containing layer to the second dielectric layer, wherein the step of diffusing fluorine changes a breakdown voltage of the first dielectric layer and the second dielectric layer; removing the fluorine-containing layer; and forming a second conductive material over the second dielectric layer.

[0006] According to some embodiments of the present disclosure, a method of fluorine doping of nanosheets includes the following steps. Forming a plurality of first nanostructures and a plurality of second nanostructures on a substrate; removing the first nanostructures; forming a first gate dielectric layer around the second nanostructures; tuning a breakdown voltage of the first gate dielectric layer; and forming a first conductive material over the first gate dielectric layer. The step of tuning the breakdown voltage includes the following steps. Forming a protective material over the first gate dielectric layer; forming a fluorine-containing layer over the protective material; diffusing fluorine from the fluorine-containing layer through the protective material into the first gate dielectric layer; and removing the protective material. BRIEF DESCRIPTION OF DRAWINGS

[0007] The various features illustrated in the drawings can not be drawn to scale. Accordingly, the dimensions of the various features can be arbitrarily increased or reduced for the sake of discussion. In addition, not all of the

[0008] FIG. 1 An example of a nanostructure field-effect transistor (nano-FET) according to some embodiments is shown in a perspective view;

[0009] FIG. 2 、 FIG. 3 、 FIG. 4 、 FIG. 5 、 FIG. 6A 、 FIG. 6B 、 FIG. 7A 、 FIG. 7B 、 FIG. 8A 、 FIG. 8B 、 FIG. 9A 、 FIG. 9B 、 FIG. 10A 、 FIG. 10B 、 FIG. 11A 、 FIG. 11B 、 FIG. 11C 、 FIG. 12A 、 FIG. 12B 、 FIG. 12C 、 FIG. 12D 、 FIG. 13A 、 FIG. 13B 、 FIG. 13C 、 FIG. 14A 、 FIG. 14B 、 FIG. 15A 、 FIG. 15B 、 FIG. 16A 、 FIG. 16B 、 FIG. 17A 、 FIG. 17B 、 FIG. 18A 、 FIG. 18B 、 FIG. 19A 、 FIG. 19B 、 FIG. 20A 、FIG. 20B , FIG. 21A , FIG. 21B , FIG. 22A , FIG. 22B , FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A , FIG. 25B , FIG. 25C , FIG. 25D , FIG. 26A , FIG. 26B , FIG. 27A , FIG. 27B , FIG. 27C , FIG. 28A , FIG. 28B , FIG. 28C , FIG. 29A , FIG. 29B and FIG. 29C are cross-sectional views of intermediate stages of manufacturing a nano-FET according to some embodiments;

[0010] FIG. 30A , FIG. 30B and FIG. 30C are cross-sectional views of a nano-FET according to some other embodiments.

[0011] [Explanation of symbols]

[0012] 20: spacer

[0013] 50: substrate

[0014] 50N: n-type region

[0015] 50P: p-type region

[0016] 50I: region

[0017] 51A-51C: first semiconductor layer

[0018] 52A-52C: first nanostructure

[0019] 53A-53C: second semiconductor layer

[0020] 54A-54C: second nanostructure

[0021] 55: nanostructure

[0022] 60: dummy dielectric layer

[0023] 64: multilayer stack

[0024] 66: fin

[0025] 68: isolation region

[0026] 70: dummy dielectric layer

[0027] 71: dummy gate dielectric layer

[0028] 72: dummy gate layer

[0029] 74: mask layer

[0030] 76: dummy gate

[0031] 78: mask

[0032] 80: first spacer layer

[0033] 81: first spacer

[0034] 82: second spacer layer

[0035] 83: second spacer

[0036] 86: first recess

[0037] 88: sidewall recess

[0038] 90: first inner spacer

[0039] 92: epitaxial source / drain region

[0040] 92A: first semiconductor material layer

[0041] 92B: second semiconductor material layer

[0042] 92C: third semiconductor material layer

[0043] 94: contact etch stop layer

[0044] 96: first interlayer dielectric

[0045] 98: second recess

[0046] 100: gate dielectric layer

[0047] 101: first gate dielectric layer

[0048] 102: gate electrode

[0049] 103: second gate dielectric layer

[0050] 104: mask

[0051] 105: first conductive material

[0052] 106: second interlayer dielectric

[0053] 107: second conductive material

[0054] 107A: first portion

[0055] 107B: second portion

[0056] 107S: interface

[0057] 108: third recess

[0058] 110: silicide region

[0059] 112, 114: contacts

[0060] 117: adhesive layer

[0061] 119: fill metal

[0062] 121: third conductive material

[0063] 123: barrier layer

[0064] 125: fill metal

[0065] 127: gate electrode

[0066] 130: opening

[0067] 140: protective material

[0068] 144: fluorine-containing layer

[0069] 200: anneal process

[0070] A-A', B-B', C-C': cross-section

[0071] X-X', Y-Y': line DETAILED DESCRIPTION

[0072] The following disclosure provides many different embodiments, or "examples," for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forms a first feature over or on a second feature in the written description can include embodiments where the first and second features are formed directly on each other, and can also include embodiments where additional features are formed between the first and second features such that the first and second features can not be directly in contact. In addition, the present disclosure can repeat use of reference numerals in the various examples as a matter of convenience and clarity. This repetition of reference numerals is not to be construed as a limitation with respect to the scope of the various embodiments or any other embodiments of the present disclosure.

[0073] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

[0074] Various embodiments provide a gate stack with fluorine treated gate dielectric layers (e.g., an interface layer and a high-k gate dielectric layer). For example, after forming the gate dielectric layers, a protective layer is formed to protect the high-k gate dielectric layer from damage or etching during subsequent fluorine treatment. The fluorine treatment begins by depositing a fluorine-containing layer on the protective layer or by converting an upper portion of the protective layer into a fluorine-containing layer. After forming the fluorine-containing layer, an anneal process is performed to diffuse fluorine from the fluorine-containing layer through the protective layer into the gate dielectric layers. The fluorine can fill some or all of the vacancies in the gate dielectric layers (e.g., in the high-k gate dielectric layer). In addition, the fluorine can attach to dangling bonds (e.g., silicon dangling bonds) near the interface between the interface layer and the semiconductor substrate of the underlying layer. Thus, the effective oxide thickness of the high-k gate dielectric layer and the interface layer can be tuned (e.g., voltage tuning) while also improving reliability and mobility. The semiconductor devices with greater robustness can be manufactured with improved yield and functionality.

[0075] FIG. 1 An example of a nanometer FET (e.g., nanowire FET, nanosheet FET, nanostructure FET, etc.) is shown in perspective view according to some embodiments. The nanometer FET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) on a fin 66 of a substrate 50 (e.g., semiconductor substrate), where the nanostructure 55 serves as a channel region of the nanometer FET. The nanostructure 55 can include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, which can protrude above and between adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" can refer to either a standalone semiconductor substrate or a combination of a semiconductor substrate and an isolation region. In addition, although a bottom portion of the fin 66 is illustrated as having a single continuous material of the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 can include a single material or multiple materials. Herein, the fin 66 refers to the portion that extends between adjacent isolation regions 68.

[0076] A gate dielectric layer 100 is located over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostmcture 55. A gate electrode 102 is located over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0077] FIG. 1 Further shown are reference cross-sections used in the later figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanometer FET. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fin 66 of the nanometer FET and in a direction, for example, of current between the epitaxial source / drain regions 92 of the nanometer FET. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the nanometer FET. For clarity, the subsequent figures refer to these reference cross-sections.

[0078] Some embodiments discussed herein are discussed in the context of nanometer FETs formed using a gate-last process. In other embodiments, a gate-first process can be used. In addition, some embodiments contemplate versions used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0079] FIGS. 2-30C A cross-sectional view of an intermediate stage in the fabrication of a nanometer FET according to some embodiments. FIGS. 2-5 FIG. 6A FIG. 13A FIG. 14A FIG. 15A FIG. 16A FIG. 17A FIG. 18A FIG. 19A FIG. 20A FIG. 21A FIG. 22A FIG. 23A FIG. 24A FIG. 25A FIG. 26A FIG. 27A FIG. 28A FIG. 29A and FIG. 30A shows a reference cross-section A-A' as shown in FIG. 1 FIG. 6B FIG. 7B FIG. 8B FIG. 9B FIG. 10B FIG. 11B FIG. 11C FIG. 12B FIG. 12D FIG. 13B ​​​​​​​​​​​​​​​​​​​​​​​​​​​​、 FIG. 14B 、 FIG. 15B 、 FIG. 16B 、 FIG. 17B 、 FIG. 18B 、 FIG. 19B 、 FIG. 20B 、 FIG. 21B 、 FIG. 22B 、 FIG. 23B 、 FIG. 24B 、 FIG. 25B 、 FIG. 26B 、 FIG. 27B 、 FIG. 28B 、 FIG. 29B and FIG. 30B shows a reference cross-section B-B' as shown in FIG. 1 . FIG. 7A 、 FIG. 8A 、 FIG. 9A 、 FIG. 10A 、 FIG. 11A 、 FIG. 12A 、 FIG. 12C 、 FIG. 13C 、 FIG. 25C 、 FIG. 27C 、 FIG. 28C 、 FIG. 29C and FIG. 30C shows a reference cross-section C-C' as shown in FIG. 1 .

[0080] In FIG. 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, which can or can not be doped (e.g., with p-type or n-type dopants). The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates can also be used, such as a multilayer or graded substrate. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide indium; or combinations thereof.

[0081] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors (e.g., n-type nanometer FETs), while the p-type region 50P can be used to form p-type devices, such as PMOS transistors (e.g., p-type nanometer FETs). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the spacer 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. In some embodiments, one or more wells and / or anti-punch through (APT) layers can be formed in the substrate 50 via one or more suitable implantation steps.

[0082] Further, in FIG. 2 The multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively, first semiconductor layers 51) and second semiconductor layers 53A-C (collectively, second semiconductor layers 53). For purposes of illustration and as discussed in greater detail below, the second semiconductor layers 53 will be removed and the first semiconductor layers 51 will be patterned to form channel regions of nanometer FETs in the p-type region 50P. In addition, the first semiconductor layers 51 will be removed and the second semiconductor layers 53 will be patterned to form channel regions of nanometer FETs in the n-type region 50N. However, in some embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be patterned to form channel regions of nanometer FETs in the n-type region 50N, and the second semiconductor layers 53 can be removed and the first semiconductor layers 51 can be patterned to form channel regions of nanometer FETs in the p-type region 50P.

[0083] In other embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be patterned to form channel regions of nanometer FETs in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layers 53 can be removed and the first semiconductor layers 51 can be patterned to form channel regions of non-FETs in both the n-type region 50N and the p-type region 50P. In these embodiments, the channel regions in the n-type region 50N and the p-type region 50P can have the same material composition (e.g., silicon, etc.) and can be formed simultaneously. FIGS. 30A-30C Structures resulting from these embodiments are shown, in which the channel regions in both the p-type region 50P and the n-type region 50N include, for example, silicon.

[0084] For purposes of illustration, the multi-layer stack 64 is shown as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multi-layer stack 64 can include any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each layer of the multi-layer stack 64 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layers 51 can be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, etc., while the second semiconductor layers 53 can be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, etc. For purposes of illustration, the multi-layer stack 64 is shown as having the bottom-most semiconductor layers suitable for p-type nano-FETs. In some embodiments, the multi-layer stack 64 can be formed such that the bottom-most layer is a semiconductor layer suitable for n-type nano-FETs.

[0085] The first semiconductor material and the second semiconductor material can be materials having high etch selectivity with respect to each other. As such, the first semiconductor layers 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layers 53 of the second semiconductor material in the n-type regions 50N, thereby allowing the second semiconductor layers 53 to be patterned to form channel regions of n-type nano-FETs. Similarly, the second semiconductor layers 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layers 51 of the first semiconductor material in the p-type regions 50P, thereby allowing the first semiconductor layers 51 to be patterned to form channel regions of p-type nano-FETs. In other embodiments, the channel regions in the n-type regions 50N and the p-type regions 50P can be formed simultaneously and have the same material composition, such as silicon, silicon germanium, etc. FIG. 28A 、 FIG. 28B and FIG. 28C Structures resulting from these embodiments are shown, in which the channel regions in both the p-type regions 50P and the n-type regions 50N include, for example, silicon.

[0086] Referring now to FIG. 3According to some embodiments, the fins 66 are formed in the substrate 50 and the nanostructures 55 are formed in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching can be anisotropic. Forming the nanostructures 55 by etching the multilayer stack 64 can further define first nanostructures 52A-52C (collectively, first nanostructures 52) by the first semiconductor layer 51 and second nanostructures 54A-54C (collectively, second nanostructures 54) by the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 can be further collectively referred to as the nanostructures 55.

[0087] The fins 66 and the nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and the nanostructures 55 can be patterned using one or more lithography processes, including a double patterning or a multiple patterning process. Generally, a double patterning process or a multiple patterning process combines lithography with a self-alignment process, allowing for the creation of patterns having a pitch, for example, that is less than that obtained using a single direct lithography process. For example, in some embodiments, a lithography process is used to pattern a sacrificial layer formed over the substrate. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0088] For illustrative purposes, FIG. 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the widths of the fins 66 in the n-type region 50N can be greater than or less than the widths of the fins 66 in the p-type region 50P. Furthermore, although each of the fins 66 and the nanostructures 55 are shown as consistently having a uniform width, in other embodiments, the fins 66 and / or the nanostructures 55 can have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 continuously increases in a direction toward the substrate 50. In these embodiments, each of the nanostructures 55 can have a different width and be shaped as a trapezoid.

[0089] In FIG. 4In some embodiments, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an anneal process can be performed. In embodiments, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a fill material, such as those discussed above, can be formed over the liner.

[0090] A removal process is then applied to the insulating material to remove the excess insulating material over the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like, can be utilized. The planarization process exposes the nanostructure 55 such that the top surface of the nanostructure 55 is flush with the insulating material after the planarization process is completed.

[0091] The insulating material is then recessed to form the STI region 68. The insulating material is recessed such that the upper portions of the fin 66 in the n-type region 50N and the p-type region 50P protrude from between the adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface (e.g., recessed), or a combination thereof, as shown. The top surface of the STI region 68 can be made flat, convex, and / or concave by an appropriate etch. The STI region 68 can be recessed using an acceptable etch process, such as an etch process selective to the material of the insulating material (e.g., etches the material of the insulating material at a faster rate than the materials of the fin 66 and the nanostructure 55). For example, oxide removal, such as using dilute hydrofluoric acid (dHF), can be used.

[0092] Previously, with respect to FIGS. 2-4The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, a mask and epitaxial growth process can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown in the trenches, and the dielectric layer can be recessed so that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures can include the aforementioned alternating semiconductor materials, such as the first and second semiconductor materials. In some embodiments in which the epitaxial structures are grown, the epitaxially grown material can be doped in situ during growth, although in situ and implantation doping can be used together, this can eliminate prior and / or subsequent implantation.

[0093] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and resulting first nanostructures 52) and the second semiconductor layer 53 (and resulting second nanostructures 54) are described and discussed herein as including the same materials in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 can be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0094] Furthermore, in FIG. 4 , appropriate wells (not shown separately) can be formed in the fins 66, nanostructures 55, and / or STI regions 68. In embodiments having different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be achieved using a photoresist or other mask (not shown separately). For example, a photoresist can be formed over the fins 66 and STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent the n-type impurity implantation into the n-type region 50N. The n-type impurity can be phosphorous, arsenic, antimony, etc., implanted in the region at a concentration in a range of about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 . After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0095] After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity implantation into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in the region at a concentration in a range of about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 . After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0096] After implantation of the n-type region 50N and p-type region 50P, annealing can be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be doped in situ during growth, which can eliminate implantation, although in situ and implantation doping can be used together.

[0097] After FIG. 5In this process, a simulated dielectric layer 70 is formed on the fins 66 and / or nanostructures 55. The simulated dielectric layer 70 may be, for example, silicon oxide, silicon nitride, or combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A simulated gate layer 72 is formed above the simulated dielectric layer 70, and a mask layer 74 is formed above the simulated gate layer 72. The simulated gate layer 72 may be deposited above the simulated dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited above the simulated gate layer 72. The simulated gate layer 72 may be a conductive or non-conductive material and may be selected from amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The simulated gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used for depositing the selected material. The simulated gate layer 72 may be made of other materials that have high etch selectivity for etching the isolation regions. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single simulated gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the simulated dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the simulated dielectric layer 70 may be deposited such that the simulated dielectric layer 70 covers the STI region 68, such that the simulated dielectric layer 70 extends between the simulated gate layer 72 and the STI region 68.

[0098] FIGS. 6A-15B Various additional steps in the manufacturing embodiment apparatus are shown. FIG. 6A , FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A , FIG. 11A , FIG. 12A , FIG. 12C , FIG. 13A , FIG. 13C , FIG. 14A and FIG. 15A Features in the n-type region 50N or the p-type region 50P are shown. FIG. 6A and FIG. 6B In the middle, the curtain layer 74 (see FIG. 5 The mask 78 can be patterned using acceptable lithography and etching techniques. The pattern of the mask 78 can then be transferred to the simulated gate layer 72 and the simulated dielectric layer 70 to form the simulated gate 76 and the simulated gate dielectric layer 71, respectively. The simulated gate 76 covers the corresponding channel regions of the fin 66. The pattern of the mask 78 can be used to separate each of the simulated gates 76 from the adjacent simulated gate 76 entities. The simulated gates 76 may also have a length direction generally perpendicular to the length of each fin 66.

[0099] In FIG. 7A and FIG. 7B , first spacer layers 80 and second spacer layers 82 are formed on the structures shown in FIG. 6A and FIG. 6B , respectively. The first spacer layers 80 and the second spacer layers 82 are then patterned as spacers for forming self-aligned source / drain regions. In FIG. 7A and FIG. 7B , the first spacer layers 80 are formed on the top surfaces of the STI regions 68; on the top surfaces and sidewalls of the fins 66, the nanostructures 55, and the caps 78; and on the sidewalls of the dummy gates 76 and the dummy gate dielectric layers 71. The second spacer layers 82 are deposited over the first spacer layers 80. The first spacer layers 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation or can be deposited by CVD, ALD, etc. The second spacer layers 82 can be formed of a material having a different etch rate than the material of the first spacer layers 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0100] After the first spacer layers 80 are formed and before the second spacer layers 82 are formed, implantation of lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments having different device types, similar to the implantation discussed above in FIG. 4 , a cap, such as a photoresist, can be formed over the n-type regions 50N while the p-type regions 50P are exposed, and impurities of the appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-type regions 50P. The cap can then be removed. Subsequently, a cap, such as a photoresist, can be formed over the p-type regions 50P while the n-type regions 50N are exposed, and impurities of the appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 in the n-type regions 50N. The cap can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The impurity concentration of the lightly doped source / drain regions can be in the range of about 1 x 1010atoms / cm2to about 1 x 1011atoms / cm2. Annealing can be used to repair implant damage and activate the implanted impurities. 15 3 19 3

[0101] In FIG. 8A and FIG. 8B ​​​​In some embodiments, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacers 81 and the second spacers 83. As will be discussed in more detail below, the first spacers 81 and the second spacers 83 are used to self-align subsequently formed source / drain regions, as well as to protect sidewalls of the fins 66 and / or the nanostructures 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), combinations thereof, and the like. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop when patterning the second spacer layer 82, and the second spacer layer 82 can act as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, where the first spacer layer 80 acts as an etch stop, where as shown in FIG. 8A the remaining portions of the second spacer layer 82 form the second spacers 83. Thereafter, while the exposed portions of the first spacer layer 80 are etched, the second spacers 83 act as a mask, thereby forming the first spacers 81 as shown in FIG. 8A

[0102] As shown in FIG. 8A the first spacers 81 and the second spacers 83 are disposed on sidewalls of the fins 66 and / or the nanostructures 55. As shown in FIG. 8B In some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric layer 71, and the first spacers 81 are disposed on sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 can remain on the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric layer 71.

[0103] Note that the above disclosure generally describes processes of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different sequences of steps can be used (e.g., the first spacers 81 can be patterned prior to depositing the second spacer layer 82), additional spacers can be formed and removed, and the like. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0104] In FIG. 9A and FIG. 9B ​In some embodiments, a first groove 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region is then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. FIG. 9A As shown, the top surface of the STI region 68 can be flush with the bottom surface of the first groove 86. In various embodiments, the fins 66 can be etched such that the bottom surface of the first groove 86 is positioned below the top surface of the STI region 68, etc. The first groove 86 can be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. The first spacer 81, the second spacer 83, and the mask 78 mask the fins 66, the nanostructures 55, and the substrate 50 during the etching process for forming the first groove 86. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 55 and / or the fins 66. A timed etching process can be used to terminate the etching of the first groove 86 after the first groove 86 reaches the desired depth.

[0105] exist FIG. 10A and FIG. 10B In this process, portions of the sidewalls of the layers of the multilayer stack 64 formed by the first semiconductor material (e.g., the first nanostructure 52) exposed by the first groove 86 are etched to form sidewall grooves 88 in the n-type region 50N, and portions of the sidewalls of the layers of the multilayer stack 64 formed by the second semiconductor material (e.g., the second nanostructure 54) exposed by the first groove 86 are etched to form sidewall grooves 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the groove 88 are... FIG. 10B The p-type region 50P is shown as straight, but the sidewalls can be concave or convex. Isotropic etching processes, such as wet etching, can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 50P while an etchant selectively targeting the first semiconductor material is used to etch the first nanostructure 52, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, a mask (not shown) can be used to protect the n-type region 50N while an etchant selectively targeting the second semiconductor material is used to etch the second nanostructure 54, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a dry etching process using hydrogen fluoride, another fluorine-based gas, etc., can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0106] In FIGS. 11A-11C , a first inner spacer 90 is formed in the sidewall recess 88. The first inner spacer 90 can be formed by depositing an inner spacer layer (not shown separately) over the structure shown in FIG. 10A and FIG. 10B . The first inner spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the gate structures. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, while the first nanostructures 52 in the n-type region 50N and the second nanostructures 54 in the p-type region 50P are replaced with respective gate structures.

[0107] The inner spacer layer can be deposited by a conformal deposition process, such as CVD, ALD, etc. The inner spacer layer can include a material such as silicon nitride or silicon oxynitride, although any suitable material can be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer can then be anisotropically etched to form the first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown as being flush with the sidewalls of the second nanostructures 54 in the n-type region 50N and the first nanostructures 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 can extend beyond or be recessed from the sidewalls of the second nanostructures 54 and / or the first nanostructures 52, respectively.

[0108] Further, although the outer sidewalls of the first inner spacer 90 are shown as being straight in FIG. 11B , the outer sidewalls of the first inner spacer 90 can be concave or convex. For example, FIG. 11C embodiments are shown in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the second nanostructures 54 in the n-type region 50N. Embodiments are also shown in which the sidewalls of the second nanostructures 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the first nanostructures 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etch process, such as RIE, NBE, etc. The first inner spacer 90 can serve to protect the subsequently formed source / drain regions (such as epitaxial source / drain regions 92, discussed below with respect to FIGS. 12A-12C ) from damage by subsequent etch processes, such as etch processes used to form the gate structures.

[0109] In FIGS. 12A-12C , epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the source / drain regions 92 can exert stress on the second nanostructures 54 in the n-type region 50N and the first nanostructures 52 in the p-type region 50P, thereby improving performance. AsFIG. 12B As shown, epitaxial source / drain regions 92 are formed in the first recesses 86 such that each dummy gate 76 is disposed between a respective pair of adjacent epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72, and the first inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the nanostructures 55 by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short to subsequently formed gates of the resulting nano-FETs.

[0110] Epitaxial source / drain regions 92 in the n-type regions 50N (e.g., NMOS regions) can be formed by masking the p-type regions 50P (e.g., PMOS regions). The epitaxial source / drain regions 92 are then epitaxially grown in the first recesses 86 in the n-type regions 50N. The epitaxial source / drain regions 92 can include any acceptable material suitable for n-type nano-FETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 can include a material that exerts tensile strain on the second nanostructures 54, such as silicon, silicon carbide, phosphorous-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 92 can have a surface that is raised from the respective upper surfaces of the nanostructures 55 and can have facets.

[0111] Epitaxial source / drain regions 92 in the p-type regions 50P (e.g., PMOS regions) can be formed by masking the n-type regions 50N (e.g., NMOS regions). The epitaxial source / drain regions 92 are then epitaxially grown in the first recesses 86 in the p-type regions 50P. The epitaxial source / drain regions 92 can include any acceptable material suitable for p-type nano-FETs. For example, if the first nanostructures 52 are silicon germanium, the epitaxial source / drain regions 92 can include a material that exerts compressive strain on the first nanostructures 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 92 can also have a surface that is raised from the respective surfaces of the multi-layer stacks 64 and can have facets.

[0112] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have an impurity concentration between about 1 x 1010atoms / cm2and about 1 x 1016atoms / cm2. The n-type and / or p-type impurities of the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth. 19 atoms / cm2 3 atoms / cm2 21 atoms / cm2 3 atoms / cm2

[0113] Due to the epitaxial process for forming epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that laterally extend outward beyond the sidewalls of nanowire structures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, as shown in FIG. 12A FIG. 12C In other embodiments, as shown in FIG. 12A FIG. 12C In embodiments shown in

[0114] Epitaxial source / drain regions 92 can include one or more layers of semiconductor material. For example, epitaxial source / drain regions 92 can include a first layer of semiconductor material 92A, a second layer of semiconductor material 92B, and a third layer of semiconductor material 92C. Any number of layers of semiconductor material can be used for epitaxial source / drain regions 92. Each of the first layer of semiconductor material 92A, the second layer of semiconductor material 92B, and the third layer of semiconductor material 92C can be formed of a different semiconductor material and can be doped to a different dopant concentration. In some embodiments, the first layer of semiconductor material 92A can have a dopant concentration that is less than the second layer of semiconductor material 92B and greater than the third layer of semiconductor material 92C. In embodiments in which epitaxial source / drain regions 92 include three layers of semiconductor material, the first layer of semiconductor material 92A can be deposited, the second layer of semiconductor material 92B can be deposited on the first layer of semiconductor material 92A, and the third layer of semiconductor material 92C can be deposited on the second layer of semiconductor material 92B.

[0115] FIG. 12D Embodiments are shown in which the sidewalls of the first nanowire structures 52 in n-type region 50N and the sidewalls of the second nanowire structures 54 in p-type region 50P are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from the sidewalls of the second nanowire structures 54 and the first nanowire structures 52, respectively. As shown in FIG. 12D ​​As shown, the epitaxial source / drain region 92 can be formed to contact the first inner spacer 90 and can extend through the sidewalls of the second nanostructure 54 in the n-type region 50N and through the sidewalls of the first nanostructure 52 in the p-type region 50P. Furthermore, in embodiments where the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, the epitaxial source / drain region 92 can be formed between the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0116] exist FIGS. 13A-13C In the middle, the first interlayer dielectric (ILD) 96 is deposited on FIG. 6A , FIG. 12B and FIG. 12A The structure shown ( FIGS. 7A-12D The manufacturing process remains unchanged. FIG. 6A (See the cross-section shown). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The CESL 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from that of the material covering the first ILD 96.

[0117] exist FIG. 14A and FIG. 14B In this process, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 96 flush with the top surface of the emulated gate 76 or the mask 78. The planarization process may also remove the mask 78 on the emulated gate 76, as well as a portion of the first sidewall 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the emulated gate 76, the first spacer 81, and the first ILD 96 are flush during the process change. Therefore, the top surface of the emulated gate 72 is exposed by the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surface of the mask 78 and the first spacer 81.

[0118] exist FIG. 15A and FIG. 15BIn some embodiments, the dummy gate 72 and the mask 78, if present, are removed in one or more etching steps, forming second recesses 98. Portions of the dummy dielectric layer 60 in the second recesses 98 can also be removed. In some embodiments, the dummy gate 72 and the dummy dielectric layer 60 are removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using a reactive gas that selectively etches the dummy gate 72 at a faster rate than the first ILD 96 or the first spacers 81. Each second recess 98 exposes and / or covers portions of the nanostructures 55 that act as channel regions in the nanometer FETs that are subsequently completed. The nanostructures 55 that act as portions of the channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 can act as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 can then be removed after the dummy gate 72 is removed.

[0119] In FIG. 16A and FIG. 16B To form the openings 130, in some embodiments, the second nanostructures 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process, such as a wet etch, using an etchant that is selective to the material of the second nanostructures 54, while the first nanostructures 52, the substrate 50, and the STI regions 68 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 include, for example, SiGe, and the first nanostructures 52 include, for example, Si or SiC, hydrogen fluoride, another fluorine-based gas, or the like can be used to remove the second nanostructures 54 in the p-type region 50P. After the removal process, the openings 130 include regions 50I between each of the first nanostructures 52.

[0120] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructures 52 in the n-type region 50N and the p-type region 50P or by removing the second nanostructures 54 in the n-type region 50N and the p-type region 50P. In these embodiments, the channel regions of the n-type nanometer FETs and the p-type nanometer FETs can have the same material composition, such as silicon, silicon germanium, or the like. FIG. 28A 、 FIG. 28B and FIG. 28C An example of a structure resulting from these embodiments is shown, in which the channel regions in the p-type region 50P and the n-type region 50N are provided by the second nanostructures 54 and include, for example, silicon.

[0121] In FIGS. 17A-26BIn some embodiments, the gate dielectric layer 100 and the gate electrode 102 / 127 are formed to replace the gate structure in the second recess 98. The gate dielectric layer 100 (e.g., a high-k gate dielectric layer) and the gate electrode 102 (e.g., a work function metal or WFM layer) are treated with aluminum and fluorine, respectively. As a result of the aluminum and fluorine soak discussed in more detail below, the flat band voltage (VFB) of the resulting transistor can increase toward the band edge of the metal of the WFM layer, the threshold voltage of the resulting transistor can decrease, and device performance can be improved. FB ) can increase toward the band edge of the metal of the WFM layer, the threshold voltage of the resulting transistor can decrease, and device performance can be improved.

[0122] The formation of the gate dielectric layer in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer in each region is formed from the same material, and the formation of the gate electrode can occur simultaneously, such that the gate electrode in each region is formed from the same material. In some embodiments, the gate dielectric layer in each region can be formed by different processes, such that the gate dielectric layers can be different materials and / or have different numbers of layers, and / or the gate electrode in each region can be formed by different processes, such that the gate electrodes can be different materials and / or have different numbers of layers. When different processes are used, various masking steps can be used to mask and expose the appropriate regions. In the following description, the gate electrode of the n-type region 50N and the gate electrode of the p-type region 50P are formed separately.

[0123] FIGS. 17A-25D The formation of the gate dielectric layer 100, the performance of the fluorine treatment, and the formation of the gate electrode 102 in the p-type region 50P are shown. In some embodiments, the n-type region 50N can be masked while the gate electrode 102 is formed in the p-type region 50P, at least. Although the p-type region 50P is shown, the gate dielectric layer 100 can be formed in the n-type region 50N simultaneously or separately. Further, the fluorine treatment can also be performed in the n-type region 50N simultaneously or separately.

[0124] In FIG. 17A and FIG. 17BIn some embodiments, the gate dielectric layer 100 is conformally deposited in the second recess 98 in the p-type region 50P. The gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 can include a first gate dielectric layer 101 (e.g., including silicon oxide, etc.) and a second gate dielectric layer 103 (e.g., including a metal oxide, etc.) on the first gate dielectric layer 101. In some embodiments, the second gate dielectric layer 103 includes a high-k dielectric material, and in these embodiments, the second gate dielectric layer 103 can have a k-value greater than about 7.0, and can include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. In some embodiments, the first gate dielectric layer 101 can be referred to as an interface layer, and the second gate dielectric layer 103 can be referred to as a high-k gate dielectric layer. In some embodiments, the formation of the gate dielectric layer 100 can include forming vacancies or voids in the material. For example, the vacancies can be portions of the first gate dielectric layer 101 and the second gate dielectric layer 103 where the dielectric material can not have fully coalesced during or after deposition. Further, the formation of the first gate dielectric layer 101 over the substrate 50 (e.g., the fin 66) can also result in dangling bonds (e.g., silicon dangling bonds) at the interface between the first gate dielectric layer 101 and the substrate 50, for example, due to incomplete reactions during formation.

[0125] In the n-type region 50N and the p-type region 50P, the structure of the gate dielectric layer 100 can be the same or different. For example, while the gate dielectric layer 100 is formed in the p-type region 50P, the n-type region 50N can be masked or exposed. In embodiments where the n-type region 50N is exposed, the gate dielectric layer 100 can be formed in the n-type region 50N at the same time. The method of forming the gate dielectric layer 100 can include molecular-beam deposition (MBD), ALD, PECVD, etc.

[0126] In FIG. 18A and FIG. 18B , the protective material 140 is conformally deposited over the gate dielectric layer 100. In some embodiments, the protective material 140 is a conductive material including titanium nitride, tantalum nitride, silicon titanium nitride (TiSiN or TSN), etc. The protective material 140 can be deposited by CVD, ALD, PECVD, etc. For example, the protective material 140 can be formed at a temperature between about 300 °C and about 600 °C and a pressure between about 0.2 Torr and about 50 Torr. As described below, the protective material 140 will protect the underlying gate dielectric layer 100 during subsequent processing steps, such as during fluorine treatment.

[0127] The depositable protective material 140 can be deposited to surround each of the first nanostructures 52 and form a thickness of between about 5 Angstroms and about 20 Angstroms. A protective material 140 greater than 5 Angstroms ensures a complete monolayer of deposition (e.g., titanium nitride). A protective material 140 less than 20 Angstroms ensures that a required or sufficient amount of fluorine is able to pass through the protective material 140 and into the gate dielectric layer 100 during fluorine treatment. Further, a protective material 140 less than 20 Angstroms ensures that the gate dielectric layer 100 maintains a low concentration level of metal elements that can diffuse from the protective material 140.

[0128] In FIG. 19A and FIG. 19B a fluorine-containing layer 144 is formed over the protective material 140 by a deposition process or a soak process. In embodiments that use a deposition process, such as CVD, ALD, etc., the fluorine-containing layer 144 is deposited over the surface of the protective material 140. For example, a fluorine-containing precursor and a reducing agent precursor flow over the surface of the protective material 140. The fluorine-containing precursor can be WF6and the reducing agent precursor can be SiH4, B2H6, H2, etc., or combinations thereof. The presence of the protective material 140 prevents the precursors (e.g., the fluorine-containing precursor) from etching the second gate dielectric layer 103. The fluorine-containing layer 144 can be deposited at a temperature between about 250 °C and about 475 °C and a pressure between about 0.5 Torr and about 400 Torr. Fluorine is part of the gas phase byproducts removed during the deposition of the fluorine-containing layer 144 in reactions that do not go to completion. As a result, the fluorine-containing layer 144 deposited on the protective material 140 can primarily comprise tungsten with a trace amount of fluorine remaining in the layer. For example, the fluorine concentration in the deposited fluorine-containing layer 144 can be less than about 30%.

[0129] In embodiments that use a soak process, a fluorine-containing precursor flows over the surface of the protective material 140 to convert an upper portion of the protective material 140 to the fluorine-containing layer 144. The fluorine-containing precursor can be WF6, NF3, CF4, CaF2, CrF6, MoF6, etc., or combinations thereof. The molecules of the fluorine-containing precursor can remain intact upon diffusion to the upper portion of the protective material 140, or the molecules of the fluorine-containing precursor can at least partially dissociate. In some embodiments not specifically illustrated, the soak process can further form a discontinuous fluorine-containing residue on the surface of the protective material 140. The soak process can be performed at a temperature between about 250 °C and about 475 °C, at a pressure between about 0.5 Torr and about 50 Torr, and for a duration of about 0.1 seconds to about 1 hour.

[0130] In FIG. 20A and FIG. 20BIn the process, an annealing process 200 is performed to diffuse fluorine from the fluorine-containing layer 144 through the protective material 140 into the gate dielectric layer 100. The protective material 140 contains a metal (e.g., titanium), and the fluorine-containing layer 144 (e.g., tungsten) further aids in attracting and driving the fluorine into the gate dielectric layer 100. Some fluorine fills vacancies or microvoids in the gate dielectric layer 100, and some fluorine may adhere to silicon dangling bonds at the interface between the first gate dielectric layer 101 and the substrate 50. The annealing process 200 can be performed at a temperature between about 150°C and about 750°C for a duration between about 0.5 seconds and about 60 seconds.

[0131] Following annealing process 200, the second gate dielectric layer 103 (e.g., comprising hafnium oxide) may have a fluorine-metal (e.g., fluorine-hafnium) atomic ratio between about 0.005 and about 0.05. Furthermore, some fluorine may reach the first gate dielectric layer 101 and cause minor regrowth of the first gate dielectric layer 101. Introducing fluorine or increasing the fluorine concentration in the gate dielectric layer 100 (e.g., the second gate dielectric layer 103) allows tuning of the threshold or breakdown voltage of the gate structure. However, excessive fluorine in the gate dielectric layer 100, such as a fluorine-hafnium ratio greater than about 0.05 in the second gate dielectric layer 103, may result in a loss of capacitance equivalent thickness (CET) in the first gate dielectric layer 101 (e.g., excessive regrowth). Furthermore, the annealing process 200 can cause metals (e.g., titanium) from the protective material 140 and / or metals (e.g., tungsten) from the fluorine-containing layer 144 to reach the gate dielectric layer 100. For example, the second gate dielectric layer 103 may have a titanium atom concentration between about 0.1% and about 5% and a tungsten atom concentration between about 0.1% and about 5%. The titanium and / or tungsten reaching the second gate dielectric layer 103 may cause additional fluorine to migrate into the first gate dielectric layer 101. Maintaining each of these concentrations in the second gate dielectric layer 103 below 5% reduces the CET that may be caused by these metals and maintains the desired quality and effective oxide thickness of the gate dielectric layer 100.

[0132] exist FIG. 21A and FIG. 21B In this process, an etching process is used to remove the fluorine-containing layer 144 and the protective material 140 to expose the second gate dielectric layer 103. For example, the etching process can be an isotropic wet etching using HCl, H2O2, H2O, or combinations thereof, or any suitable material as the etchant. According to some embodiments, a combination of etchants containing HCl, H2O2, and H2O can be used to remove the fluorine-containing layer 144 and the protective material 140. In other embodiments, a combination of etching process and etchant can be used to remove the fluorine-containing layer 144, while another etching process and / or combination of etchant can be used to remove the protective material 140.

[0133] In FIG. 22A And FIG. 22B In some embodiments, the first conductive material 105 is a p-type WFM layer including titanium nitride, tantalum nitride, silicon titanium nitride, or the like. The first conductive material 105 can be deposited by CVD, ALD, PECVD, PVD, or the like. The first conductive material 105 can be deposited to surround each first nanostructure 52. In some embodiments, the first conductive material 105 can only partially fill the region 50I. Thus, after deposition of the first conductive material 105, the openings 130 can remain in the region 50I between the first nanostructures 52. In other embodiments, the first conductive material 105 can completely fill the remaining portion of the region 50I.

[0134] Although not specifically shown, the fluorine treatment can be performed without forming the protective material 140. For example, the first conductive material 105 can be formed on the second gate dielectric layer 103 prior to performing the fluorine treatment. Thereafter, to perform the fluorine treatment, a fluorine-containing layer 144 is formed (e.g., using a deposition process or a dip process) over the first conductive material 105, and the anneal process 200 is performed to diffuse fluorine from the fluorine-containing layer 144 through the first conductive material 105 to the gate dielectric layer 100, as described above. A subsequent etch process (e.g., as described above) can be used to remove the fluorine-containing layer 144 while the first conductive material 105 remains intact. In some embodiments, the etch process can continue beyond the fluorine-containing layer 144 to remove a portion of the first conductive material 105, e.g., to reduce the first conductive material 105 to a desired thickness.

[0135] In other embodiments, the second gate dielectric layer 103 is subjected to the fluorine treatment without first forming the protective material 140 or the first conductive material 105. For example, the fluorine-containing layer 144 can be formed using a deposition process or a dip process. However, in the absence of the protective material 140, the fluorine-containing precursor used to form the fluorine-containing layer 144 can etch the second gate dielectric layer 103 by up to about 2 angstroms. As a result, the fluorine-containing layer 144 will be deposited over the second gate dielectric layer 103 using a deposition process, while the upper portion of the second gate dielectric layer 103 will be converted to the fluorine-containing layer 144 using a dip process. The anneal process 200 is then performed to diffuse fluorine from the fluorine-containing layer 144 directly into the gate dielectric layer 100. Thus, the anneal process 200 can be performed under more moderate conditions, e.g., at a temperature between about 150 °C and about 700 °C, at a pressure between about 0.1 Torr and about 50 Torr, and for a duration between about 0.1 seconds and about 60 minutes. After the anneal process 200, the fluorine-containing layer 144 is removed (e.g., in the manner described above) to expose the second gate dielectric layer 103.

[0136] InFIG. 23A and FIG. 23B In this process, a second conductive material 107 is conformally deposited on a first conductive material 105. In some embodiments, the second conductive material 107 is a p-type WFM including titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, etc. The second conductive material 107 can be deposited by CVD, ALD, PECVD, PVD, etc.

[0137] The second conductive material 107 may fill any remaining portion of the region 50I between the first nanostructures 52 (e.g., fill the opening 130). For example, the second conductive material 107 may be deposited on the first conductive material 105 until they are joined and seamed together, and in some embodiments, an interface 107S may be formed by the first portion 107A (e.g., conductive material 107A) of the second conductive material 107 contacting the second portion 107B (e.g., conductive material 107B) of the second conductive material 107 in the region 50I.

[0138] exist FIG. 24A and FIG. 24B In this process, the adhesive layer 117 is conformally deposited over the second conductive material 107. In some embodiments, the adhesive layer 117 is conformally deposited on the second conductive material 107 in the p-type region 50P. In some embodiments, the adhesive layer 117 includes titanium nitride, tantalum nitride, etc. The adhesive layer 117 can be deposited by CVD, ALD, PECVD, PVD, etc. For example, the adhesive layer 117 can alternatively be called an adhesive layer and improve the adhesion between the second conductive material 107 and the overlying filler metal 119.

[0139] exist FIGS. 25A-25D In this process, the remaining portion of the gate electrode 102 is deposited to fill the remaining portion of the second groove 98. For example, filler metal 119 may be deposited over the adhesive layer 117. In some embodiments, filler metal 119 comprises cobalt, ruthenium, aluminum, tungsten, and combinations thereof, and is deposited by CVD, ALD, PECVD, PVD, etc. The resulting gate electrode 102 is used to replace the gate electrode and may include a first conductive material 105, a second conductive material 107, adhesive layer 117, and filler metal 119. FIG. 25C It shows along FIG. 25B (For example, in region 50I) a top view of line X-X', while FIG. 25D It shows along FIG. 25B A top view of a line Y-Y' (e.g., via one of the first nanostructures 52).

[0140] In the p-type region 50P, the gate dielectric layer 100, the first conductive material 105, the second conductive material 107, the adhesive layer 117, and the fill metal 119 can each be formed on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100, the first conductive material 105, the second conductive material 107, the adhesive layer 117, and the fill metal 119 can also be deposited on the top surfaces of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68. After filling the second trench 98, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100, the first conductive material 105, the second conductive material 107, the adhesive layer 117, and the fill metal 119 above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus forms the alternative gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0141] FIG. 26A and FIG. 26B A gate stack in an n-type region 50N is illustrated. Forming a gate stack in the n-type region 50N may include first removing a first nanostructure 52 in the n-type region 50N. The first nanostructure 52 may be removed by forming a mask (not shown) over a p-type region 50P and performing an isotropic etching process (such as wet etching) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructures 52A-52C comprise, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., may be used to remove the first nanostructure 52 in the n-type region 50N.

[0142] A gate stack is then formed over and around the second nanostructure 54 in the n-type region 50N. The gate stack includes a gate dielectric layer 100 and a gate electrode 127. In some embodiments, the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can be formed simultaneously, and the fluorine treatment can also be performed simultaneously. Furthermore, at least a portion of the gate electrode 127 can be formed before or after the formation of the gate electrode 102 (e.g., while masking the p-type region 50P) (see [link to documentation]). FIGS. 25A-25D). Thus, the gate electrode 127 can include different materials than the gate electrode 102. For example, the gate electrode 127 can include a third conductive material 121, a barrier layer 123, and a fill metal 125. The third conductive material 121 can be an n-type WFM layer including an n-type metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. The third conductive material 121 can be deposited by CVD, ALD, PECVD, PVD, and the like. The barrier layer 123 can include titanium nitride, tantalum nitride, tungsten carbide, combinations thereof, and the like, and the barrier layer 123 can further function as an adhesion layer. The barrier layer 123 can be deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 125 can include cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like, deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 125 can or can not have the same material composition and be deposited concurrently with the fill metal 119.

[0143] Although not specifically shown, fluorine treatment can be performed in the n-type region 50N without forming the protective material 140, similar to the description above for the p-type region 50P. For example, the third conductive material 121 can be formed on the second gate dielectric layer 103 prior to performing the fluorine treatment. Thereafter, the fluorine-containing layer 144 is formed, the anneal process 200 is performed, and the fluorine-containing layer 144 is removed, while the third conductive material 121 remains intact. In another embodiment, the first conductive material 105 (rather than the third conductive material 121) is formed in both the n-type region 50N and the p-type region 50P prior to performing the fluorine treatment. The fluorine treatment can then be performed in both regions simultaneously. The first conductive material 105 can also be removed or can at least partially remain intact during the removal of the fluorine-containing layer 144 in the n-type region 50N. The third conductive material 121 and the remaining portions of the gate electrode 127 can then be formed over the structure.

[0144] In other embodiments, the fluorine treatment can be performed on the second gate dielectric layer 103 without first forming the protective material 140, the first conductive material 105, or the third conductive material 121, similar to the description above for the p-type region 50P. After the fluorine treatment and removal of the fluorine-containing layer 144, the third conductive material 121 can be formed on the second gate dielectric layer 103.

[0145] According to some embodiments, the gate dielectric layer 100 in the n-type region 50N can be formed concurrently with the gate dielectric layer 100 in the p-type region. The fluorine treatment (e.g., deposition of the protective material 140, formation of the fluorine-containing layer 144, performance of the anneal process, and removal of the fluorine-containing layer 144 and the protective material 140) can also be performed concurrently in both regions. After the fluorine treatment, portions of the gate stack can be continuous in both regions, or one of the regions can be masked while the remaining gate stack is formed in the other region, as described above.

[0146] According to other embodiments, the fluorine treatment can be performed separately, for example, when the gate dielectric layers 100 in the regions (e.g., p-type region 50P and n-type region 50N) are formed separately or when the gate dielectric layers 100 will have different compositions or specifications. For example, the gate dielectric layers 100 can be formed in each region simultaneously, then one of the regions is masked for the fluorine treatment, and the gate stack for the other region is completed. Any suitable combination of these methods can be utilized to form some or all of the gate stack in each region, and all such combinations are fully included within the scope of embodiments.

[0147] Still referring to FIG. 26A and FIG. 26B After filling the second recess 98 in the n-type region 50N, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 127 that are above the top surface of the first ILD 96. Thus, the remaining portions of the material of the gate electrode 127 and the gate dielectric layer 100 form the replacement gate structure for the resulting nanosheet FET of the n-type region 50N. The CMP process to remove excess material of the gate electrode 102 in the p-type region 50P and the gate electrode 127 in the n-type region 50N can be performed simultaneously or separately.

[0148] In FIGS. 27A-27C the gate structures (e.g., gate electrode 102 and gate electrode 127) are recessed such that a recess is formed between the direct overhang of the gate structures and the opposing portions of the first spacers 81. A cap 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material that extend over the first ILD 96. The resulting gate contact, such as gate contact 114, discussed below with respect to FIGS. 29A-29C , penetrates through the gate cap 104 to contact the top surface of the recessed gate electrode 102 / 127.

[0149] As FIGS. 27A-27C further shown, a second ILD 106 is deposited over the first ILD 96 and over the gate cap 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed from a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0150] In FIGS. 28A-28CIn the process, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 that exposes the epitaxial source / drain regions 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the third recess 108 can be etched via the second ILD 106 and the first ILD 96 using a first etching process; the gate mask 104 can be etched using a second etching process; and then the CESL 94 can be etched using a third etching process. A mask such as a photoresist can be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process may over-etch; therefore, the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be flush with (e.g., at the same level, or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the top surface of the epitaxial source / drain region 92 and / or gate structure. Although FIG. 28B The third groove 108 is illustrated as exposing the epitaxial source / drain region 92 and gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross sections, thereby reducing the risk of subsequent contact short circuits.

[0151] After the third groove 108 is formed, a silicide region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by the following steps: first, depositing a metal (not shown) such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof that can react with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 on the exposed portion of the epitaxial source / drain region 92 to form a silicide or germanide region; then performing a thermal annealing process to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanium region (e.g., a region containing both silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0152] Next, in FIGS. 29A-29CIn this embodiment, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each comprise a barrier layer and a conductive material, and are electrically coupled to conductive features of the underlying layer (e.g., gate electrode 102, gate electrode 127, and / or silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to gate electrodes 102 and 127 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0153] FIGS. 30A-30C A cross-sectional view of an apparatus according to some other embodiments is shown. FIG. 30A It shows FIG. 1 The reference section A-A' is shown. FIG. 30B It shows FIG. 1 The reference section B-B' is shown. FIG. 30C It shows FIG. 1 The reference cross-section C-C' is shown. Similar element symbols denote similar elements formed by similar processes as discussed in the above embodiments, for example... Figures 29A-29C The structure. However, in Figures 30A-30C In this configuration, the channel regions in the n-type region 50N and the p-type region 50P contain the same material. For example, a second nanostructure 54 containing silicon provides a channel region for both the p-type nanoFET in the p-type region 50P and the n-type nanoFET in the n-type region 50N. The structure can be formed, for example, by simultaneously removing a first nanostructure 52 from both the p-type region 50P and the n-type region 50N, depositing a gate dielectric layer 100 and a gate electrode 102 around the second nanostructure 54 in the p-type region 50P, and depositing a gate dielectric layer 100 and a gate electrode 127 around the second nanostructure 54 in the n-type region 50N. Alternatively, the second nanostructure 54 can be removed from both the p-type region 50P and the n-type region 50N, and the first nanostructure 52 can provide a channel region for both the p-type nanoFET in the p-type region 50P and the n-type nanoFET in the n-type region 50N.

[0154] Multiple advantages can be realized. Various embodiments provide a gate stack with a fluorine treated gate dielectric layer to increase yield and improve reliability and mobility related to the gate dielectric layer. In particular, the fluorine treatment diffuses fluorine into the gate dielectric layer to fill vacancies, attach to dangling bonds, and achieve a desired effective oxide thickness. For example, a protective material is first formed over the gate dielectric layer to protect the gate dielectric layer (e.g., a high-k gate dielectric layer) from being etched during a fluorine treatment. The fluorine treatment begins with a deposition process or a soak process to form a fluorine containing layer on the protective material. An anneal process is then performed to drive or diffuse some of the fluorine from the fluorine containing layer through the protective material and into the gate dielectric layer. The fluorine containing layer and the protective material are then removed, and remaining layers of the gate stack (e.g., a gate electrode layer) are formed. In some embodiments, only the fluorine containing layer is completely removed, while all or a portion of the protective material remains to a portion of the gate electrode. Embodiments result in a desired amount of fluorine diffusing into the gate dielectric layer, thereby achieving the benefits of increased yield and improved device performance.

[0155] In some embodiments, a method of fluorine incorporation of a nanosheet includes the steps of: forming a plurality of nanostmctures on a substrate; etching the nanostmctures to form a plurality of recesses; forming a plurality of source / drain regions in the recesses; removing a plurality of first nanostmctures of the nanostmctures, leaving a plurality of second nanostmctures of the nanostmctures; depositing a gate dielectric layer over and around the second nanostmctures; depositing a protective material on the gate dielectric layer; fluorine treating the protective material; removing the protective material; depositing a first conductive material on the gate dielectric layer; and depositing a second conductive material on the first conductive material. In another embodiment, the step of fluorine treating includes the step of: forming a fluorine containing layer over the protective material. In another embodiment, the step of forming a fluorine containing layer on the protective material includes the step of: converting an upper portion of the protective material into the fluorine containing layer. In another embodiment, the step of fluorine treating further includes the step of: performing an anneal process on the fluorine containing layer. In another embodiment, the step of performing an anneal process includes the step of: diffusing fluorine from the fluorine containing layer into the gate dielectric layer. In another embodiment, the method further includes the step of: removing the fluorine containing layer. In another embodiment, the fluorine containing layer further includes tungsten. In another embodiment, the step of fluorine treating includes the step of: filling a plurality of vacancies in the gate dielectric layer with fluorine.

[0156] In some embodiments, a method of fluorine incorporation for nanosheets includes the steps of: forming a plurality of nanostructures on a substrate; forming a first dielectric layer over the substrate and around the nanostructures; forming a second dielectric layer over the first dielectric layer; depositing a first conductive material over the second dielectric layer; forming a fluorine-containing layer over the first conductive material; diffusing fluorine from the fluorine-containing layer into the second dielectric layer, wherein the step of diffusing fluorine changes a breakdown voltage of the first and second dielectric layers; removing the fluorine-containing layer; and forming a second conductive material over the second dielectric layer. In another embodiment, the step of removing the fluorine-containing layer includes the step of: removing a portion of the first conductive material. In another embodiment, the first conductive material is removed prior to forming the second conductive material. In another embodiment, the second conductive material is further formed over the first conductive material. In another embodiment, the first conductive material includes at least one of titanium nitride, tantalum nitride, and titanium silicon nitride. In another embodiment, the step of diffusing fluorine includes the step of: performing an anneal process, and wherein after the step of diffusing fluorine, the second dielectric layer includes a fluorine-to-metal atomic ratio between 0.005 and 0.05. In another embodiment, the step of diffusing fluorine further includes the step of: diffusing fluorine into the first dielectric layer, and wherein a first portion of the fluorine fills a plurality of vacancies in the second dielectric layer, and wherein a second portion of the fluorine adheres to a plurality of silicon dangling bonds at an interface between the substrate and the first dielectric layer.

[0157] In some embodiments, a method of fluorine incorporation for nanosheets includes the steps of: forming a plurality of first nanostructures and a plurality of second nanostructures on a substrate; removing the first nanostructures; forming a first gate dielectric layer around the second nanostructures; tuning a breakdown voltage of the first gate dielectric layer, the step of tuning the breakdown voltage including the steps of: forming a protective material over the first gate dielectric layer; forming a fluorine-containing layer over the protective material; diffusing fluorine from the fluorine-containing layer through the protective material into the first gate dielectric layer; and removing the protective material; and forming a first conductive material over the first gate dielectric layer. In another embodiment, the step of forming the fluorine-containing layer includes the step of: converting an upper portion of the protective material into the fluorine-containing layer. In another embodiment, the fluorine-containing layer further includes tungsten. In another embodiment, the step of diffusing fluorine from the fluorine-containing layer through the protective material includes the step of: performing an anneal process, and wherein the first gate dielectric layer includes a fluorine-to-metal atomic ratio between 0.05 and 0.005. In another embodiment, the method further includes the steps of: forming a second gate dielectric layer around the second nanostructures prior to forming the first gate dielectric layer; and diffusing fluorine from the fluorine-containing layer through the protective material, through the first gate dielectric layer, into the second gate dielectric layer.

[0158] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A method for fluorine doping of nanosheets, characterized in that, Includes the following steps: Multiple nanostructures are formed on a substrate; Etch these nanostructures to form multiple grooves; Multiple source / drain regions are formed in these grooves; Remove multiple first nanostructures from these nanostructures, leaving multiple second nanostructures of these nanostructures; A gate dielectric layer is deposited on and around these second nanostructures; A protective material comprising a metal is deposited on the gate dielectric layer to protect the gate dielectric layer; the protective material is then subjected to a fluorine treatment. Remove the protective material; A first conductive material is deposited on the gate dielectric layer; and A second conductive material is deposited on the first conductive material.

2. The method according to claim 1, characterized in that, The steps of performing the fluorine treatment include the following steps: forming a fluorine-containing layer on top of the protective material, the fluorine-containing layer further comprising tungsten.

3. The method according to claim 2, characterized in that, The step of forming the fluorine-containing layer over the protective material includes the following steps: allowing a fluorine-containing precursor and a reducing agent precursor to flow over the surface of the protective material.

4. The method according to claim 2, characterized in that, The fluorine treatment process further includes the following steps: performing an annealing process on the fluorine-containing layer.

5. The method according to claim 4, characterized in that, The annealing process includes the following steps: diffusing fluorine from the fluorine-containing layer into the gate dielectric layer.

6. The method according to claim 2, characterized in that, The process further includes the following steps: removing the fluorine-containing layer.

7. The method according to claim 1, characterized in that, The steps of performing this fluorine treatment include the following: converting an upper portion of the protective material into a fluorine-containing layer.

8. The method according to claim 1, characterized in that, The steps of performing this fluorine treatment include the following steps: filling multiple vacancies in the gate dielectric layer with fluorine.

9. A method for fluorine doping of nanosheets, characterized in that, Includes the following steps: Multiple nanostructures are formed on a substrate; A first dielectric layer is formed above the substrate and around the nanostructures; A second dielectric layer is formed above the first dielectric layer; A first conductive material is deposited on top of the second dielectric layer; A fluorine-containing layer is formed on top of the first conductive material; Fluorine is diffused from the fluorine-containing layer to the second dielectric layer, wherein the fluorine diffusion step changes the breakdown voltage of the first dielectric layer and the second dielectric layer; Removing the fluorine-containing layer, wherein the step of removing the fluorine-containing layer includes the following steps: removing a portion of the first conductive material; and A second conductive material is formed on top of the second dielectric layer.

10. The method according to claim 9, characterized in that, The fluorine-containing layer is formed using a deposition process or an immersion process.

11. The method according to claim 9, characterized in that, The first conductive material is removed before the second conductive material is formed.

12. The method according to claim 9, characterized in that, The second conductive material is further formed on top of the first conductive material.

13. The method according to claim 9, characterized in that, The first conductive material comprises at least one of titanium nitride, tantalum nitride, and silicon titanium nitride.

14. The method according to claim 9, characterized in that, The diffusion of fluorine includes the following steps: performing an annealing process, wherein after the diffusion of fluorine, the second dielectric layer comprises a fluorine-metal atomic ratio between 0.005 and 0.

05.

15. The method according to claim 9, characterized in that, The fluorine diffusion step further includes the following steps: diffusing fluorine into the first dielectric layer, wherein a first portion of the fluorine fills a plurality of vacancies in the second dielectric layer, and wherein a second portion of the fluorine is attached to a plurality of silicon dangling bonds at the interface between the substrate and the first dielectric layer.

16. A method for fluorine doping of nanosheets, characterized in that, Includes the following steps: Multiple first nanostructures and multiple second nanostructures are formed on a substrate; Remove these first nanostructures; A first gate dielectric layer is formed around these second nanostructures; Tuning a breakdown voltage of the first gate dielectric layer, the step of tuning the breakdown voltage includes the following steps: A protective material comprising a metal nitride is formed above the first gate dielectric layer. A fluorine-containing layer is formed on top of the protective material; Fluorine diffuses from the fluorine-containing layer through the protective material into the first gate dielectric layer; and Remove the protective material; and A first conductive material is formed above the first gate dielectric layer.

17. The method according to claim 16, characterized in that, The steps of forming the fluorinated layer include the following steps: converting the upper portion of the protective material into the fluorinated layer.

18. The method according to claim 16, characterized in that, The fluorine-containing layer further contains tungsten.

19. The method according to claim 16, characterized in that, The step of diffusing fluorine from the fluorine-containing layer through the protective material includes the following steps: performing an annealing process, wherein the first gate dielectric layer has a fluorine-metal atomic ratio between 0.05 and 0.

005.

20. The method according to claim 19, characterized in that, Further steps include: Before forming the first gate dielectric layer, a second gate dielectric layer is formed around the second nanostructures; and Fluorine diffuses from the fluorine-containing layer through the protective material, through the first gate dielectric layer, and into the second gate dielectric layer.

Images