A method for preparing a high electron mobility transistor

Abstract

The present application provides a method for fabricating a high electron mobility transistor, which relates to the field of semiconductor technology. The method includes: preparing a prefabricated structure, the prefabricated structure including a substrate and a heterojunction on the substrate, and the first surface of the heterojunction having a plurality of V-shaped pits; annealing in a preset atmosphere to expand the V-shaped pits to form a plurality of pits distributed on the first surface of the heterojunction. Since a plurality of pits with different depths are formed on the first surface of the heterojunction, when the gate metal is evaporated on the first surface, correspondingly, the bottom of the gate metal will be filled in the plurality of pits with different depths distributed in the gate region. Thus, the distances from different regions under the same gate metal to the two-dimensional electron gas are different, so that different regions under the gate have different turn-off voltages, thereby achieving the flattening of the transconductance and improving the linearity of the high electron mobility transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a method for fabricating a high electron mobility transistor. Background Art

[0002] GaN materials have advantages such as a large bandgap width, a high breakdown electric field, a high thermal conductivity, a high electron saturation velocity, and a high radiation resistance, and have broad application prospects in high-temperature, high-frequency, and high-power microwave semiconductor devices. They are the forefront and hotspots of global semiconductor research. GaN high electron mobility transistor devices are planar lateral devices, and device fabrication is achieved by depositing source, drain, and gate metals and various passivation layers on the surface-flat GaN high electron mobility transistor epitaxial material to form a three-terminal device.

[0003] In the actual application process of traditional GaN high electron mobility transistor devices, the device transconductance (Gm) decreases as the gate voltage (Vgs) increases, corresponding to a decrease in device gain; the non-linearity caused by the decrease in transconductance will lead to premature saturation of the output power, signal distortion, etc., affecting the characteristics of the system and increasing the complexity of system design. Summary of the Invention

[0004] The purpose of this application is to provide a method for fabricating a high electron mobility transistor to achieve the flattening of transconductance and improve the linearity of the high electron mobility transistor in view of the deficiencies in the above-mentioned prior art.

[0005] To achieve the above objective, the technical solutions adopted in the embodiments of this application are as follows:

[0006] On the one hand, an embodiment of this application provides a method for fabricating a high electron mobility transistor, the method including: preparing a prefabricated structure, the prefabricated structure including a substrate and a heterojunction formed on the substrate, the heterojunction having a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate; annealing the prefabricated structure in a preset atmosphere to expand the V-shaped pits to form a plurality of pits distributed on the first surface of the heterojunction; forming a source metal, a drain metal, and a gate metal on the first surface of the heterojunction, wherein the gate metal fills the pits.

[0007] Optionally, the preset atmosphere is an H2 atmosphere, an N2 atmosphere, or a mixed atmosphere of H2 and N2.

[0008] Optionally, annealing the prefabricated structure in the preset atmosphere includes: annealing the prefabricated structure in situ in an H2 atmosphere for 5 min to 20 min, the annealing temperature being 900 °C to 1200 °C, the chamber pressure being 50 mbar to 500 mbar, and the gas flow rate of the preset atmosphere being 1 SLM to 100 SLM.

[0009] Optionally, annealing the prefabricated structure in a preset atmosphere includes: annealing the prefabricated structure in-situ in an N2 atmosphere for 10 min to 30 min, with an annealing temperature of 900 °C to 1200 °C, a chamber pressure of 50 mbar to 500 mbar, and a gas flow rate of the N2 atmosphere of 1 SLM to 100 SLM.

[0010] Optionally, annealing the prefabricated structure in a preset atmosphere includes: annealing the prefabricated structure in-situ in a mixed atmosphere of H2 and N2 for 10 min to 30 min, with an annealing temperature of 900 °C to 1200 °C, a chamber pressure of 50 mbar to 500 mbar, a gas flow rate of the mixed atmosphere of H2 and N2 of 1 SLM to 100 SLM, and a mixing ratio of H2 and N2 of 0 to 1.

[0011] Optionally, the heterojunction includes a channel layer and a barrier layer formed in sequence on a substrate. One side of the barrier layer facing away from the substrate is a first surface, and the depth of the pit is less than the thickness of the barrier layer.

[0012] Optionally, the prefabricated structure further includes an insertion layer formed between the channel layer and the barrier layer.

[0013] Optionally, the prefabricated structure further includes a nucleation layer and a buffer layer formed in sequence between the substrate and the heterojunction.

[0014] Optionally, the depth of the pit is 10 nm to 12 nm.

[0015] Optionally, the annealing time is positively correlated with the depth of the pit.

[0016] The beneficial effects of this application include:

[0017] This application provides a method for fabricating a high electron mobility transistor. The method includes: preparing a prefabricated structure, where the prefabricated structure includes a substrate and a heterojunction formed on the substrate, and the heterojunction has a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate; annealing the prefabricated structure in a preset atmosphere to expand the V-shaped pits to form a plurality of pits distributed on the first surface of the heterojunction; forming source metal, drain metal, and gate metal on the first surface of the heterojunction, where the gate metal fills the pits. Since a plurality of pits with different depths are formed on the first surface of the heterojunction, at least some of the plurality of pits are distributed in the gate region. Then, when depositing the gate metal on the first surface, correspondingly, the bottom of the gate metal will fill into the plurality of pits with different depths distributed in the gate region. Thus, the distances from different regions under the same gate metal to the two-dimensional electron gas are different. Therefore, the voltages required to deplete the two-dimensional electron gas are different, so that different regions under the gate have different turn-off voltages, thereby achieving the flattening of the transconductance and improving the linearity of the high electron mobility transistor. Description of the Drawings

[0018] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0019] Figure 1 Schematic flow chart of a method for manufacturing a high electron mobility transistor provided by an embodiment of the present application;

[0020] Figure 2 One of the state diagrams of a method for manufacturing a high electron mobility transistor provided by an embodiment of the present application;

[0021] Figure 3 Another state diagram of a method for manufacturing a high electron mobility transistor provided by an embodiment of the present application;

[0022] Figure 4 Another state diagram of a method for manufacturing a high electron mobility transistor provided by an embodiment of the present application;

[0023] Figure 5 One of the structural diagrams of a high electron mobility transistor provided by an embodiment of the present application;

[0024] Figure 6 Another structural diagram of a high electron mobility transistor provided by an embodiment of the present application;

[0025] Figure 7 Schematic diagram of the transconductance and gate voltage of a high electron mobility transistor provided by an embodiment of the present application;

[0026] Figure 8 Another structural diagram of a high electron mobility transistor provided by an embodiment of the present application.

[0027] Icons: 100 - Heterojunction; 110 - First surface; 111 - V-shaped pit; 112 - Pit; 120 - Source metal; 130 - Drain metal; 140 - Gate metal; 150 - Barrier layer; 160 - Channel layer; 170 - Substrate; 180 - Nucleation layer; 190 - Buffer layer; 200 - Insertion layer. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. Components of the embodiments of this application that are usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0029] It should be understood that although terms such as first and second may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extend onto another element, or there may also be intermediate elements. In contrast, when an element is referred to as "directly on another element" or "directly extending onto another element", there are no intermediate elements. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "above another element" or "extending above another element", it can be directly above another element or directly extend above another element, or there may also be intermediate elements. In contrast, when an element is referred to as "directly above another element" or "directly extending above another element", there are no intermediate elements. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0031] Unless otherwise defined, the meanings of all terms (including technical and scientific terms) used herein are the same as those commonly understood by those of ordinary skill in the art to which this disclosure belongs. It should also be understood that the terms used herein should be interpreted as having meanings consistent with their meanings in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless clearly defined as such herein.

[0032] On the one hand, an embodiment of this application provides a method for manufacturing a high electron mobility transistor, as Figure 1 shown, the method includes:

[0033] S010: Prepare a prefabricated structure, where the prefabricated structure includes a substrate and a heterojunction formed on the substrate. The heterojunction has a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate.

[0034] Provide a substrate 170, which can be a SiC, sapphire or Si substrate 170, and the present application does not limit it.

[0035] As Figure 2 shown, then epitaxially grow a heterojunction 100 on the substrate 170 to obtain a prefabricated structure. The heterojunction 100 has a two-dimensional electron gas at the heterointerface. As Figure 5 shown, the heterojunction 100 may include a channel layer 160 and a barrier layer 150. During the epitaxial growth process of the heterojunction 100, a large number of threading dislocations exist inside the heterojunction 100. For the first surface 110 of the heterojunction 100 facing away from the substrate 170, a part of the threading dislocations will emerge on the first surface 110, resulting in the formation of a plurality of tiny V-shaped pits 111 on the first surface 110. The plurality of V-shaped pits 111 are randomly distributed on the first surface 110 of the heterojunction 100.

[0036] S020: Anneal the prefabricated structure in a preset atmosphere to expand the V-shaped pits to form a plurality of pits distributed on the first surface of the heterojunction.

[0037] As Figure 3 shown, after obtaining the prefabricated structure by epitaxial growth through S010, the prefabricated structure is annealed in a preset atmosphere. Since there are a plurality of tiny V-shaped pits 111 on the first surface 110 of the heterojunction 100, the semi-polar plane of the heterojunction 100 material will be correspondingly exposed. During the annealing process, the semi-polar plane will be decomposed and etched in the high-temperature preset atmosphere. Therefore, the plurality of V-shaped pits 111 where the dislocations emerge on the first surface 110 will be expanded after annealing, and then a plurality of pits 112 with different depths will be formed on the first surface 110 of the heterojunction 100.

[0038] S030: Form a source metal, a drain metal and a gate metal on the first surface of the heterojunction, where the gate metal fills the pits.

[0039] The first surface 110 of the heterojunction 100 may have a source region, a drain region and a gate region, where the gate region is located between the source region and the drain region. As Figure 4 and Figure 5 shown, on the first surface 110 of the heterojunction 100, a source metal 120 located in the source region, a drain metal 130 located in the drain region and a gate metal 140 located in the gate region are formed through processes such as photolithography, evaporation and stripping.

[0040] Since a plurality of pits 112 with different depths are formed on the first surface 110 of the heterojunction 100 by S020, at least part of the plurality of pits 112 are distributed in the gate region. Then, as Figure 6 shown, when the gate metal 140 is evaporated on the first surface 110, correspondingly, the bottom of the gate metal 140 will be filled in the plurality of pits 112 with different depths distributed in the gate region. Thus, the distances from different regions under the same gate metal 140 to the two-dimensional electron gas are different. Therefore, the voltages required to deplete the two-dimensional electron gas are different, so that different regions under the gate have different turn-off voltages, thereby realizing the flattening of the transconductance, improving the linearity of the high electron mobility transistor, and reducing the adverse effects such as premature saturation of the output power and signal distortion caused by the device non-linearity.

[0041] Please refer to Figure Figure 6 (only part of the pits 112 are shown in the figure). After the gate metal 140 is evaporated and formed on the first surface 110 of the heterojunction 100, the bottom of the gate metal 140 will correspondingly fill a part of the pits 112 with different depths. For example, in the gate width direction, there are a plurality of pits 112 with different depths filled by the bottom of the gate metal 140. Thus, the distances from different regions under the same gate metal 140 to the two-dimensional electron gas are different. Combining Figure 7 shown, the voltages required to deplete the two-dimensional electron gas are different, so that different regions under the gate have different turn-off voltages, thereby realizing the flattening of the transconductance and improving the linearity of the high electron mobility transistor.

[0042] In some embodiments, the high electron mobility transistor may be a GaN device, and the corresponding heterojunction 100 may be a GaN heterojunction 100, such as AlGaN / GaN, etc. As Figure 5 shown, a MOCVD device (metal organic chemical vapor deposition device) can be used with H2 or N2 as the carrier gas, and TMAl, TMGa, and NH3 as the Al source, Ga source, and N source respectively to epitaxially grow the heterojunction 100 on the substrate 170.

[0043] In some embodiments, after the heterojunction 100 is epitaxially grown on the substrate 170, S020 can be performed in the MOCVD device by in-situ annealing or cooling.

[0044] It should be noted that the depth of the pits 112 can be adjusted by controlling the annealing or cooling time. For example, the annealing time is positively correlated with the depth of the pits 112. In other words, the longer the annealing time, the deeper the depth of the pits 112, and vice versa. When the heterojunction 100 includes a channel layer 160 and a barrier layer 150, the side of the barrier layer 150 facing away from the substrate 170 is the first surface 110, and the depth of the pits 112 should be less than the thickness of the barrier layer 150 to avoid affecting the device function.

[0045] When in-situ annealing or cooling the prefabricated structure through S020, the preset atmosphere can be one of H2 atmosphere, N2 atmosphere, and a mixed atmosphere of H2 and N2. For example, when the preset atmosphere is N2 atmosphere, the expansion of the tiny V-shaped pit 111 can be achieved by the high-temperature decomposition of nitrides; for example, in H2 atmosphere, the size of the V-shaped pit 111 can be effectively enlarged by using the high-temperature decomposition of nitrides and the etching effect of H2 on nitrides. The following will be described through embodiments:

[0046] In one embodiment, when the prefabricated structure is annealed in the preset atmosphere, the prefabricated structure is in-situ annealed in the H2 atmosphere in the chamber of the MOCVD equipment. The annealing time is 5 min to 20 min, the annealing temperature is 900 °C to 1200 °C, the chamber pressure is maintained at 50 mbar to 500 mbar, and the flow rate of H2 is 1 SLM to 100 SLM. Controlling the annealing time can form randomly distributed pits 112 with different depths and a depth less than the thickness of the barrier layer 150 on the first surface 110. For example: the thickness of the barrier layer 150 is 25 nm, the prefabricated structure is annealed in H2 atmosphere, the annealing temperature is 1050 °C, and the annealing time is 10 min. Thus, the depth of the pits 112 formed on the first surface 110 is about 10 nm.

[0047] In one embodiment, when the prefabricated structure is annealed in the preset atmosphere, the prefabricated structure is in-situ annealed in the N2 atmosphere in the chamber of the MOCVD equipment. The annealing time is 10 min to 30 min, the annealing temperature is 900 °C to 1200 °C, the chamber pressure is maintained at 50 mbar to 500 mbar, and the flow rate of N2 is 1 SLM to 100 SLM. For example: the thickness of the barrier layer 150 is 25 nm, the prefabricated structure is annealed in N2 atmosphere, the annealing temperature is 1050 °C, and the annealing time is 20 min. Thus, the depth of the pits 112 formed on the first surface 110 is about 12 nm.

[0048] In one embodiment, when the prefabricated structure is annealed in the preset atmosphere, the prefabricated structure is in-situ annealed in the mixed atmosphere of H2 and N2 in the chamber of the MOCVD equipment. The annealing time is 10 min to 30 min, the annealing temperature is 900 °C to 1200 °C, the chamber pressure is maintained at 50 mbar to 500 mbar, the flow rate of the mixed gas of H2 and N2 is 1 SLM to 100 SLM, and the mixing ratio of H2 and N2 is between 0 and 1. For example: the thickness of the barrier layer 150 is 25 nm, the prefabricated structure is annealed in the mixed atmosphere of H2 and N2, the annealing temperature is 1050 °C, and the annealing time is 14 min. Thus, the depth of the pits 112 formed on the first surface 110 is about 10 nm.

[0049] Please refer to Figure 8, the prefabricated structure further includes an insertion layer 200 formed between the channel layer 160 and the barrier layer 150, a nucleation layer 180 and a buffer layer 190 sequentially formed between the substrate 170 and the heterojunction 100, and a cap layer is formed on the barrier layer 150, so that the device has better performance.

[0050] As Figure 8 shown, the MOCVD equipment can be used with H2 or N2 as the carrier gas, and TMAl, TMGa, and NH3 are used as the Al source, Ga source, and N source respectively to epitaxially grow the nucleation layer 180, buffer layer 190, channel layer 160, insertion layer 200, barrier layer 150, and cap layer on the substrate 170 in sequence. Specifically:

[0051] In one embodiment, the material of the nucleation layer 180 is AlN, its growth temperature is between 1000°C and 1200°C, and the growth pressure is between 50 mbar - 150 mbar. For example, a growth temperature of 1150°C and a growth pressure of 100 mbar are adopted.

[0052] In one embodiment, the material of the buffer layer 190 is GaN, its growth temperature is between 1000°C and 1100°C, and the growth pressure is between 100 mbar - 500 mbar. For example, a growth temperature of 1080°C and a growth pressure of 300 mbar are adopted. The GaN buffer layer 190 is a high-resistance buffer layer 190, and the high-resistance implementation method is to introduce a C source or an Fe source as a doping source.

[0053] In one embodiment, the material of the channel layer 160 is GaN, its growth temperature is between 1000°C and 1100°C, and the growth pressure is between 100 mbar - 500 mbar. For example, a growth temperature of 1080°C and a growth pressure of 500 mbar are adopted. The channel layer 160 is an unintentionally doped GaN layer, and the C impurity concentration < 1E16 atoms / cm 3 .

[0054] In one embodiment, the material of the insertion layer 200 is AlN, its growth temperature is between 1000°C and 1100°C, and the growth pressure is between 50 mbar - 200 mbar. For example, a growth temperature of 1080°C and a growth pressure of 100 mbar are adopted.

[0055] In one embodiment, the material of the barrier layer 150 is one or a combination of several of AlGaN, AlN, or AlInN. When the material of the barrier layer 150 is AlGaN, its growth thickness is 10 nm - 30 nm, its growth temperature is between 1000°C and 1100°C, and the growth pressure is between 50 mbar - 200 mbar. For example, a growth temperature of 1080°C and a growth pressure of 100 mbar are adopted.

[0056] In one embodiment, the material of the cap layer is GaN, with a growth thickness of 1 nm to 10 nm, a growth temperature of 1000 °C to 1100 °C, and a growth pressure of 50 mbar to 200 mbar. For example, the growth thickness is 2 nm, the growth temperature is 1080 °C, and the growth pressure is 100 mbar.

[0057] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for fabricating a high electron mobility transistor, characterized in that, The method includes: Preparing a prefabricated structure, which includes a substrate and a heterojunction formed on the substrate. The heterojunction has a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate; Annealing the prefabricated structure in a preset atmosphere to expand the V-shaped pits to form a plurality of pits distributed on the first surface of the heterojunction; Forming a source metal, a drain metal, and a gate metal on the first surface of the heterojunction, wherein the gate metal fills the pits.

2. The method for manufacturing a high electron mobility transistor according to claim 1, wherein, The preset atmosphere is an H2 atmosphere, an N2 atmosphere, or a mixed atmosphere of H2 and N2.

3. The method for manufacturing a high electron mobility transistor according to claim 2, wherein Annealing the prefabricated structure in a preset atmosphere includes: In-situ annealing the prefabricated structure in an H2 atmosphere for 5 min to 20 min, with an annealing temperature of 900 °C to 1200 °C, a chamber pressure of 50 mbar to 500 mbar, and a gas flow rate of the preset atmosphere of 1 SLM to 100 SLM.

4. The method for manufacturing a high electron mobility transistor according to claim 2, characterized in that, Annealing the prefabricated structure in a preset atmosphere includes: In-situ annealing the prefabricated structure in an N2 atmosphere for 10 min to 30 min, with an annealing temperature of 900 °C to 1200 °C, a chamber pressure of 50 mbar to 500 mbar, and a gas flow rate of the N2 atmosphere of 1 SLM to 100 SLM.

5. The method for manufacturing a high electron mobility transistor according to claim 2, wherein, Annealing the prefabricated structure in a preset atmosphere includes: In-situ annealing the prefabricated structure in a mixed atmosphere of H2 and N2 for 10 min to 30 min, with an annealing temperature of 900 °C to 1200 °C, a chamber pressure of 50 mbar to 500 mbar, a gas flow rate of the mixed atmosphere of H2 and N2 of 1 SLM to 100 SLM, and a mixing ratio of H2 and N2 of 0 to 1.

6. The method for manufacturing a high electron mobility transistor according to any one of claims 1 to 5, characterized in that, The heterojunction includes a channel layer and a barrier layer formed in sequence on the substrate. One side of the barrier layer facing away from the substrate is the first surface, and the depth of the pits is less than the thickness of the barrier layer.

7. The method for manufacturing a high electron mobility transistor according to claim 6, characterized in that, The prefabricated structure further includes an insertion layer formed between the channel layer and the barrier layer.

8. The method for manufacturing a high electron mobility transistor according to claim 1, wherein The prefabricated structure further includes a nucleation layer and a buffer layer formed in sequence between the substrate and the heterojunction.

9. The method for manufacturing a high electron mobility transistor according to claim 1, characterized in that, The depth of the pits is 10 nm to 12 nm.

10. The method for manufacturing a high electron mobility transistor according to claim 1, wherein The annealing time is positively correlated with the depth of the pits.

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