SiC trench-gate IGBT device with low electromagnetic interference noise and preparation method thereof

Abstract

The present invention provides a SiC trench-gate IGBT device with low electromagnetic interference noise and a manufacturing method thereof, belonging to the technical field of power semiconductor devices. It is mainly used to improve the control ability of the gate resistance over the IGBT turn-on process, reduce the device voltage mutation dV / dt and current mutation dI / dt noise, without increasing the production cost of the device, adding extra process flows, or sacrificing other device performances. Compared with the traditional trench-gate SiC IGBT cell structure, the novel SiC cell structure of the present invention covers an oxide layer and a polysilicon gate on part of the P+ ohmic contact region and the N+ source region, and without affecting the Miller capacitance C GC on the premise, increases the gate-to-emitter parasitic oxide layer capacitance C GE of the device, effectively suppresses the gate self-charging effect, realizes low loss and low electromagnetic interference noise during the IGBT turn-on process, reduces the conduction interference and radiation interference generated by the IGBT module, and enhances the operation reliability of the power system.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and particularly relates to a SiC trench-gate IGBT device with low electromagnetic interference noise. Background Art

[0002] As one of the representatives of the third-generation wide bandgap semiconductor materials, silicon carbide (SiC) material has a wider bandgap width (3 times), higher critical electric field (10 times), higher carrier saturation drift velocity (2 times), higher thermal conductivity (2.5 times), etc. than silicon material. It is an excellent material for preparing high-voltage power electronic devices and has broad application prospects in the fields of high-power, high-temperature, high-voltage and radiation-resistant power electronics.

[0003] The SiC IGBT device with conductivity modulation effect integrates the advantages of high controllability of the MOS field-controlled structure and large on-state current capacity of the bipolar structure, and has the characteristics of low on-state loss, high blocking voltage, high switching speed and low switching loss. SiC IGBT mainly has planar gate and trench gate types. There is a JFET effect between adjacent P-well regions in the SiC planar gate IGBT, which significantly increases its forward conduction voltage; the conductive channel of the SiC trench gate IGBT is vertical, there is no need to fabricate a conductive channel on the surface, and there is no JFET structure between adjacent P-well regions. Compared with the SiC planar gate IGBT, the cell size is more compact, the channel density and near-surface carrier concentration are higher, the forward conduction voltage drop is lower, and the loss is lower.

[0004] With the increase of the bus voltage and the improvement of the switching frequency, the requirement of the circuit system for low electromagnetic interference (EMI) noise of the trench-gate IGBT is also increasing. During the turn-on process of the trench-gate IGBT, in addition to the gate drive current, the charging current of the gate capacitance also includes the self-charging displacement current generated by the accumulation of non-equilibrium minority carriers near the gate oxide. The larger the self-charging displacement current, the greater the EMI noise (dV CE / dt, dI CE / dt noise and reverse recovery dV KA / dt noise of the freewheeling diode) generated during the turn-on process of the trench-gate IGBT device, and the control ability of the gate resistance R g for the turn-on process of the IGBT gradually weakens.

[0005] In the design of the trench-gate IGBT, one solution is to reduce the rate of non-equilibrium minority carrier accumulation near the gate oxide or reduce the gate-collector capacitance C GC to reduce the self-charging displacement current, thereby achieving the purpose of suppressing EMI noise. However, this solution may lead to the degradation of parameters such as the forward conduction voltage drop of the device; another solution is to keep the gate-collector capacitance C GC unchanged and increase the gate-emitter capacitance CGE achieve the purpose of suppressing EMI noise, but the existing device structures for reducing the C GC and C GE ratio require complex process procedures to implement.

[0006] Therefore, there is an urgent need for a SiC trench-gate IGBT device structure that can increase the gate-emitter capacitance C GE of the device without increasing the production cost of the device, without adding additional process procedures, and without sacrificing other performance of the device, reduce the EMI noise of the SiC trench-gate IGBT device, prevent crosstalk in the circuit, and enhance the reliability during the operation of the power system. Summary of the Invention

[0007] The object of the present invention is to propose a SiC trench-gate IGBT device with low electromagnetic interference noise. By covering an oxide layer and a polysilicon gate on part of the N+ contact region and the P+ contact region, the overlapping area between the gate and the emitter is increased, which serves to increase the C GE capacitance. And because there is a grounded Pbase region under the N+ contact region and the P+ contact, a shielding effect is achieved, and it will not cause an increase in the Miller capacitance C GC . Furthermore, under the premise of not increasing the production cost of the device, not adding additional process procedures, and not sacrificing other performance of the device, the EMI noise of the device is reduced, crosstalk in the circuit is prevented, and the requirements for enhancing the reliability during the operation of the power system are met.

[0008] To achieve the above-mentioned invention object, the technical solution of the present invention is as follows:

[0009] A SiC trench-gate IGBT device with low electromagnetic interference noise, comprising: a P-type substrate 10, an N-type buffer layer 9 located above the P-type substrate, an N-type drift layer 8 located above the N-type buffer layer 9, a charge storage layer CSL7 located above the N-type drift layer 8, a P-type shielding layer Pshield6 located inside the charge storage layer CSL7, a P-type base region Pbase5 located above the charge storage layer CSL7, a P+ contact region 4 and an N+ contact region 3 located above the P-type base region Pbase5, an oxide layer 2 is provided above the P-type shielding layer Pshield6 and at the top of the device, and a polysilicon gate 1 is provided above the oxide layer 2; the polysilicon layer gate 1 and the oxide layer 2 cover part of the top regions of the P+ contact region 3 and the N+ contact region 4; the surfaces of the P+ contact region 3 and the N+ contact region 4 are partially covered by the polysilicon layer gate 1 and the oxide layer 2, the collector 11 is located below the device and forms an ohmic contact with the P-type substrate 10, and the emitter 12 is located above the device and forms an ohmic contact with part of the N+ contact region 3 and the P+ contact region 4.

[0010] As a preferred embodiment, the ratio of the area of the regions on the surfaces of the P+ contact region 3 and the N+ contact region 4 covered by the polysilicon layer gate 1 and the oxide layer 2 to the area of the regions not covered by the polysilicon layer gate 1 and the oxide layer 2 is selected from one of 1:1, 2:1, 1:2, 3:1, 1:3, 4:1, 1:4, 5:1, 1:5. Any ratio greater than zero can be adopted according to the requirements of reducing EMI noise and process capabilities. The larger the covered area, the stronger the ability of the device to reduce EMI noise.

[0011] As a preferred embodiment, the thickness of the oxide layer 2 above the surfaces of the P+ contact region 3 and the N+ contact region 4 and below the polysilicon layer gate 1 is equal to the thickness of the oxide layer 2 in the device body. If the thicknesses are equal, the device process flow is simpler.

[0012] As a preferred embodiment, the thickness of the oxide layer 2 above the surfaces of the P+ contact region 3 and the N+ contact region 4 and below the polysilicon layer gate 1 is not equal to the thickness of the oxide layer 2 in the device body. If the thicknesses are not equal, the capacitance C can be adjusted according to requirements during device design. GE size.

[0013] As a preferred embodiment, the oxide layer 2 is SiO2 or a high-k dielectric.

[0014] As a preferred embodiment, the doping types of each part in the device are changed to the opposite doping types, that is, when the P-type doping becomes N-type doping, the N-type doping becomes P-type doping at the same time.

[0015] As a preferred embodiment, the device material is SiC material.

[0016] The present invention also provides a method for manufacturing a SiC trench-gate IGBT device with low electromagnetic interference noise, including the following steps:

[0017] The first step: Clean the epitaxial wafer, epitaxially grow a charge storage layer CSL on the drift region, and perform planarization; as Figure 3 shown;

[0018] The second step: Using the oxide layer as an implantation barrier, perform ion implantation to form a P-type base region Pbase region, a P+ contact region, and an N+ contact region; as Figure 4 shown;

[0019] The third step: Etch the trench; as Figure 5 shown;

[0020] The fourth step: Perform ion implantation at the bottom of the trench to form a P-type shielding layer Pshield; as Figure 6 shown;

[0021] The fifth step: Generate a gate oxide layer by dry oxidation; as Figure 7 shown;

[0022] Step 6: Deposit polysilicon and perform surface planarization; as shown in Figure 8 shown;

[0023] Step 7: Lithographically pattern the polysilicon and oxide layer; as shown in Figure 9 shown;

[0024] Step 8: Deposit field oxide layer; as shown in Figure 10 shown;

[0025] Step 9: Lithographically pattern vias, deposit metal, and form ohmic contact electrodes. As shown in Figure 11 shown.

[0026] In the described device, the polysilicon serves as the gate, the bottom of the P-type substrate serves as the collector, and the N+ contact region and P+ contact region serve as the emitter.

[0027] Advantages of the present invention: By covering the oxide layer and polysilicon gate on part of the N+ contact region and P+ contact region, the overlapping area between the gate and the emitter is increased, and the C of the device is increased while keeping C unchanged. Without increasing the production cost of the device, adding additional process steps, or sacrificing other performance of the device, the purpose of reducing the EMI noise of the device, reducing the conducted interference and radiation interference generated by the IGBT module, preventing crosstalk in the circuit, and enhancing the reliability during the operation of the power system is achieved. GE while keeping C GC unchanged. Without increasing the production cost of the device, adding additional process steps, or sacrificing other performance of the device, the purpose of reducing the EMI noise of the device, reducing the conducted interference and radiation interference generated by the IGBT module, preventing crosstalk in the circuit, and enhancing the reliability during the operation of the power system is achieved. Description of the Drawings

[0028] Figure 1 is a schematic diagram of the device structure of a conventional SiC trench-gate IGBT;

[0029] Figure 2 is a schematic diagram of the device structure of a SiC trench-gate IGBT with low electromagnetic interference noise proposed by the present invention;

[0030] Figure 3 is the cross-sectional view and top view of the cell after epitaxial growth of the CSL layer in the preparation method of Embodiment 1 of the present invention;

[0031] Figure 4 is the cross-sectional view and top view of the cell after ion implantation to form the Pbase, N+ contact region, and P+ contact region in the preparation method of Embodiment 1 of the present invention;

[0032] Figure 5 is the cross-sectional view and top view of the cell after etching the trench in the preparation method of Embodiment 1 of the present invention;

[0033] Figure 6 is the cross-sectional view and top view of the cell after forming the Pshield region by ion implantation at the bottom of the trench in the preparation method of Embodiment 1 of the present invention;

[0034] Figure 7It is the cross-sectional view and top view of the cell after dry oxidation in the preparation method of Embodiment 1 of the present invention;

[0035] Figure 8 It is the cross-sectional view and top view of the cell after depositing polysilicon and performing surface planarization in the preparation method of Embodiment 1 of the present invention;

[0036] Figure 9 It is the cross-sectional view and top view of the cell after lithographically patterning the polysilicon gate and the oxide layer in the preparation method of Embodiment 1 of the present invention;

[0037] Figure 10 It is the cross-sectional view and top view of the cell after depositing silicon oxide in the preparation method of Embodiment 1 of the present invention;

[0038] Figure 11 It is the cross-sectional view and top view of the cell after lithographically patterning the through holes and depositing metal to form ohmic contacts in the preparation method of Embodiment 1 of the present invention.

[0039] 1 is the polysilicon gate, 2 is the oxide layer, 3 is the N+ contact region, 4 is the P+ contact region, 5 is the P-type base region Pbase, 6 is the P-type shielding layer Pshield, 7 is the charge storage layer CSL, 8 is the N-type drift layer, 9 is the N-type buffer layer, 10 is the P-type substrate, 11 is the collector, and 12 is the emitter. Detailed implementation manners

[0040] The following illustrates the implementation manners of the present invention through specific specific examples. The proposed embodiments are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] As Figure 2 shown, a SiC trench-gate IGBT device with low electromagnetic interference noise in this embodiment

[0042] P-type substrate 10, N-type buffer layer 9 located above the P-type substrate, N-type drift layer 8 located above the N-type buffer layer 9, charge storage layer CSL7 located above the N-type drift layer 8, P-type shielding layer Pshield6 located inside the charge storage layer CSL7, P-type base region Pbase5 located above the charge storage layer CSL7, P+ contact region 4 and N+ contact region 3 located above the P-type base region Pbase5, oxide layer 2 is provided above the P-type shielding layer Pshield6 and at the top of the device; polysilicon gate 1 is provided above the oxide layer 2; the polysilicon layer gate 1 and the oxide layer 2 cover partial regions at the tops of the P+ contact region 3 and the N+ contact region 4; the surfaces of the P+ contact region 3 and the N+ contact region 4 are partially covered by the polysilicon layer gate 1 and the oxide layer 2, collector 11 is located below the device and forms an ohmic contact with the P-type substrate 10, emitter 12 is located above the device and forms an ohmic contact with partial N+ contact region 3 and P+ contact region 4.

[0043] Preferably, the ratio of the area of the regions on the surfaces of the P+ contact region 3 and the N+ contact region 4 covered by the polysilicon layer gate 1 and the oxide layer 2 to the area of the regions not covered by the polysilicon layer gate 1 and the oxide layer 2 is selected from one of 1:1, 2:1, 1:2, 3:1, 1:3, 4:1, 1:4, 5:1, 1:5. Any ratio greater than zero can be adopted according to the requirement of reducing EMI noise and process capabilities. The larger the covered area, the stronger the ability of the device to reduce EMI noise.

[0044] Preferably, the thickness of the oxide layer 2 above the surfaces of the P+ contact region 3 and the N+ contact region 4 and below the polysilicon layer gate 1 is equal to the thickness of the oxide layer 2 inside the device. If the thicknesses are equal, the process flow of the device is more convenient.

[0045] Preferably, the thickness of the oxide layer 2 above the surfaces of the P+ contact region 3 and the N+ contact region 4 and below the polysilicon layer gate 1 is not equal to the thickness of the oxide layer 2 inside the device. If the thicknesses are not equal, the capacitance C can be adjusted according to requirements during device design. GE size.

[0046] The oxide layer 2 is SiO2 or a high-k dielectric.

[0047] In other embodiments, the doping types of each part in the device are correspondingly changed to the opposite doping types, that is, when the P-type doping becomes N-type doping, the N-type doping becomes P-type doping at the same time.

[0048] The device material is SiC material or other semiconductor materials.

[0049] The working principle of the present invention is:

[0050] During the device turn-on process, on the one hand, when the V of the device GE is greater than the threshold voltage V of the device TH, the SiC trench-gate IGBT turns on. At this time, the gate self-charging effect causes V GE to increase rapidly, resulting in a relatively high dI CE / dt. On the other hand, due to the existence of parasitic inductance in the circuit, the dV KA / dt of the freewheeling diode is much higher than the dV CE / dt of the SiC trench-gate IGBT, thereby causing relatively large EMI noise.

[0051] In the present invention, by covering an oxide layer and a polysilicon gate on a partial P+ ohmic contact region and an N+ ohmic contact region, the gate-emitter capacitance C GE of the SiC trench-gate IGBT device is increased, the gate self-charging effect is suppressed, and a relatively large dI CE / dt and dV CE / dt during the turn-on process are avoided, and the EMI noise is reduced. At the same time, since there is a grounded Pbase region under the N+ contact region and the P+ contact, a shielding effect is achieved, and the Miller capacitance C GC will not increase, thereby preventing an increase in the turn-on loss of the device.

[0052] Moreover, in the present invention, the size of the gate-emitter capacitance C GE can be adjusted by changing the area of the oxide layer and the polysilicon gate covered on the P+ ohmic contact region and the N+ ohmic contact region and the thickness of the oxide layer.

[0053] This embodiment also provides a method for manufacturing a SiC trench-gate IGBT device with low electromagnetic interference noise, including the following steps:

[0054] The first step: cleaning the epitaxial wafer, epitaxially growing a charge storage layer CSL on the drift region, and performing planarization;

[0055] The second step: using the oxide layer as an implantation blocking layer, ion-implanting to form a P-type base region Pbase region, a P+ contact region, and an N+ contact region;

[0056] The third step: etching the trench;

[0057] The fourth step: implanting ions at the bottom of the trench to form a P-type shielding layer Pshield;

[0058] The fifth step: dry-oxidizing to generate a gate oxide layer;

[0059] The sixth step: depositing polysilicon and performing surface planarization;

[0060] The seventh step: lithographically patterning the polysilicon and the oxide layer;

[0061] The eighth step: depositing a field oxide layer;

[0062] Step 9: Lithographically pattern vias, deposit metal, and form ohmic contact electrodes.

[0063] The polysilicon of the device serves as the gate, the bottom of the P-type substrate serves as the collector, and the N+ contact region and the P+ contact region serve as the emitter.

Claims

1. A SiC trench-gate IGBT device with low electromagnetic interference noise, characterized in that Including: A P-type substrate (10), an N-type buffer layer (9) located above the P-type substrate, an N-type drift layer (8) located above the N-type buffer layer (9), a charge storage layer CSL (7) located above the N-type drift layer (8), a P-type shielding layer Pshield (6) located inside the charge storage layer CSL (7), a P-type base region Pbase (5) located above the charge storage layer CSL (7), a P+ contact region (4) and an N+ contact region (3) located above the P-type base region Pbase (5); an oxide layer (2) is provided above the P-type shielding layer Pshield (6) and at the top of the device, and a polysilicon gate (1) is provided above the oxide layer (2); the polysilicon layer gate (1) and the oxide layer (2) cover a partial area at the top of the P+ contact region (3) and the N+ contact region (4); the surfaces of the P+ contact region (3) and the N+ contact region (4) are partially covered by the polysilicon layer gate (1) and the oxide layer (2), a collector (11) is located below the device and forms an ohmic contact with the P-type substrate (10), and an emitter (12) is located above the device and forms an ohmic contact with a partial N+ contact region (3) and a P+ contact region (4).

2. The SiC trench-gate IGBT device with low electromagnetic interference noise according to claim 1, characterized in that: The ratio of the area of the regions on the surfaces of the P+ contact region (3) and the N+ contact region (4) covered by the polysilicon layer gate (1) and the oxide layer (2) to the area of the regions not covered by the polysilicon layer gate (1) and the oxide layer (2) is selected from one of 1:1, 2:1, 1:2, 3:1, 1:3, 4:1, 1:4, 5:1, 1:

5.

3. The SiC trench-gate IGBT device with low electromagnetic interference noise according to claim 1, characterized in that: The thickness of the oxide layer (2) above the surfaces of the P+ contact region (3) and the N+ contact region (4) and below the polysilicon layer gate (1) is equal to the thickness of the oxide layer (2) inside the device body.

4. The SiC trench-gate IGBT device with low electromagnetic interference noise according to any one of claims 1 to 3, characterized in that: The oxide layer (2) is SiO2 or a high-K dielectric.

5. The SiC trench-gate IGBT device with low electromagnetic interference noise according to any one of claims 1 to 3, characterized in that: The doping types of each part in the device are correspondingly changed to the opposite doping types, that is, when the P-type doping is changed to N-type doping, the N-type doping is changed to P-type doping at the same time.

6. The SiC trench-gate IGBT device with low electromagnetic interference noise according to any one of claims 1 to 5, characterized in that: The device material is SiC material.

7. A method for manufacturing the SiC trench-gate IGBT device with low electromagnetic interference noise according to any one of claims 1 to 5, characterized in that Including the following steps: The first step: Clean the epitaxial wafer, epitaxially grow a charge storage layer CSL on the drift region, and perform planarization. The second step: Using the oxide layer as an implantation blocking layer, perform ion implantation to form a P-type base region Pbase region, a P+ contact region and an N+ contact region. The third step: Etch trenches. The fourth step: Perform ion implantation at the bottom of the trench to form a P-type shielding layer Pshield. The fifth step: Perform dry oxidation to generate a gate oxide layer. The sixth step: Deposit polysilicon and perform surface planarization. The seventh step: Photolithographically pattern the polysilicon and the oxide layer. The eighth step: Deposit a field oxide layer. The ninth step: Photolithographically pattern vias, deposit metal, and form ohmic contact electrodes.

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