Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a first electrode layer, an active layer, a gate insulating layer and a second electrode layer. The first electrode layer comprises a first metal layer and a second metal layer which is insulated from the first metal layer. The active layer is overlapped on the sidewall of the first electrode layer. Two ends of the active layer are respectively in contact with the first metal layer and the second metal layer. In the plan view direction of the array substrate, the second electrode layer and the first electrode layer are arranged at an angle. The active layer is overlapped on the sidewall of the first electrode layer, and the second electrode layer and the first electrode layer are arranged at an angle, so that the area of the orthographic projection of the active layer in the plan view direction of the array substrate is reduced. Compared with the prior art of preparing the active layer on the plane, the application occupies a smaller area of the light-proof area of the array substrate when preparing the active layer on the inclined plane, thereby increasing the aperture ratio of the array substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel. BACKGROUND

[0002] At present, the display technology is developing towards high resolution, for example, the resolution of mobile phone has reached the level of 1080P (1080x1920), and the resolution of television has reached the level of 4K (4096x2160). With the continuous improvement of resolution, the driving capability of TFT device needs to be continuously improved. Therefore, thin film transistor display devices with high resolution, fast response speed, high brightness, high aperture ratio and other advantages are also more and more concerned.

[0003] In the existing display panel, in order to realize the requirement of high resolution, the number of thin film transistors in unit area of array substrate needs to be increased. However, this will lead to the decrease of aperture ratio of display panel, and further affect the display effect of display panel. SUMMARY

[0004] The present application provides an array substrate, a manufacturing method thereof and a display panel to solve the technical problem of low aperture ratio of the existing display panel.

[0005] To solve the above-mentioned scheme, the technical scheme provided by the present application is as follows:

[0006] The present application provides an array substrate, comprising a first electrode layer, an active layer, a gate insulating layer and a second electrode layer, the first electrode layer comprises a first metal layer and a second metal layer arranged on the first metal layer, the first metal layer and the second metal layer are arranged in insulation, the active layer is overlapped on the side wall of the first electrode layer, both ends of the active layer are in contact with the first metal layer and the second metal layer respectively, the gate insulating layer covers the active layer and the first electrode layer, and the second electrode layer is arranged on the gate insulating layer.

[0007] In the top view direction of the array substrate, the second electrode layer and the first electrode layer are arranged at an angle.

[0008] In the array substrate provided in the embodiment of the present application, the array substrate further comprises a first ohmic contact layer and a second ohmic contact layer, and the first electrode layer is located between the first ohmic contact layer and the second ohmic contact layer.

[0009] Both ends of the active layer are in contact with the first ohmic contact layer and the second ohmic contact layer respectively.

[0010] In the array substrate provided in the embodiments of the present application, the active layer comprises a first active part and a second active part which is arranged apart from the first active part, the first active part comprises a first sub-inclined part which overlaps one sidewall of the first electrode layer, and the second active part comprises a second sub-inclined part which overlaps another sidewall of the first electrode layer.

[0011] In the plan view of the array substrate, the area of the orthographic projection of the first sub-inclined part on the first metal layer is equal to the area of the orthographic projection of the second sub-inclined part on the first metal layer.

[0012] In the array substrate provided in the embodiments of the present application, the array substrate further comprises a barrier layer arranged between the first metal layer and the second metal layer.

[0013] The thickness of the barrier layer is greater than the thickness of the first metal layer or the second metal layer.

[0014] In the array substrate provided in the embodiments of the present application, in the plan view of the array substrate, the height of the first active part or the second active part in the direction perpendicular to the first ohmic contact layer is equal to the sum of the thicknesses of the first electrode layer and the barrier layer.

[0015] In the array substrate provided in the embodiments of the present application, in the plan view of the array substrate, the orthographic projection of the second metal layer on the first metal layer is located in the first metal layer, and the area of the orthographic projection of the second metal layer on the first ohmic contact layer is less than the area of the orthographic projection of the first metal layer on the first ohmic contact layer.

[0016] In the array substrate provided in the embodiments of the present application, in the direction from the gate insulating layer to the active layer, the included angle between the active layer and the first metal layer is greater than or equal to 60 degrees and less than or equal to 90 degrees.

[0017] In the array substrate provided in the embodiments of the present application, the array substrate further comprises an interlayer insulating layer arranged on the second electrode layer and a pixel electrode layer arranged on the interlayer insulating layer, the interlayer insulating layer has a first via hole, and the pixel electrode layer is electrically connected with the second metal layer through the first via hole.

[0018] In the plan view of the array substrate, the orthographic projection of the first via hole on the second metal layer does not coincide with the orthographic projection of the second electrode layer on the second metal layer.

[0019] Correspondingly, the embodiments of the present application further provide a manufacturing method of an array substrate, comprising:

[0020] Forming a first ohmic contact layer and a first electrode layer on a substrate, the first electrode layer comprising a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer and the second metal layer being disposed in insulation;

[0021] Forming a first semiconductor layer on the first ohmic contact layer, the first semiconductor layer being patterned to obtain an active layer, the active layer being overlapped on a sidewall of the first electrode layer, two ends of the active layer being in contact with the first metal layer and the second metal layer respectively;

[0022] Forming a second ohmic contact layer on the second metal layer, two ends of the second ohmic contact layer being electrically connected with the active layer respectively;

[0023] Forming a gate insulating layer, a second electrode layer and an interlayer insulating layer on the substrate in sequence, the interlayer insulating layer having a first via, the first via exposing part of the second metal layer;

[0024] Forming a planarization layer, a common electrode layer, a passivation layer and a pixel electrode layer on the interlayer insulating layer in sequence, the passivation layer having a second via, the first via being located in the second via, the pixel electrode layer being electrically connected with the second metal layer through the second via.

[0025] Correspondingly, the application further provides a display panel comprising the array substrate as any one of the above.

[0026] Beneficial effects: The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a first electrode layer, an active layer, a gate insulating layer and a second electrode layer. The first electrode layer comprises a first metal layer and a second metal layer disposed on the first metal layer. The first metal layer and the second metal layer are disposed in insulation. The active layer is overlapped on a sidewall of the first electrode layer. Two ends of the active layer are in contact with the first metal layer and the second metal layer respectively. The gate insulating layer covers the active layer and the first electrode layer. The second electrode layer is disposed on the gate insulating layer. In the plan view direction of the array substrate, the second electrode layer and the first electrode layer are disposed at an angle. The active layer is overlapped on the sidewall of the first electrode layer. Two ends of the active layer are in contact with the first metal layer and the second metal layer respectively. The second electrode layer and the first electrode layer are disposed at an angle. Therefore, the area of the active layer in the plan view direction of the array substrate is reduced. Compared with the prior art of preparing the active layer on a plane, the active layer is prepared on an inclined plane, and the non-light-transmitting area of the array substrate is smaller, so that the aperture ratio of the array substrate is increased. BRIEF DESCRIPTION OF DRAWINGS

[0027] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0028] Figure 1 A top view of the first electrode layer and the second electrode layer in the array substrate provided by the embodiments of the present application;

[0029] Figure 2 A sectional view of the array substrate provided by the embodiments of the present application along the direction of A-A’; Figure 1

[0030] Figure 3 A sectional view of the array substrate provided by the embodiments of the present application along the direction of B-B’; Figure 1

[0031] Figure 4 A flow chart of the manufacturing method of the array substrate of the present application;

[0032] Figures 5A1 to 5E8 A process chart of the manufacturing method of the array substrate of the present application. DETAILED DESCRIPTION

[0033] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0034] Please refer to Figures 1 to 5E8 , the present application provides an array substrate 100, the array substrate 100 includes a first electrode layer 140, an active layer 160, a gate insulating layer 180 and a second electrode layer 190, the first electrode layer 140 includes a first metal layer 141 and a second metal layer 142 disposed on the first metal layer 141, the first metal layer 141 and the second metal layer 142 are insulated, the active layer 160 is overlapped on the sidewall of the first electrode layer 140, both ends of the active layer 160 are in contact with the first metal layer 141 and the second metal layer 142 respectively, the gate insulating layer 180 covers the active layer 160 and the first electrode layer 140, the second electrode layer 190 is disposed on the gate insulating layer 180; wherein, in the top view direction of the array substrate 100, the second electrode layer 190 and the first electrode layer 140 are arranged at an angle.

[0035] ​​The array substrate 100 provided in the application overlaps the active layer 160 on the sidewall of the first electrode layer 140, two ends of the active layer 160 are in contact with the first metal layer 141 and the second metal layer 142 respectively, and the second electrode layer 190 and the first electrode layer 140 are arranged at an angle, so that the area of the active layer 160 in the orthographic projection direction of the array substrate 100 is reduced, and therefore, compared with the prior art of preparing the active layer 160 on a plane, the present application occupies a smaller area of the array substrate 100 on the inclined plane, thereby increasing the aperture ratio of the array substrate 100.

[0036] The technical solutions of the application will be described in detail in combination with specific embodiments.

[0037] Please refer to Figure 1 , FIG. is a top view of the first electrode layer 140 and the second electrode layer 190 in the array substrate 100 provided in the embodiment of the application; in the embodiment of the application, the array substrate 100 comprises a plurality of thin film transistors, and at least one of the thin film transistors is a vertical transistor.

[0038] Specifically, the vertical transistor comprises a first electrode layer 140 and a second electrode layer 190, the first electrode layer 140 is the source and drain of the vertical transistor, and the second electrode layer 190 is the gate of the vertical transistor, the first electrode layer 140 comprises a first metal layer 141 and a second metal layer 142 arranged on the first metal layer 141, and the first metal layer 141 and the second metal layer 142 are arranged in insulation.

[0039] In the top view direction of the array substrate 100, the second electrode layer 190 and the first electrode layer 140 are arranged at an angle; such design is conducive to reducing the floor area of the vertical transistor on the array substrate 100, thereby facilitating the increase of the number of vertical transistors on the array substrate 100.

[0040] In the embodiment of the application, in the top view direction of the array substrate 100, the angle between the second electrode layer 190 and the first electrode layer 140 is 90 degrees; such design is conducive to the complete coverage of the second electrode layer 190 on the second metal layer 142, thereby avoiding the influence on the electrical properties of the vertical transistor.

[0041] Specifically, the array substrate 100 further includes an interlayer insulating layer 210, which has a first via 2101 that exposes a portion of the second metal layer 142. In a top view of the array substrate 100, the orthographic projection of the first via 2101 onto the second metal layer 142 does not coincide with the orthographic projection of the second electrode layer 190 onto the second metal layer 142. This design prevents the first via 2101 from penetrating the second electrode layer 190, thereby preventing the second electrode layer 190 from being penetrated by the first via 2101 and avoiding short circuits caused by electrical connections between the second electrode layer 190 and other metal film layers.

[0042] like Figure 2 As shown, the array substrate 100 provided in this embodiment of the application is along... Figure 1 A cross-sectional view along the A-A' direction; wherein, the array substrate 100 includes a substrate 110, a buffer layer 120 disposed on the substrate 110, a first ohmic contact layer 130 disposed on the buffer layer 120, a first electrode layer 140 disposed on the first ohmic contact layer 130, a second ohmic contact layer 170 disposed on the first electrode layer 140, a gate insulating layer 180 disposed on the second ohmic contact layer 170, a second electrode layer 190 disposed on the gate insulating layer 180, an interlayer insulating layer 210 disposed on the second electrode layer 190, a planarization layer 220 disposed on the interlayer insulating layer 210, a common electrode layer 230 disposed on the planarization layer 220, a passivation layer 240 disposed on the common electrode layer 230, and a pixel electrode layer 250 disposed on the passivation layer 240.

[0043] The array substrate 100 further includes a barrier layer 150 disposed between the first metal layer 141 and the second metal layer 142, wherein the thickness of the barrier layer 150 is greater than the thickness of either the first metal layer 141 or the second metal layer 142. This design increases the angle between the active layer 160 and the first metal layer 141 in the direction from the gate insulating layer 180 to the active layer 160, thereby reducing the area occupied by the active layer 160 on the vertical transistor.

[0044] In this embodiment, the substrate 110 can be made of materials such as glass, quartz, or polyimide.

[0045] In the embodiment, the buffer layer 120 is arranged between the first ohmic contact layer 130 and the substrate 110, and is used to isolate the first ohmic contact layer 130 and the upper metal material. The material of the buffer layer 120 can include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film or a silicon oxide-silicon nitride stacked structure. Specifically, the material of the buffer layer 120 is silicon nitride.

[0046] In the embodiment, the first ohmic contact layer 130 is used to electrically connect the active layer 160 and the first electrode layer 140. The material of the first ohmic contact layer 130 is amorphous silicon (a-Si) doped with phosphorus ions. + a-Si).

[0047] In the embodiment, the first metal layer 141 is arranged on the first ohmic contact layer 130, and is used as a source electrode or a drain electrode of the vertical transistor. The first metal layer 141 is electrically connected to the active layer 160 through the first ohmic contact layer 130. The material of the first metal layer 141 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0048] In the embodiment, the barrier layer 150 is arranged on the first metal layer 141, and is used to prevent the second metal layer 142 from short-circuiting with the first metal layer 141. The material of the barrier layer 150 is silicon nitride or silicon oxide.

[0049] In the embodiment, the second metal layer 142 is arranged on the barrier layer 150, and forms the first electrode layer 140 together with the first metal layer 141. The material of the second metal layer 142 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0050] Specifically, in the plan view direction of the array substrate 100, the orthographic projection of the second metal layer 142 on the first metal layer 141 is located in the first metal layer 141, and the area of the orthographic projection of the second metal layer 142 on the first ohmic contact layer 130 is smaller than the area of the orthographic projection of the first metal layer 141 on the first ohmic contact layer 130. The above design is to make the first metal layer 141, the barrier layer 150 and the second metal layer 142 form a convex structure. Since the sidewall of the convex structure is provided with the active layer 160, the active layer 160 can be arranged on an inclined surface, and the area of the orthographic projection of the active layer 160 in the plan view direction of the array substrate 100 is reduced.

[0051] In the embodiment of the present application, the active layer 160 comprises a first active part 161, the first active part 161 comprises a first sub-inclined part 1611 which is overlapped on one sidewall of the first electrode layer 140, one end of the first active part 161 is electrically connected with the first ohmic contact layer 130 and the first metal layer 141 respectively, and the other end of the first active part 161 is electrically connected with the second metal layer 142 and the second ohmic contact layer 170 respectively.

[0052] The active layer 160 further comprises a second active part 162 which is spaced apart from the first active part 161, the second active part 162 comprises a second sub-inclined part 1621 which is overlapped on another sidewall of the first electrode layer 140, one end of the second active part 162 is electrically connected with the first ohmic contact layer 130 and the first metal layer 141 respectively, and the other end of the second active part 162 is electrically connected with the second metal layer 142 and the second ohmic contact layer 170 respectively.

[0053] In the top view direction of the array substrate 100, the area of the orthographic projection of the first sub-inclined part 1611 on the first metal layer 141 is equal to the area of the orthographic projection of the second sub-inclined part 1621 on the first metal layer 141. Such design is to make the first active part 161 and the second active part 162 symmetric about the center line of the protrusion-shaped structure which is perpendicular to the substrate 110, so that the length of the first sub-inclined part 1611 and the second sub-inclined part 1621 on the sidewall is equal.

[0054] Specifically, the material of the active layer 160 can be any one of IGZO (indium gallium zinc oxide), a-Si (amorphous silicon) or LTPS (low temperature polysilicon), for example, the material of the active layer 160 in the present application can be Poly-Si (polysilicon).

[0055] Further, in the top view direction of the array substrate 100, the height of the first active part 161 or the second active part 162 which is perpendicular to the first ohmic contact layer 130 is equal to the sum of the thicknesses of the first electrode layer 140 and the barrier layer 150; such arrangement is to make the first active part 161, the second metal layer 142 and the second active part 162 flush away from the surface of the substrate 110, so as to facilitate the deposition of the second ohmic contact layer 170 on the second metal layer 142, and avoid the deposition of the second metal layer 142 on the sidewall of the protrusion-shaped structure.

[0056] Specifically, in the embodiment of the present application, the angle between the active layer 160 and the first metal layer 141 is greater than or equal to 60 degrees and less than or equal to 90 degrees in the direction from the gate insulating layer 180 to the active layer 160.

[0057] It can be understood that when the angle between the active layer 160 and the first metal layer 141 is greater than or equal to 60 degrees and less than or equal to 90 degrees, the doping amount of the channel part (the first sub-inclined part 1611 and the second sub-inclined part 1621) of the active layer 160 is very small or even no doping when the ion implantation process is performed, so as to avoid the influence of the doping ions on the current efficiency of the channel part.

[0058] In an embodiment, when the inclination angle is 90 degrees, the active layer 160 can be formed by an atomic deposition method. It can be understood that when the inclination angle is 90 degrees, the barrier layer 150 is perpendicular to the substrate 110, and the ordinary physical deposition method is used to deposit the active layer 160, which cannot cover the barrier layer 150. However, the atomic deposition is a chemical deposition method, which is a method of alternately passing gas-phase precursors into a reactor and chemisorbing and reacting on a deposition substrate to form a deposition film. Therefore, even if the barrier layer 150 is perpendicular to the substrate 110, it does not affect the chemisorption and surface reaction of the gas-phase precursors and the deposition substrate, and the active layer 160 formed can cover the barrier layer 150.

[0059] In the embodiment of the present application, the second ohmic contact layer 170 is arranged on the second metal layer 142 and completely covers the second metal layer 142, the active layer 160 is electrically connected to the second metal layer 142 through the second ohmic contact layer 170, and the material of the second ohmic contact layer 170 is amorphous silicon (a-Si) doped with phosphorus ions. + a-Si).

[0060] In the embodiment of the present application, the gate insulating layer 180 is arranged on the buffer layer 120 and completely covers the first active part 161, the second ohmic contact layer 170, and the second active part 162, the gate insulating layer 180 is laid in an integral layer, so that the active layer 160 and the conductive layer on the gate insulating layer 180 are arranged separately, and the material of the gate insulating layer 180 can be silicon oxide.

[0061] In the embodiment of the present application, the second electrode layer 190 is used as the gate electrode of the vertical transistor, the second electrode layer 190 is arranged on the gate insulating layer 180, and the second electrode layer 190 completely covers the active layer 160 and the protrusion-shaped structure.

[0062] Specifically, the material of the second electrode layer 190 can be copper, molybdenum, or a molybdenum-titanium alloy, etc.

[0063] In this embodiment, the interlayer insulating layer 210 is disposed on the second electrode layer 190, and the interlayer insulating layer 210 is laid out over the entire layer. The material of the interlayer insulating layer 210 can be an inorganic material composed of silicon oxynitride or an organic material with planarity. In this embodiment, the material of the interlayer insulating layer 210 is a silicon nitride.

[0064] In this embodiment, the planarization layer 220 is disposed on the interlayer insulating layer 210, and the planarization layer 220 is laid across the entire layer. Specifically, the material of the planarization layer 220 can be an inorganic material composed of silicon oxynitride or an organic material with planarity.

[0065] In this embodiment, the common electrode layer 230 is disposed on the planarization layer 220, and the common electrode layer 230 is used to provide a common electrode signal to the vertical transistor. Specifically, the common electrode layer 230 can be made of a transparent conductive material such as indium tin oxide.

[0066] In this embodiment, the passivation layer 240 is disposed on the planarization layer 220, the passivation layer 240 is laid out in the whole layer and completely covers the common electrode layer 230, and the material of the passivation layer 240 can be an inorganic material composed of silicon oxynitride or an organic material with planarity.

[0067] In this embodiment, the pixel electrode layer 250 is disposed on the passivation layer 240, and the material of the pixel electrode layer 250 can be a transparent conductive material such as indium tin oxide.

[0068] like Figure 3 As shown, Figure 3 The array substrate 100 provided in the embodiments of this application is along Figure 1 A cross-sectional view along the B-B' direction; wherein, in the length direction parallel to the first electrode layer 140, the orthogonal projections of the second electrode layer 190, the first ohmic contact layer 130, and the second ohmic contact layer 170 onto the second metal layer 142 are all located within the second metal layer 142.

[0069] Specifically, the interlayer insulating layer 210 has a first via 2101, and the pixel electrode layer 250 is electrically connected to the second metal layer 142 through the first via 2101.

[0070] In this embodiment, the pixel electrode layer 250 and the common electrode layer 230 have an overlapping portion, which is used to form the storage capacitor of the vertical transistor.

[0071] The application provides an array substrate 100, which comprises a first electrode layer 140, an active layer 160, a gate insulating layer 180 and a second electrode layer 190, the first electrode layer 140 comprises a first metal layer 141 and a second metal layer 142 arranged on the first metal layer 141, the first metal layer 141 and the second metal layer 142 are arranged in an insulating mode, the active layer 160 is overlapped on the side wall of the first electrode layer 140, two ends of the active layer 160 are in contact with the first metal layer 141 and the second metal layer 142 respectively, the gate insulating layer 180 covers the active layer 160 and the first electrode layer 140, and the second electrode layer 190 is arranged on the gate insulating layer 180; wherein in the plan view direction of the array substrate 100, the second electrode layer 190 and the first electrode layer 140 are arranged at an angle.

[0072] The array substrate 100 provided by the application overlaps the active layer 160 on the side wall of the first electrode layer 140, the two ends of the active layer 160 are in contact with the first metal layer 141 and the second metal layer 142 respectively, and the second electrode layer 190 and the first electrode layer 140 are arranged at an angle, so that the area of the active layer 160 in the plan view direction of the array substrate 100 is reduced, and therefore, compared with the prior art of preparing the active layer 160 on a plane, the present application occupies a smaller area of the array substrate 100 on the inclined plane, thereby increasing the aperture ratio of the array substrate 100.

[0073] Please refer to Figure 4 The application further provides a manufacturing method of the array substrate 100, which comprises the following steps.

[0074] S10, sequentially forming a first ohmic contact layer 130 and a first electrode layer 140 on a substrate 110, the first electrode layer 140 comprises a first metal layer 141 and a second metal layer 142 arranged on the first metal layer 141, and the first metal layer 141 and the second metal layer 142 are arranged in an insulating mode.

[0075] Specifically, the S10 further comprises the following steps.

[0076] Please refer to Figure 5A1 , Figure 5A1 The array substrate 100 is arranged along Figure 1Figure 2 is a cross-sectional view of the array substrate 100 along the direction of A-A'; first, a substrate 110 is provided, which can be made of glass, quartz, polyimide or other materials; then, a first inorganic film layer is deposited on the substrate 110 by a chemical vapor deposition process to form a buffer layer 120; finally, a first semiconductor doped layer is deposited on the buffer layer 120 by a chemical vapor deposition process, which is patterned to form a first ohmic contact layer 130.

[0077] Please continue to refer to Figure 5A2 , Figure 5A2 For the array substrate 100 along Figure 1 Figure 2 is a cross-sectional view of the array substrate 100 along the direction of A-A'; first, a substrate 110 is provided, which can be made of glass, quartz, polyimide or other materials; then, a first inorganic film layer is deposited on the substrate 110 by a chemical vapor deposition process to form a buffer layer 120; finally, a first semiconductor doped layer is deposited on the buffer layer 120 by a chemical vapor deposition process, which is patterned to form a first ohmic contact layer 130.

[0078] Please continue to refer to Figure 5A3 , Figure 5A3 For the array substrate 100 along Figure 1 Figure 2 is a cross-sectional view of the array substrate 100 along the direction of A-A'; first, a substrate 110 is provided, which can be made of glass, quartz, polyimide or other materials; then, a first inorganic film layer is deposited on the substrate 110 by a chemical vapor deposition process to form a buffer layer 120; finally, a first semiconductor doped layer is deposited on the buffer layer 120 by a chemical vapor deposition process, which is patterned to form a first ohmic contact layer 130.

[0079] Please continue to refer to Figure 5A4 , Figure 5A4 For the array substrate 100 along Figure 1 Figure 2 is a cross-sectional view of the array substrate 100 along the direction of A-A'; first, a substrate 110 is provided, which can be made of glass, quartz, polyimide or other materials; then, a first inorganic film layer is deposited on the substrate 110 by a chemical vapor deposition process to form a buffer layer 120; finally, a first semiconductor doped layer is deposited on the buffer layer 120 by a chemical vapor deposition process, which is patterned to form a first ohmic contact layer 130.

[0080] S20, forming a first semiconductor layer on the first ohmic contact layer 130, which is patterned to obtain an active layer 160, the active layer 160 is overlapped on the sidewall of the first electrode layer 140, and the two ends of the active layer 160 are respectively in contact with the first metal layer 141 and the second metal layer 142.

[0081] Specifically, the S20 further includes:

[0082] Please refer to Figure 5B , Figure 5B For the array substrate 100 along Figure 1A cross-sectional view along the direction of A-A'; wherein a first semiconductor layer is first formed on the first ohmic contact layer 130, the first semiconductor layer is patterned to form an active layer 160, the active layer 160 is overlapped on the sidewall of the first electrode layer 140, and two ends of the active layer 160 are respectively in contact with the first metal layer 141 and the second metal layer 142.

[0083] The active layer 160 includes a first active part 161 and a second active part 162 which is spaced apart from the first active part 161, the first active part 161 is located on one sidewall of the first electrode layer 140, and the second active part 162 is located on the other sidewall of the second electrode layer 190.

[0084] S30, a second ohmic contact layer 170 is formed on the second metal layer 142, and two ends of the second ohmic contact layer 170 are respectively electrically connected with the active layer 160.

[0085] Specifically, the S30 further includes:

[0086] Please refer to Figure 5C , Figure 5C for the array substrate 100 along Figure 1 A cross-sectional view along the direction of A-A'; wherein a second semiconductor doped layer is first deposited on the second metal layer 142 by a chemical vapor deposition process, the second semiconductor doped layer is patterned to form a second ohmic contact layer 170, and two ends of the second ohmic contact layer 170 are respectively electrically connected with the active layer 160.

[0087] The one end of the second ohmic contact layer 170 is electrically connected with the first active part 161, and the other end of the second ohmic contact layer 170 is electrically connected with the second active part 162.

[0088] S40, a gate insulating layer 180, a second electrode layer 190 and an interlayer insulating layer 210 are sequentially formed on the substrate 110, the interlayer insulating layer 210 has a first via hole 2101, and the first via hole 2101 exposes part of the second metal layer 142.

[0089] Specifically, the S40 further includes:

[0090] Please refer to Figure 5D1 , Figure 5D1 for the array substrate 100 along Figure 1A cross-sectional view along the A-A' direction; wherein, firstly, a third inorganic film layer is deposited on the buffer layer 120 to form a gate insulating layer 180; then, a third metal material layer is deposited on the gate insulating layer 180, and the third metal material layer is patterned to form a second electrode layer 190, the second electrode layer 190 covering the second ohmic contact layer 170; finally, an interlayer insulating layer 210 is formed by depositing a fourth inorganic film layer on the gate insulating layer 180.

[0091] Please see Figure 5D2 , Figure 5D2 For the array substrate 100 along Figure 1 A cross-sectional view along the B-B' direction; First, a first via 2101 is formed on the interlayer insulating layer 210. The first via 2101 penetrates the interlayer insulating layer 210 and a portion of the gate insulating layer 180, and exposes a portion of the second metal layer 142. However, the first via 2101 does not penetrate the second electrode layer 190.

[0092] S50. A planarization layer 220, a common electrode layer 230, a passivation layer 240 and a pixel electrode layer 250 are sequentially formed on the interlayer insulating layer 210. The passivation layer 240 has a second via 2401. The first via 2101 is located in the second via 2401. The pixel electrode layer 250 is electrically connected to the second metal layer 142 through the second via 2401.

[0093] Please see Figure 5E1 , Figure 5E1 For the array substrate 100 along Figure 1 A cross-sectional view along the A-A' direction; wherein, a planarization layer 220 is first formed after a fourth inorganic film layer is deposited on the gate insulating layer 180.

[0094] Please see Figure 5E2 , Figure 5E2 For the array substrate 100 along Figure 1 A cross-sectional view along the B-B' direction; then, a third via 2201 is formed on the planarization layer 220, the third via 2201 penetrating the planarization layer 220 and exposing the first via 2101.

[0095] Please see Figure 5E3 , Figure 5E3 For the array substrate 100 along Figure 1 A cross-sectional view along the A-A' direction; then, a first transparent conductive material layer is deposited on the planarization layer 220, and the first transparent conductive material layer is patterned to form a common electrode layer 230.

[0096] Please see Figure 5E4 ,Figure 5E4 For the array substrate 100 along Figure 1 A cross-sectional view along the B-B' direction; wherein the common electrode layer 230 does not cover the third via 2201.

[0097] Please see Figure 5E5 , Figure 5E5 For the array substrate 100 along Figure 1 A cross-sectional view along the A-A' direction; wherein, after depositing a fifth inorganic film layer on the gate insulating layer 180, a passivation layer 240 is formed, and the passivation layer 240 completely covers the common electrode layer 230 and the third via 2201.

[0098] Please see Figure 5E6 , Figure 5E6 For the array substrate 100 along Figure 1 A cross-sectional view along the B-B' direction; wherein, a second via 2401 is formed on the passivation layer 240, the second via 2401 penetrates the passivation layer 240, the planarization layer 220, the interlayer insulating layer 210 and a portion of the gate insulating layer 180 and exposes the third via 2201, the first via 2101 and the second metal layer 142.

[0099] Please see Figure 5E7 , Figure 5E7 For the array substrate 100 along Figure 1 A cross-sectional view along the A-A' direction; wherein, a second transparent conductive material layer is deposited on the passivation layer 240, and the second transparent conductive material layer is patterned to form a pixel electrode layer 250.

[0100] Please see Figure 5E8 , Figure 5E8 For the array substrate 100 along Figure 1 A cross-sectional view along the B-B' direction; wherein the pixel electrode layer 250 completely fills the second via 2401, and the pixel electrode layer 250 is electrically connected to the second metal layer 142 through the second via 2401. Specifically, the pixel electrode layer 250 and the common electrode layer 230 have an overlapping portion.

[0101] Please see Figure 1 , Figure 2 as well as Figure 3 In the above embodiments of this application, the array substrate 100 has the following different features from the array substrate 100 of the prior art:

[0102] In a first aspect, the active layer 160 includes the first active part 161 and the second active part 162 which is spaced apart from the first active part 161, and the first active part 161 and the second active part 162 are respectively overlapped on the sidewall of the first electrode layer 140 with an inclined surface, so that the channel length L of the vertical transistor (i.e. the length of the first active part 161 or the second active part 162 extending from the first metal layer 141 to the second metal layer 142 on the sidewall) is determined by the taper angle of the active layer 160 and the first metal layer 141 and the thickness of the blocking layer 150 between the first metal layer 141 and the second metal layer 142. The above design makes the active layer 160 a vertical structure, so that the footprint of the active layer 160 on the array substrate 100 is greatly reduced.

[0103] In a second aspect, one end of the first active part 161 is respectively electrically connected with the first ohmic contact layer 130 and the first metal layer 141, and the other end of the first active part 161 is respectively electrically connected with the second metal layer 142 and the second ohmic contact layer 170, while one end of the second active part 162 is respectively electrically connected with the first ohmic contact layer 130 and the first metal layer 141, and the other end of the second active part 162 is respectively electrically connected with the second metal layer 142 and the second ohmic contact layer 170, so that the first active part 161 on one sidewall and the second active part 162 on the other sidewall are connected in parallel through the parallelly arranged first metal layer 141 and the second metal layer 142, which equivalently increases the channel width W (i.e. the length of the first metal layer 141 on the AA' cross section) of the vertical transistor. Since the on-state current of the vertical transistor is proportional to the channel width W and inversely proportional to the channel length L in the vertical transistor, the size of the on-state current of the vertical transistor basically depends on the width-length ratio W / L of the channel; therefore, the above structure of the active layer 160 can proportionally increase the on-state current of the vertical transistor.

[0104] Therefore, the array substrate 100 of the embodiment of the present application can effectively reduce the footprint of the vertical transistor and increase the on-state current of the vertical transistor, which is very beneficial to the manufacture of the array substrate 100 with high resolution, high aperture ratio, narrow frame and high refresh rate.

[0105] The embodiment of the present application further provides a display panel including the array substrate 100 and an opposite substrate which are oppositely arranged. The display panel provided by the embodiment of the present application can be a liquid crystal display panel or an organic light emitting diode display panel.

[0106] The display terminal provided by the embodiment of the present application can be a product or component with display function, such as a mobile phone, a tablet computer, a notebook computer, a television, a digital camera, a navigator, and the like.

[0107] The array substrate 100 provided by the present application comprises a first electrode layer 140, an active layer 160, a gate insulating layer 180 and a second electrode layer 190, the first electrode layer 140 comprises a first metal layer 141 and a second metal layer 142 arranged on the first metal layer 141, the first metal layer 141 and the second metal layer 142 are arranged in insulation, the active layer 160 is overlapped on the sidewall of the first electrode layer 140, two ends of the active layer 160 are in contact with the first metal layer 141 and the second metal layer 142 respectively, the gate insulating layer 180 covers the active layer 160 and the first electrode layer 140, and the second electrode layer 190 is arranged on the gate insulating layer 180; wherein, in the plan view direction of the array substrate 100, the second electrode layer 190 and the first electrode layer 140 are arranged at an angle.

[0108] The array substrate 100 provided by the present application overlaps the active layer 160 on the sidewall of the first electrode layer 140, two ends of the active layer 160 are in contact with the first metal layer 141 and the second metal layer 142 respectively, and the second electrode layer 190 and the first electrode layer 140 are arranged at an angle, so that the area of the active layer 160 in the plan view direction of the array substrate 100 is reduced, and therefore, compared with the prior art of preparing the active layer 160 on a plane, the present application occupies a smaller area of the array substrate 100 in the preparation of the active layer 160 on an inclined plane, thereby increasing the aperture ratio of the array substrate 100.

[0109] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0110] The array substrate 100 and the manufacturing method and the display panel provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper, and the above embodiment description is only used to help understand the technical solutions and core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that, include: The first electrode layer includes a first metal layer and a second metal layer disposed on the first metal layer. The first metal layer and the second metal layer are insulated from each other. The first electrode layer has two opposing sidewalls. An active layer is attached to the sidewall of the first electrode layer, and both ends of the active layer are in contact with the first metal layer and the second metal layer, respectively. A gate insulating layer covers the active layer and the first electrode layer; as well as The second electrode layer is disposed on the gate insulating layer; In the top view of the array substrate, the second electrode layer and the first electrode layer are arranged at an angle; the array substrate further includes a first ohmic contact layer and a second ohmic contact layer, with the first electrode layer located between the first ohmic contact layer and the second ohmic contact layer; both ends of the active layer are in contact with the first ohmic contact layer and the second ohmic contact layer, respectively; the active layer includes a first active portion and a second active portion spaced apart from the first active portion, the first active portion including a first sub-tilted portion overlapping one sidewall of the first electrode layer, and the second active portion including a second sub-tilted portion overlapping the other sidewall of the first electrode layer; one end of the second ohmic contact layer is in contact with the first sub-tilted portion, and the other end is in contact with the second sub-tilted portion, and the second electrode layer continuously covers the first sub-tilted portion and the second sub-tilted portion.

2. The array substrate according to claim 1, characterized in that, In the top view direction of the array substrate, the orthographic projection area of ​​the first sub-tilted portion on the first metal layer is equal to the orthographic projection area of ​​the second sub-tilted portion on the first metal layer.

3. The array substrate according to claim 2, characterized in that, The array substrate further includes a barrier layer disposed between the first metal layer and the second metal layer; The thickness of the barrier layer is greater than the thickness of the first metal layer or the second metal layer.

4. The array substrate according to claim 3, characterized in that, In the top view direction of the array substrate, the height of the first active portion or the second active portion in the direction perpendicular to the first ohmic contact layer is the same as the sum of the thicknesses of the first electrode layer and the barrier layer.

5. The array substrate according to claim 1, characterized in that, In the top view direction of the array substrate, the orthographic projection of the second metal layer onto the first metal layer is located within the first metal layer, and the orthographic projection area of ​​the second metal layer onto the first ohmic contact layer is smaller than the orthographic projection area of ​​the first metal layer onto the first ohmic contact layer.

6. The array substrate according to claim 1, characterized in that, In the direction from the gate insulating layer to the active layer, the angle between the active layer and the first metal layer is greater than or equal to 60 degrees and less than or equal to 90 degrees.

7. The array substrate according to claim 1, characterized in that, The array substrate further includes an interlayer insulating layer disposed on the second electrode layer and a pixel electrode layer disposed on the interlayer insulating layer. The interlayer insulating layer has a first via, and the pixel electrode layer is electrically connected to the second metal layer through the first via. In the top view direction of the array substrate, the orthographic projection of the first via on the second metal layer does not coincide with the orthographic projection of the second electrode layer on the second metal layer.

8. A method for fabricating an array substrate, characterized in that, include: A first ohmic contact layer and a first electrode layer are sequentially formed on a substrate. The first electrode layer includes a first metal layer and a second metal layer disposed on the first metal layer. The first metal layer and the second metal layer are insulated from each other. The first electrode layer has two opposing sidewalls. A first semiconductor layer is formed on the first ohmic contact layer. The first semiconductor layer is patterned to obtain an active layer. The active layer overlaps the sidewall of the first electrode layer. The two ends of the active layer are in contact with the first metal layer and the second metal layer, respectively. The active layer includes a first active portion and a second active portion spaced apart from the first active portion. The first active portion includes a first sub-tilted portion overlapping one sidewall of the first electrode layer. The second active portion includes a second sub-tilted portion overlapping the other sidewall of the first electrode layer. A second ohmic contact layer is formed on the second metal layer. Both ends of the second ohmic contact layer are electrically connected to the active layer. One end of the second ohmic contact layer contacts the first sub-tilted portion, and the other end contacts the second sub-tilted portion. A gate insulating layer, a second electrode layer, and an interlayer insulating layer are sequentially formed on the substrate. The second electrode layer continuously covers the first sub-tilted portion and the second sub-tilted portion. The interlayer insulating layer has a first via, and the first via exposes a portion of the second metal layer. A planarization layer, a common electrode layer, a passivation layer, and a pixel electrode layer are sequentially formed on the interlayer insulating layer. The passivation layer has a second via, and the first via is located inside the second via. The pixel electrode layer is electrically connected to the second metal layer through the second via.

9. A display panel, characterized in that, It includes an array substrate and an opposing substrate arranged opposite each other, wherein the array substrate is the array substrate according to any one of claims 1 to 7.

Images