Non-volatile memory element and method of making the same

Abstract

A non-volatile memory element and a method of making the same are disclosed. The non-volatile memory element includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from a surface of the substrate. The first floating gate is located in the recess and has a base and a sidewall connected to the base, and is electrically isolated from the semiconductor substrate. The first control gate is located above the first floating gate and is electrically isolated from the semiconductor substrate and the first floating gate. The first drain region is located in the semiconductor substrate in the recess. The common source region is located in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main portion and an extension. The main portion is located below a bottom surface of the recess and is adjacent to the base. The extension extends upward from the bottom surface and beyond the base, and is adjacent to the sidewall.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory device and a method for fabricating the same, and more particularly to a non-volatile memory (NVM) device and a method for fabricating the same. BACKGROUND

[0002] Non-volatile memory devices, such as floating gate flash memory, have the characteristic of not losing information stored in the memory cells when the power is removed. They have been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, etc.

[0003] A typical floating gate flash memory has a plurality of diffusion regions and isolation regions arranged alternately along a first direction (e.g., x-axis direction) in a substrate, and a plurality of gate structures (including longitudinally stacked gate dielectric layer, floating gate, tunneling dielectric layer and control gate) arranged in a second direction (e.g., y-axis direction) perpendicular to the first direction and spaced apart from the diffusion regions. Each diffusion region overlaps with a gate structure, and the diffusion regions on the sides of the gate structure can be used as source regions and the diffusion regions on the other sides of the gate structure can be used as drain regions, thereby defining a memory cell. An array of memory cells is formed on the substrate.

[0004] Each drain region of the memory cells arranged in the same row is respectively connected to an external lead through an individual contact window, and the source regions of the memory cells arranged in the same row are connected in series through a common source line defined by a doped region in the substrate, and are electrically connected to an external lead through a source contact window disposed between two isolation regions.

[0005] Since the distances between the source regions of each memory cell arranged in the same row and the contact window are different, although the source regions share a common source line, the length of the doped region connecting each memory cell to the contact window is different, and the resistance value of the doped region connecting each memory cell to the contact window is also different. When the source load changes (e.g., a read voltage is applied to the memory cell), the loading effect of the source will cause the outputs (e.g., read current) of the memory cells to be inconsistent, thereby reducing the stability and reliability of the signal (e.g., read signal) and even affecting the operating performance of the memory cell (e.g., causing read failure of the memory cell).

[0006] Therefore, there is a need to provide an advanced non-volatile memory device and a method for fabricating the same to solve the problems faced by the prior art. SUMMARY

[0007] One embodiment of the present specification discloses a non-volatile memory device, comprising: a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from a surface of the substrate. The first floating gate is located in the recess, has a base and a sidewall connected to the base, and is electrically isolated from the semiconductor substrate. The first control gate is located above the first floating gate and is electrically isolated from the semiconductor substrate and the first floating gate, respectively. The first drain region is located in the semiconductor substrate in the recess. The common source region is located in the semiconductor substrate in the recess, is adjacent to the first floating gate, and comprises: a main body and an extension. The main body is located below the bottom surface of the recess and is adjacent to the base of the first floating gate. The extension extends upward from the bottom surface of the recess and beyond the base of the first floating gate, and is adjacent to the sidewall of the first floating gate.

[0008] Another embodiment of the present specification discloses a method for manufacturing a non-volatile memory device, comprising the following steps: first, providing a semiconductor substrate, so that the semiconductor substrate has a recess extending downward from a surface of the substrate. Then, forming a floating gate in the recess, so that it has a base and a sidewall connected to the base, and is electrically isolated from the semiconductor substrate. Then, forming a control gate adjacent to the first floating gate, and being electrically isolated from the semiconductor substrate and the floating gate, respectively. And forming a drain region and a common source region in the semiconductor substrate in the recess, so that the common source region is adjacent to the floating gate and comprises a main body and an extension. The main body is located below the bottom surface of the recess and is adjacent to the base of the first floating gate. The extension extends upward from the bottom surface of the recess and beyond the base, and is adjacent to the sidewall of the first floating gate.

[0009] According to the above-mentioned embodiments, the present specification provides a non-volatile memory device and a method for manufacturing the same. By forming a recess in the semiconductor substrate, then forming a floating gate on the bottom surface of the recess, forming a control gate on the floating gate, and forming a source region and a drain region in the semiconductor substrate in the recess, the source region has a main body located below the bottom surface of the recess, and an extension extending upward from the bottom surface of the recess and beyond the base of the floating gate, and is adjacent to the sidewall of the floating gate. At least one memory cell is formed in the semiconductor substrate.

[0010] The extensions protruding from the bottom surface of the recess can substantially enlarge the cross-sectional area of the source region of each memory cell, which can increase the on-current of the source region and reduce the resistance of the source region. When a plurality of memory cells are connected in series by their respective source regions to form a common source line, the adverse effects of source loading on the output stability of each memory cell can be alleviated. In some embodiments, the resistance of the common source line can be further reduced by increasing the doping concentration of the extensions of the source regions of each memory cell, which can further reduce the source loading effect and improve the operating performance of the non-volatile memory element. BRIEF DESCRIPTION OF DRAWINGS

[0011] For a better understanding of the above and other aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figures 1A-1L A series of cross-sectional schematic diagrams of fabricating a non-volatile memory element is shown in an embodiment of the present disclosure.

[0013] LIST OF SYMBOLS

[0014] 100; non-volatile memory element

[0015] 101: semiconductor substrate

[0016] 101a: substrate surface

[0017] 102: recess

[0018] 102A: first sub-recess

[0019] 102B: second sub-recess

[0020] 102k: bottom surface of the recess

[0021] 102s: sidewall of the recess

[0022] 103A: first control gate

[0023] 103B: second control gate

[0024] 104: protrusion

[0025] 104t: top surface

[0026] 105A: first floating gate

[0027] 105B: second floating gate

[0028] 105k: base of the floating gate

[0029] 105t: top of the floating gate

[0030] 106: shallow trench isolation structure

[0031] 107: pad silicon oxide layer

[0032] 108: hard mask layer

[0033] 109: trench

[0034] 110: dielectric material

[0035] 111: gate dielectric layer

[0036] 112: first conductive layer

[0037] 113: dielectric storage layer

[0038] 114: second conductive layer

[0039] 115: oxide layer

[0040] 116: hard mask layer

[0041] 117: spacer

[0042] 118: patterned photoresist layer

[0043] 119A: first drain region

[0044] 119B: second drain region

[0045] 120: patterned photoresist layer

[0046] 121: common source region

[0047] 121A: body portion

[0048] 121B: extension portion

[0049] 122: erase gate

[0050] 123A: first word line

[0051] 123B: second word line

[0052] 124: logic gate structure

[0053] 125: inner dielectric layer

[0054] 130A: first memory cell

[0055] 130B: second memory cell

[0056] IMP1: ion implantation fabrication process

[0057] IMP2: ion implantation fabrication process DETAILED DESCRIPTION

[0058] The present application provides a non-volatile memory device and a method of fabricating the same. The present application can reduce the negative effect of source load on the output stability of each memory cell. For the above-mentioned embodiments and other objects, features and advantages of the present application, refer to the detailed description and the appended drawings.

[0059] It must be noted that, as the making and using of the embodiments are involved in this specification, other specific embodiments and features thereof can be apparent to those skilled in the art and can be practiced or carried out without departing from the spirit and scope of the application. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature, and not as restrictive. Like numbers have been used in the drawings to indicate like features.

[0060] Please refer to Figures 1A-1L , Figures 1A-1L Fig. 1 is a series of cross-sectional views illustrating a method of fabricating a non-volatile memory device 100 according to an embodiment of the present application. The method of fabricating the non-volatile memory device 100 includes the following steps: first, providing a semiconductor substrate 101, such that the semiconductor substrate 101 has a recess 102 extending downward from a substrate surface 101a (as shown in Fig. 1A). Figure 1A

[0061] In some embodiments of the present application, the semiconductor substrate 101 can be a substrate made of a semiconductor material, such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). In other embodiments, the semiconductor substrate 101 can be a silicon-on-insulator (SOI) substrate. In the present embodiment, the semiconductor substrate 101 is preferably a silicon substrate, such as a silicon wafer.

[0062] The recess 102 is formed by an etching process using a photoresist (not shown) to remove a portion of the semiconductor substrate 101 downward from the substrate surface 101a, so as to form the recess 102 and leave a portion of the semiconductor substrate 101 in the recess 102 to form a protrusion 104 extending upward from a bottom surface 102k of the recess 102 and dividing the recess 102 into a first sub-recess 102A and a second sub-recess 102B. In the present embodiment, the protrusion 104 has a top surface 104t substantially coplanar with the substrate surface 101a.

[0063] ​Next, at least one floating gate (e.g., a first floating gate 105A and a second floating gate 105B) is formed in the recess 102, each having a base 105k and a sidewall 105s connecting the base 105k, and electrically isolated from the semiconductor substrate 101. In some embodiments of this specification, before forming the first floating gate 105A and the second floating gate 105B, a shallow trench isolation structure 106 is first formed in the recess 102.

[0064] The shallow trench isolation structure 106 is formed by a thermal oxidation process, forming a pad silicon oxide layer 107 covering the substrate surface 101, the sidewalls 102s and bottom surface 102k of the recess 102, and the protrusion 104 located in the recess 102. A silicon nitride hard mask layer 108 is then formed on the pad silicon oxide layer 107 (e.g., ...). Figure 1B shown).

[0065] Next, the patterned pad silicon oxide layer 107, hard mask layer 108, and substrate 101 are used to form trenches 109 in the recess 102 (e.g., Figure 1C (As illustrated). Then, using dielectric material 110, for example, silicon oxide (SiO2). x Silicon carbide (SiC), silicon oxycarbide (SiCO), silicon nitride (SiN), silicon oxynitride (SiNO), or other suitable materials are used to fill trench 109 (e.g. Figure 1D (As illustrated). Then, using the pad silicon oxide layer 107 as a stop layer, a planarization process, such as Chemical Mechanical Polishing (CMP), is performed to remove a portion of the dielectric material 110, a portion of the hard mask layer 108, and a portion of the pad silicon oxide layer 107 to form a shallow trench isolation structure 106 (as shown). Figure 1E shown).

[0066] After removing a portion of the remaining hard mask layer 108 and pad silicon oxide layer 107 located in the recess 102, a gate dielectric layer 111 is formed on the substrate surface 101 using a deposition process, covering the sidewalls 102s (including a portion of the shallow trench isolation structure 106) and bottom surface 102k of the recess 102; and a first conductor layer 112 is formed over the gate dielectric layer 111 (e.g., ...). Figure 1F (As illustrated). A portion of the first conductor layer 112 outside the recess 102 is removed using another planarization process (not shown). The remaining portion of the first conductor layer 112 in the recess 102 is then etched back to form a first floating gate 105A and a second floating gate 105B isolated from each other in the first sub-recess 102A and the second sub-recess 102B, respectively (as shown). Figure 1GThe first floating gate 105A and the second floating gate 105B are electrically isolated from the semiconductor substrate 101 by a portion of the gate dielectric layer 111 covering the sidewalls 102s and the bottom surface 102k of the recessed chamber 102. The base 105k of the first floating gate 105A and the second floating gate 105B are respectively adjacent to the protrusion 104 in the recessed chamber 102.

[0067] The material constituting the gate dielectric layer 111 can be, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiNO), high-κ dielectric material (e.g., hafnium oxide (HfO2), aluminum oxide (AlO x ), or a combination of the above dielectric materials.

[0068] After the formation of the first floating gate 105A and the second floating gate 105B, the first control gate 103A and the second control gate 103B are formed to be electrically isolated from each other, and are respectively adjacent to the first floating gate 105A and the second floating gate 105B above, and are electrically isolated from the semiconductor substrate 101 and the first floating gate 105A and the second floating gate 105B. In some embodiments of the present disclosure, the formation of the first control gate 103A and the second control gate 103B includes, first, forming a dielectric storage layer 113 covering the first floating gate 105A and the second floating gate 105B and the protrusion 104; then forming a second conductive layer 114 covering the dielectric storage layer 113; forming an oxide layer 115 covering the second conductive layer 114; and forming a hard mask layer 116 covering the oxide layer 115 (as shown in the drawing). Figure 1H

[0069] ​In some embodiments of the present disclosure, the dielectric storage layer 113 comprises at least one composite layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (i.e., an ONO structure). However, the structure of the dielectric storage layer 113 is not limited thereto. In other embodiments of the present disclosure, the composite layer of the dielectric storage layer 113 can also be selected from a group consisting of an oxide-nitride-oxide-nitride-oxide (ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, a tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon (TANOS) structure, and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure.

[0070] Subsequently, a photolithography and etching process is performed with the dielectric storage layer 113 as a stop layer to remove a portion of the hard mask layer 116, a portion of the oxide layer 115, and a portion of the second conductive layer 114 to form the first control gate 103A and the second control gate 103B stacked by a portion of the dielectric storage layer 113, a portion of the second conductive layer 114, and a portion of the hard mask layer 116 above the first floating gate 105A and the second floating gate 105B, respectively. In the present embodiment, the first control gate 103A and the second control gate 103B are electrically isolated from each other.

[0071] In addition, after forming the first control gate 103A and the second control gate 103B, the method further includes forming at least one spacer 117 on sidewalls of the first control gate 103A and the second control gate 103B and covering the top 105t of the first floating gate 105A and the second floating gate 105B, respectively (as shown in FIG. 1C). Figure 1I

[0072] ​It is noted that the spacer 117 can be a single layer structure or a multi-layer structure, and in some embodiments, each layer in the multi-layer structure of the spacer 117 can be formed on the sidewall of the first control gate 103A and the second control gate 103B by different materials and fabrication processes in different fabrication process steps, respectively.

[0073] After the formation of the first control gate 103A and the second control gate 103B, a patterned photoresist layer 118 is formed over the substrate 101 to expose a portion of the recess 102 (the first sub-recess 102A and the second sub-recess 102B) not covered by the first floating gate 105A and the second floating gate 105B, and at least one ion implantation process IMP1 is performed to form the first drain region 119A and the second drain region 119B in the semiconductor substrate 101 under the exposed portion of the recess 102, respectively (as shown in Figure 1J ).

[0074] After the removal of the patterned photoresist layer 118, another patterned photoresist layer 120 is formed over the substrate 101 to expose the area above the protrusion 104, and another ion implantation process IMP2 is performed to form the common source region 121 in the protrusion 104 and the substrate 101 under the protrusion 104 (as shown in Figure 1K ). In this embodiment, the common source region 121 includes a main body portion 121A and an extension portion 121B. The extension portion 121B can be formed by the doped protrusion 104. The main body portion 121A can be formed by the doped region under the extension portion 121B (under the bottom surface 102k of the recess 102). The main body portion 121A is adjacent to the base portion 105k of the first floating gate 105A and the second floating gate 105B.

[0075] The extension portion 121B of the common source region 121 extends upward from the bottom surface 102k of the recess 102 and beyond the base portion 105k of the first floating gate 105A and the second floating gate 105B, and is adjacent to the sidewall of the first floating gate 105A and the second floating gate 105B2. The top surface of the extension portion 121 (the top surface 104t of the protrusion) is substantially coplanar with the substrate surface 101. The distance H between the base portion 105k and the top portion 105t of the first floating gate 105A and the second floating gate 105B is substantially less than or equal to the depth D of the recess 102. The doping concentration of the extension portion 121B is higher than that of the main body portion.

[0076] Then, an erase gate 122 is formed over the extension 121B of the common source region 121, abutting the first floating gate 105A, the second floating gate 105B, the first control gate 103A and the second control gate 103B; and the erase gate 122 is electrically isolated from the semiconductor substrate 101 (including the common source region 121), the first floating gate 105A, the second floating gate 105B, the first control gate 103A and the second control gate 103B by the gate dielectric layer 111 and the spacers 117.

[0077] A first word line 123A is formed in the first sub-recess 102A, abutting the first floating gate 105A and the first control gate 103A; and a second word line 123B is formed in the second sub-recess 102B, abutting the second floating gate 105B and the second control gate 103B. The first word line 123A and the second word line 123B are electrically isolated from the semiconductor substrate 101 (including the common source region 121), the first floating gate 105A, the second floating gate 105B, the first control gate 103A and the second control gate 103B by the gate dielectric layer 111 and the spacers 117.

[0078] The first floating gate 105A, the first control gate 103A, the first drain region 119A and the common source region 121 together form a first memory cell 130A; and the second floating gate 105B, the second control gate 103B, the second drain region 119B and the common source region 121 together form a second memory cell 130B.

[0079] The common source region 121 includes both the extension 121B protruding beyond the base 105k of the first floating gate 105A and the second floating gate 105B and the main body 121A located below the base 105k. The cross-sectional area of the common source region 121 can be substantially enlarged, the on-current of the common source region 121 can be increased, and the series resistance of the common source region 121 can be reduced. In addition, the negative effect of the source load on each memory cell (not shown) connected in series to the common source region 121 can be alleviated.

[0080] Subsequently, a logic gate structure 124 is formed in a logic region of the semiconductor substrate 101 by a back-end-of-line (BEOL) process, an inner dielectric layer 125 is formed on the surface 101a of the substrate, and metal interconnects (not shown) are formed in the inner dielectric layer 125. The non-volatile memory element 100 shown in Figure 1L is thus completed.

[0081] According to the above embodiments, the present application provides a nonvolatile memory element and a method for manufacturing the same. The nonvolatile memory element includes a semiconductor substrate, a floating gate formed on a bottom surface of a recess formed in the semiconductor substrate, a control gate formed on the floating gate, a source region and a drain region formed in the semiconductor substrate in the recess, the source region having a main body portion located below the bottom surface of the recess and an extension portion extending upward from the bottom surface of the recess beyond a base portion of the floating gate and abutting a sidewall of the floating gate, and a drain electrode formed on the drain region.

[0082] The extension portion of the source region extending above the bottom surface of the recess can substantially increase the cross-sectional area of the source region of each memory cell, thereby increasing the on-current of the source region and reducing the resistance of the source region. When a plurality of memory cells are connected in series with their source regions to form a common source line, the adverse effects of source loading on the output stability of each memory cell can be reduced. In some embodiments, the resistance of the common source line can be further reduced by increasing the doping concentration of the extension portion of the source region of each memory cell, thereby further reducing the source loading effect and improving the operating efficiency of the nonvolatile memory element.

[0083] Although the present application has been disclosed in connection with the above preferred embodiments, it will be evident for those skilled in the art that some modifications and improvements can be made without departing from the spirit and scope of the application. Therefore, the scope of the present application should be limited only by the appended claims.

Claims

1. A non-volatile memory element, characterized in that, include: A semiconductor substrate having a recess extending downward from the substrate surface; A first floating gate is located in the recess, has a base and a sidewall connected to the base, and is electrically isolated from the semiconductor substrate; A first control gate is adjacent to the first floating gate and is electrically isolated from the semiconductor substrate and the first floating gate, respectively. The first drain region is located within the semiconductor substrate in the recess; as well as A common source region is located within the semiconductor substrate in the recess, adjacent to the first floating gate, and includes: The main body is located below the bottom surface of the recess and adjacent to the base; as well as An extension extends upward from the bottom surface, beyond the base, and adjacent to the sidewall, wherein the extension has a higher doping concentration than the main body.

2. The non-volatile memory element of claim 1, wherein the extension has a top surface that is coplanar with the surface of the substrate.

3. The non-volatile memory element of claim 1, wherein the distance between the base and the top of the first floating gate connected to the sidewall is less than or equal to the depth of the recess.

4. The non-volatile memory element as claimed in claim 1, further comprising: The second floating gate is located within the recess and adjacent to the first floating gate, and is electrically isolated from the semiconductor substrate and the first floating gate; and The second control gate is adjacent to the second floating gate and is electrically isolated from the semiconductor substrate, the first floating gate and the second floating gate, respectively.

5. The non-volatile memory element of claim 4 further includes an erase gate located between the first floating gate and the second floating gate, adjacent to the common source region, and electrically isolated from the semiconductor substrate.

6. The non-volatile memory element of claim 1 further includes a spacer wall located on the sidewall of the control gate and covering the top of the first floating gate.

7. The non-volatile memory element of claim 1, wherein the body portion and the extension portion comprise a semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), gallium arsenide (GaAs), and any combination thereof.

8. The non-volatile memory element of claim 1, further comprising a gate dielectric layer, wherein the first floating gate is electrically isolated from the semiconductor substrate by the gate dielectric layer covering a portion of the recess.

9. The non-volatile memory element of claim 8, wherein the gate dielectric layer comprises a dielectric material selected from silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiNO), hafnium oxide (HfO2), and aluminum oxide (AlO2). x The group formed by any combination of the above.

10. A method for manufacturing a non-volatile memory element, comprising: A semiconductor substrate is provided, having a recess extending downward from the surface of the substrate; A floating gate is formed in the recess, having a base and a sidewall connected to the base, and is electrically isolated from the semiconductor substrate; A control gate is formed adjacent to the floating gate and electrically isolated from the semiconductor substrate and the floating gate, respectively. A drain region is formed in the semiconductor substrate within the recess; as well as A common source region is formed in the semiconductor substrate within the recess, adjacent to the floating gate, and includes: The main body is located below the bottom surface of the recess and adjacent to the base; as well as An extension extends upward from the bottom surface, beyond the base, and adjacent to the sidewall, wherein the extension has a higher doping concentration than the main body.

11. The method of manufacturing a non-volatile memory element as claimed in claim 10, wherein the main body and the extension comprise a semiconductor material selected from the group consisting of silicon, germanium, gallium arsenide, and any combination thereof.

12. The method of fabricating a non-volatile memory element as claimed in claim 10, wherein the step of forming the floating gate comprises: An etching process is performed to form a recess in a semiconductor substrate, leaving a protrusion at the bottom of the recess that extends upward from the bottom surface of the recess. A gate dielectric layer is formed to cover the bottom surface and the protrusion; A first conductor layer is formed, covering the gate dielectric layer; and The first conductor layer is patterned to form the floating gate.

13. The method of fabricating a non-volatile memory element as claimed in claim 12, wherein the step of forming the control gate includes: A dielectric storage layer is formed to cover the floating gate and the protrusion; A second conductive layer is formed to cover the dielectric storage layer; The second conductive layer is patterned to form the control gate above the floating gate; as well as At least one gap wall is formed on the control gate and covers the top of the floating gate.

14. The method of fabricating a non-volatile memory element as claimed in claim 13, wherein the step of forming the drain region includes, after forming the floating gate, performing a first ion implantation process on a portion of the bottom surface not covered by the floating gate.

15. The method of fabricating a non-volatile memory element as claimed in claim 13, wherein the step of forming the source region includes performing a second ion implantation process on the protrusion to form the extension in the protrusion and forming the body portion below the protrusion.

16. The method of fabricating a non-volatile memory element as claimed in claim 12, further comprising forming an erase gate above the common source region, thereby electrically isolating it from the semiconductor substrate through the gate dielectric layer.

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