Silicon carbide semiconductor devices with reduced heterointerface resistance

Abstract

In a semiconductor element including a silicon carbide heterostructure, the resistance component generated due to spontaneous polarization at the hetero-matched interface is suppressed, thereby reducing the specific on-resistance of the semiconductor element. A hetero-matched interface (S X ) and 1 × 10 19 cm -3 The tunnel doped region (D T By providing the layer, a carrier transport mechanism by tunneling is realized, and the specific on-resistance of the semiconductor element is kept low.

Description

[Technical Field]

[0001] The present invention relates to the structure of semiconductor devices using heteroepitaxial stacked structures of silicon carbide (SiC), and in particular to the structures of MOSFETs, IGBTs, and JFETs used in power electronics. [Background technology]

[0002] Silicon carbide (hexagonal SiC), which has a hexagonal structure and is represented by 4H-SiC, is widely used as a material for power semiconductor devices due to its excellent physical properties. However, metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs) using 4H-SiC have a high interface state density (D it ) and its channel resistance (R ch ) and deterioration of long-term reliability.

[0003] As a solution to this problem, a semiconductor device structure has been proposed in which a cubic SiC (3C-SiC) layer is stacked on a hexagonal SiC layer, and a gate insulating film is provided on the 3C-SiC layer. Such a semiconductor device structure and one of its manufacturing methods is described in Patent Document 1 (WO2008 / 56698). In Patent Document 1, an extended terrace surface is formed on a part of the surface of hexagonal SiC such as 4H-SiC, and a 3C-SiC layer is formed on top of that, thereby achieving D it According to Non-Patent Document 1, forming a MOS structure on 3C-SiC reduces D it is reduced by more than two orders of magnitude, and 2 ·V ―1 sec -1 Channel mobility (μ ch ) is achieved, and R ch is reduced to less than one-seventh of that of a conventional MOS structure using 4H-SiC. In addition, since the maximum electric field region of the semiconductor element is located in hexagonal SiC, which has a high dielectric breakdown field strength, the structure provided by Patent Document 1 reduces the breakdown voltage (V bwithout compromising the characteristic on-resistance (R on ) can be kept low.

[0004] Patent Document 2 (Japanese Patent No. 6795805) provides a structure for suppressing carrier capture and scattering at a heterocoherent interface in a heteroepitaxially grown SiC layer in a semiconductor device using a stacked structure of 3C-SiC and hexagonal SiC, and a manufacturing method thereof. The heterocoherent interface provided by Patent Document 2 is an interface where cubic and hexagonal SiC single crystals are in contact with each other at the basal planes where the two-dimensional arrangement of the crystal lattices is equivalent. This structure minimizes misfit dislocation density and scattering of carriers drifting parallel to the heterocoherent interface. To form this heterocoherent interface, a seed plane parallel to the basal plane of the crystal lattice and an inclined plane inclined from the basal plane are provided on the hexagonal SiC surface. Two-dimensional nuclei of 3C-SiC are generated on the seed plane, and simultaneously, step-controlled epitaxy is performed on the inclined plane to produce a SiC stack composed of a hexagonal SiC layer and a 3C-SiC layer. By making all interfaces in the SiC stack hetero-matched interfaces and separating the 3C-SiC surface from the hexagonal SiC surface, it is possible to freely arrange semiconductor elements, thereby obtaining a high-performance semiconductor device.

[0005] Patent Document 3 (JP 2025-86831 A) provides a method for producing a SiC stack in which 3C-SiC layers and hexagonal SiC layers are alternately stacked, without requiring strict control of epitaxial growth conditions, substrate processing shape, or special surface treatment processes. This method creates positively and negatively inclined planes inclined from the basal plane of the crystal lattice on the hexagonal SiC surface, controlling the arrangement of the ridge lines at their boundaries. Additionally, the formation of 3C-SiC layers is ensured by creating ridge line apexes that protrude in specific directions. Furthermore, multiple 3C-SiC nucleation sites are provided, and their arrangement is displaced relative to the

[0001] orientation, allowing for flexible control of the film thickness of each SiC layer. This method makes it possible to produce a SiC stack in which 3C-SiC layers and hexagonal SiC layers are alternately stacked to the desired film thickness.

[0006] On the other hand, Non-Patent Document 2 (MVS Handrashekhar, Applied Physics Letters 90, 173509 (2007)) reports on the electrical properties of a stacked structure of 3C-SiC and 4H-SiC, a type of hexagonal SiC, and reports that spontaneous polarization at the hetero-matched interface causes a 9.7 × 10 12 cm -2 It has been pointed out that fixed charges of 2D are generated. These two-dimensional fixed charges prevent the transport of carriers that try to penetrate in the perpendicular direction. That is, negative fixed charges are generated at the heterocoherent interface where the 4H-SiC(0001)Si face and the 3C-SiC(-1-1-1)C face meet, which prevents the transmission of electrons. On the other hand, positive fixed charges are generated at the heterocoherent interface where the 4H-SiC(000-1)C face and the 3C-SiC(111)Si face meet, which prevents the transmission of holes. For this reason, even if R ch Even if the resistance at the heteromatched interface (R X ) increases, and R on This prevents reduction in

[0007] On the other hand, as a method for suppressing spontaneous polarization in a semiconductor crystal having a heteroepitaxial structure, Patent Document 4 (JP Patent Publication No. 2004-22818) discloses a method for suppressing negative charges generated by spontaneous polarization in an InGaP layer by discharging the negative charges into adjacent n + The authors disclose a structure in which the GaAs spacer layer is doped with positive charges to compensate for the band lifting of the heterobarrier, resulting in better transistor characteristics.

[0008] Furthermore, Patent Document 5 (Patent Publication No. 5417693) discloses a method for intentionally suppressing the channel directly under the gate in a heterojunction device of group III nitride semiconductors by controlling the composition of InAlGaN to control the location where two-dimensional electron gas is generated due to spontaneous polarization. This shows that it is possible to suppress the occurrence of spontaneous polarization by intentionally designing the structure of the epitaxial film. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] WO2008 / 56698 publication [Patent Document 2] Patent No. 6795805 [Patent Document 3] Japanese Patent Application Laid-Open No. 2025-86831 [Patent Document 4] Japanese Patent Application Laid-Open No. 2004-22818 [Patent Document 5] Patent No. 5417693 [Non-patent literature]

[0010] [Non-Patent Document 1] H. Uchida, Mater. Sci. Forum, Vols.717-720 pp1109 (2012) [Non-patent document 2] MVSChandrashekhar, Applied Physics Letters 90,173509 (2007) Summary of the Invention [Problem to be solved by the invention]

[0011] As mentioned above, the hetero-matched interface in a structure where 3C-SiC and hexagonal SiC are stacked contains an essential problem that hinders carrier transport. That is, at the hetero-matched interface between hexagonal SiC, which has an asymmetric crystal structure, and 3C-SiC, which has a symmetric crystal structure, the generation of fixed charges due to spontaneous polarization is inevitable. This fixed charge forms a barrier (depletion layer) with high resistance that hinders the transport of specific carriers, and therefore, R on The present invention has been made in view of the above-mentioned problems, and aims to reduce the hetero-interface resistance (R X ) effectively reduces R onThe object of the present invention is to provide a semiconductor device structure in which the following is drastically reduced: [Means for solving the problem]

[0012] The semiconductor element for solving the above problems has the following configuration. [Configuration 1] A silicon carbide laminate film is provided on a substrate, the silicon carbide laminate film having a laminate structure in which a lower single-crystal hexagonal silicon carbide layer and an upper single-crystal cubic silicon carbide layer abut against each other, forming a heterocoherent interface, the heterocoherent interface being parallel to the basal plane of the crystal face of the hexagonal silicon carbide layer, and exposing a section thereof at an included angle of 0.5 degrees or more and 60 degrees or less with respect to the surface of the silicon carbide laminate film, and a portion of the surface of the silicon carbide laminate film including the section of the heterocoherent interface is doped with ionized impurities of 1×10 19 cm -3 a first conductivity type tunnel doped region doped with impurities at a concentration equal to or greater than the concentration of impurities in the tunnel doped region, a portion of the hexagonal silicon carbide layer included in the tunnel doped region being in contact with a drift region made of a hexagonal silicon carbide layer of the first conductivity type doped with impurities at a lower concentration than the tunnel doped region, and a portion of the cubic silicon carbide layer included in the tunnel doped region being in contact with a well region of a second conductivity type, a first electrode being in contact with a portion of the surface of the well region via a contact region of the first conductivity type so as to form an ohmic contact, a portion of the surface of the cubic silicon carbide layer constituting the well region being a channel separating the contact region of the first conductivity type and the tunnel doped region, a control electrode being adjacent to an upper portion of the channel, and a second electrode being in contact with either the surface of the hexagonal silicon carbide layer of the first conductivity type or the underside of the substrate so as to form an ohmic contact. [Configuration 2] The semiconductor device according to Configuration 1, wherein the well region intersects with a heteroaligned interface. [Configuration 3] The control electrode according to the first aspect and a semiconductor element characterized in that the insulating film is disposed between the first and second electrodes and adjacent to the channel. [Configuration 4] The surface of the cubic silicon carbide layer is a silicon surface, the first conductivity type is n-type, and the second conductivity type is p-type. The semiconductor element according to configuration 1 . [Configuration 5] A semiconductor device according to any one of Configurations 1 to 4, wherein the surface of the 3C-SiC layer adjacent to the control electrode is parallel to the hetero-matched interface. [Effects of the Invention]

[0013] By using the configuration provided by the present invention, a low D it Since channels are formed in the 3C-SiC layer, which leads to μ ch becomes higher, and R ch Furthermore, if the hetero-matched interface is arranged to intersect with the well region, the maximum electric field region (the bottom end of the well region) when a voltage is applied between the first and second electrodes is located within the hexagonal SiC layer, achieving a high V b This can be achieved.

[0014] By applying the semiconductor device structure provided by this invention to MOSFETs, IGBTs, and JFETs, it is possible to arbitrarily spread the potential barrier induced by the depletion layer generated at the hetero-interface between 3C-SiC and hexagonal SiC to the channel formed below the control electrode by adjusting the thickness of the 3C-SiC layer. The threshold voltage (V th According to Non-Patent Document 1, the fixed charge density generated at the heterointerface between 3C-SiC and 4H-SiC is 9.7 × 10 12 cm ―2 Therefore, the ionized impurity concentration of the second conductivity type well region is 1 × 10 17 cm ―3 Assuming that the depletion layer extends equally upward and downward, the width of the depletion layer is 970 nm. If the depletion layer expands equally upward and downward, a 3C-SiC layer with a thickness of less than 485 nm will be fully depleted, and V th On the other hand, as long as the thickness of the 3C-SiC layer exceeds 485 nm, the channel is not depleted, so V thThis phenomenon can be used to measure the V th This can be corrected by increasing or decreasing the thickness of the 3C-SiC layer.

[0015] As mentioned above, the V th changes depending on the thickness of the 3C-SiC layer. If a 3C-SiC layer surface inclined relative to the basal plane of the 4H-SiC layer (inclined surface of the 3C-SiC layer) is used, the distance between the hetero-matching interface and the channel will inevitably vary depending on the location of the control electrode. th In contrast, in the structure of the semiconductor device provided by the present invention, the surface of the 3C-SiC layer where the channel is exposed can be made parallel to the basal plane (a non-inclined surface of the 3C-SiC layer), so that the V th This makes it possible to maintain high accuracy and precision.

[0016] Unlike the inclined surface of the 3C-SiC layer, the non-inclined surface of the 3C-SiC layer does not have a step-and-terrace structure and is atomically smooth. Therefore, when using a structure in which the control electrode and the channel are separated by an insulating film, such as in MOSFETs and IGBTs, by contacting the insulating film with the non-inclined surface of the 3C-SiC layer, carrier scattering factors are suppressed due to the improved smoothness, thereby reducing μ ch Further improvement of R ch A further reduction in is realized.

[0017] Next, the function of the tunnel doping region provided in the present invention will be explained. As mentioned above, fixed charges are generated at the hetero-matched interface where the 3C-SiC layer and the hexagonal SiC layer meet. This fixed charge generates a repulsive force against carriers of the same polarity (electrons or holes), forming a depletion layer. In other words, carriers having the same charge as the fixed charge at the hetero-matched interface cannot penetrate the hetero-matched interface. For example, when the surface of the SiC laminated film constituting a semiconductor device is the Si face, the Si face of the hexagonal SiC layer and the C face of the 3C-SiC layer meet at the hetero-matched interface, forming a negative fixed charge. This hetero-matched interface therefore prevents electrons from penetrating. On the other hand, when the surface of the SiC laminated film is the C face, the C face of the hexagonal SiC layer and the Si face of the 3C-SiC layer meet at the hetero-matched interface, forming a positive fixed charge. This hetero-matched interface therefore prevents holes from penetrating. In other words ... R ch Even if R is reduced, if the polarity of the carriers matches the polarity of the fixed charges at the heterocoherent interface, R X The increase in R on It becomes difficult to reduce.

[0018] However, the semiconductor device structure provided by the present invention offsets the fixed charge by intentionally adding ionized impurity elements to the vicinity of the hetero-matched interface as a tunnel doping region, making it possible to reduce the depletion layer. However, if impurity elements are added to the entire matched interface, the potential distribution in the well region becomes non-uniform, and the V of the semiconductor device b and V thThis leads to secondary problems such as impaired stability and controllability of the hetero-matched interface. Therefore, the tunnel-doped region is formed only near the surface where the hetero-matched interface intercept is exposed. As shown in Patent Documents 2 and 3, the location where the 3C-SiC layer is formed can be precisely determined by the position of the groove formed on the surface of the hexagonal SiC layer, so the hetero-matched interface intercept can be arbitrarily exposed on the surface of the tunnel-doped region. Furthermore, the thickness and impurity concentration of the tunnel-doped region can be precisely determined using ion implantation techniques, etc., so the effects of the present invention can be realized with high reproducibility. Furthermore, the electric field acting on the tunnel-doped region during operation of the semiconductor device can be sufficiently suppressed by using known techniques that can be implemented by those skilled in the art, such as the placement of a well region or the provision of an electric field relaxation structure.

[0019] Next, the tunnel doped region is R X According to Non-Patent Document 2, the fixed charge at the hetero-matched interface of 3C-SiC / 4H-SiC is 9.7 × 10 12 cm -2 The tunnel doped region reduces the depletion layer caused by the fixed charge by adding ionized impurities of a different polarity to the fixed charge at the hetero-matched interface. The width of the depletion layer depends on the impurity concentration (n T ) is inversely proportional to n T 1×10 18 cm -3 Then, w x is 97 nm, which prevents carriers from penetrating. T 1×10 19 cm -3 If that's the case, w x The distance between the n-doped and n-doped regions is 9.7 nm or less, allowing carriers to tunnel through the depletion layer. T For the tunneling current density through the hetero-matched interface (J T ) indicates the upper limit of n T is 1×10 18 cm ―3 In the following, J T is 10 ―22 A cm―2 However, n T 1×10 19 cm ―3 In this case, J T is 0.1A·cm ―2 It increases to n T 5×10 19 cm ―3 When increasing to J T is 1000A·cm ―2 In addition, this J T does not mean the current density that actually penetrates the hetero-matched interface, but means the upper limit of the current transport capacity of the hetero-matched interface. In other words, the current density when the channel or drift region is in a conductive state is J T If it is lower than R X means that it can be ignored.

[0020] Next, we will explain the correlation between the surface polarity of a hexagonal SiC substrate and the conductivity type of each component of a semiconductor device. The semiconductor device provided by the present invention contains a heterocoherent interface that generates fixed charges. The polarity of the fixed charges is affected by the microscopic structure of the heterocoherent interface where 3C-SiC and hexagonal SiC meet. For example, if the surface polarity of a hexagonal SiC substrate is the (0001) Si plane, the hexagonal SiC layer constituting the SiC laminate film formed on top of it will have the (0001) Si plane oriented upward. Therefore, the 3C-SiC layer stacked on top of the hexagonal SiC layer will necessarily expose the (111) Si plane on its surface. However, its lower surface, the (-1-1-1) C plane, forms a heterocoherent interface with the (0001) Si plane of the hexagonal SiC layer. At this heterocoherent interface, the cation plane faces upward and the anion plane faces downward, resulting in the formation of negative fixed charges. Therefore, it is necessary to add positively charged impurity ions to the tunnel doping region to offset the negative fixed charge. Therefore, the first conductivity type is n-type and the second conductivity type is p-type, which inevitably results in the formation of an n-type channel below the gate electrode. In this case, it is desirable to add at least one of nitrogen (N) or phosphorus (P), which are typical donor impurities that form positively charged ions, to the first conductivity type region. On the other hand, if the polarity of the surface of a hexagonal SiC substrate is the (000-1) C-plane, the first conductivity type is p-type and the second conductivity type is n-type, resulting in the formation of a p-type channel below the gate electrode. In this case, it is desirable to add at least one of aluminum (Al) or boron (B), which are typical acceptor impurities that form negatively charged ions in SiC, to the first conductivity type region.

[0021] At first glance, the configuration of the present invention appears similar to the structures disclosed in Patent Documents 2 and 3. However, the present invention is based on a completely new technical concept for solving the problem of "resistance due to spontaneous polarization at heteroepitaxial interfaces," which Patent Documents 2 and 3 did not recognize. A clear difference from Patent Documents 2 and 3 lies in its objectives. Patent Document 2 treats the slice of the heterocoherent interface exposed on the surface of a single-crystal SiC laminate film simply as the boundary between different device regions, and its main objective is the integration of heterogeneous devices. Patent Document 3, on the other hand, aims to enable the formation of a 3C-SiC layer free of double positioning boundaries (DPBs) at predetermined locations without requiring strict control of the hexagonal SiC surface tolerance, and furthermore, to enable the stacking of a hexagonal SiC layer on a 3C-SiC layer. Therefore, Patent Documents 2 and 3 do not recognize the electrical issues inherent in the heterocoherent interface itself (depletion layer due to spontaneous polarization), and do not disclose or suggest the idea of ​​intentional doping to improve the characteristics of the heterocoherent interface. In contrast, the present invention uses hetero-matched interface resistance (R X The essential feature of this method is the formation of a highly doped region (tunnel doped region) that imparts a specific conductivity type to the region containing the exposed hetero-matched interface, with the clear objective of reducing the conductivity type.

[0022] It may also be possible to combine the structure shown in Patent Document 2 with the concept of "a configuration in which fixed charges that cause spontaneous polarization are compensated for with charges caused by impurities" shown in Patent Document 4. However, this combination is not easily conceivable for those skilled in the art. The reasons are as follows. First, Patent Document 2 describes R XSince the present invention does not address the above problem but aims to integrate heterogeneous devices, there is no motivation for a person skilled in the art to apply the technology of Patent Document 4, which addresses a different problem, to the structure of Patent Document 2. Second, Patent Document 4 differs significantly from the present invention in both the material system (InGaP) and the doping method (during crystal growth). Applying technology from a different field and a different manufacturing process—the addition of ionized impurities limited to the surface—to solve the unique problems inherent in SiC heterocoherent interfaces represents a technological leap. Furthermore, Patent Document 4 has a typical vertical structure, with the interface buried internally. In contrast, the present invention has a unique structure in which the heterocoherent interface and the SiC stacked film surface are intentionally made non-parallel, and a section of the heterocoherent interface is exposed on the SiC stacked film surface. Therefore, the specific method for realizing a structure that solves the problem is completely different. More specifically, Patent Document 4 provides a method for alleviating the effects of the potential barrier by inserting a "narrow band gap spacer layer" between the base layer and the InGaP layer, but this is conceived from the perspective of avoiding the occurrence of polarization (use of a disordered layer) or bypassing and alleviating the barrier that occurs (insertion of a spacer layer). On the other hand, the present invention uses the hetero-matched interface where spontaneous polarization occurs as is, and attempts to solve the problem from the perspective of directly offsetting and neutralizing the fixed charge itself present at the hetero-matched interface by impurity doping limited to the surface layer. If the method disclosed in Patent Document 4 were to be applied to the present invention, it would mean replacing the entire SiC hetero-matched interface with "another material that does not polarize," which would negate the R that is the premise of the present invention. ch This would make it impossible to achieve the objectives of reducing noise and improving long-term reliability.

[0023] Furthermore, the SiC laminated film used in the present invention can only be constructed with a one-to-one bond between silicon (Si) and carbon (C), and it is impossible to suppress spontaneous polarization by the means of "composition control" proposed in Patent Document 5. [Brief explanation of the drawings]

[0024] [Figure 1]FIG. 1 is a diagram showing the relationship between the tunneling current density (JT) and the ionized impurity concentration (nT) in the tunnel doped region to show the effect of the tunnel doping of the present invention. [Figure 2] 1 is a cross-sectional view showing an example of the configuration of a lateral n-channel MOSFET according to a first embodiment of the present invention. [Figure 3] FIG. 10 is a cross-sectional view showing the configuration of a lateral n-channel MOSFET according to a modified example of the first embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views showing an example of a homoepitaxial growth process for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 5] 1A to 1C are cross-sectional views showing an example of a groove processing step for manufacturing lateral n-channel MOSFETs according to the first embodiment of the present invention and its modifications. [Figure 6] 1A to 1C are cross-sectional views showing an example of an early stage of a heteroepitaxial growth process for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 7] 1A to 1C are cross-sectional views showing an example of an intermediate stage of a heteroepitaxial growth process for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 8] 1A to 1C are cross-sectional views showing an example of a state after a heteroepitaxial growth step for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a well formation step for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 10] 1A to 1C are cross-sectional views showing an example of a donor impurity doping step for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of an acceptor impurity doping step for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 12]1A to 1C are cross-sectional views showing an example of a gate insulating film and a gate electrode formation step for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of a source electrode and a drain electrode forming step for manufacturing a lateral n-channel MOSFET according to the first embodiment of the present invention and its modifications. [Figure 14] FIG. 10 is a cross-sectional view showing an example of the configuration of a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 15] FIG. 10 is a cross-sectional view illustrating an example of a homoepitaxial growth process for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 16] FIG. 10 is a cross-sectional view showing an example of a groove processing step for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 17] 5A to 5C are cross-sectional views illustrating an example of a heteroepitaxial growth process for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 18] FIG. 10 is a cross-sectional view illustrating an example of a well region forming step for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 19] FIG. 10 is a cross-sectional view illustrating an example of a donor impurity doping step for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 20] FIG. 10 is a cross-sectional view illustrating an example of an acceptor impurity doping step for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 21] 10A to 10C are cross-sectional views showing an example of a gate insulating film and gate electrode step for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. [Figure 22] 10A to 10C are cross-sectional views showing an example of a source electrode and drain electrode step for manufacturing a vertical n-channel MOSFET according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to cross-sectional views. In each cross-sectional view illustrating the structure and steps of the embodiment, parts having the same or similar functions or properties are designated by the same reference numerals. However, the cross-sectional views are schematic views for illustrating the positional relationships of minute regions, and the thicknesses, dimensions, and dimensional ratios thereof differ from those of the actual objects. Furthermore, the relationships and ratios of the respective dimensions and thicknesses differ between cross-sectional views.

[0026] As used herein, the term "region" does not necessarily refer to a region that can be distinguished by shape or material. It may also refer to a function or property that manifests depending on the operating conditions of a semiconductor device, and therefore such regions may not be clearly indicated in the drawings. For example, a "drift region" is a section formed between a first electrode and a second electrode, where the width of the depletion layer varies. Furthermore, the drift region located between well regions exhibits behavior equivalent to the JFET channel due to the depletion layer extending from the well region, and therefore this portion is referred to as the "JFET region." Because the channel manifests itself depending on the voltage applied to the gate electrode, it is not clearly distinguishable by shape. However, in Figures 2, 3, and 14, which are cross-sectional views showing the structure of the embodiment, it is shown as a channel (Ch) separated by a dashed line.

[0027] In this specification, "conductivity type" means either an n-type semiconductor (electrons are majority carriers) or a p-type semiconductor (holes are majority carriers) of an extrinsic semiconductor, and when the "first conductivity type" is an n-type semiconductor, the "second conductivity type" means a p-type semiconductor. On the other hand, when the "first conductivity type" is a p-type semiconductor, the "second conductivity type" means an n-type semiconductor. "First conductivity type impurities" mean ionized impurities added to a first conductivity type region, and "second conductivity type impurities" mean ionized impurities added to a second conductivity type region. For example, when the first conductivity type is n-type, the first conductivity type impurities are donor impurities, and the different second conductivity type impurities are acceptor impurities. In addition, in this specification, n + , or p +The notation + means that the concentration of electrons or holes is 10 times or more higher relative to the region without the + notation.

[0028] In this specification, a voltage is applied between the first electrode and the second electrode from the outside, and the control electrode is a terminal to which a potential difference is applied to the first electrode or the second electrode in order to control the value of the current flowing between the first electrode and the second electrode. For example, if the semiconductor element is an n-channel MOSFET or JFET, the first electrode corresponds to the source electrode, the second electrode corresponds to the drain electrode, and the control electrode corresponds to the gate electrode, and if the semiconductor element is an n-channel IGBT, the first electrode corresponds to the emitter electrode, the second electrode corresponds to the collector electrode, and the control electrode corresponds to the gate electrode.

[0029] This specification uses Miller indices to indicate the plane orientation of SiC crystals. Normally, when a Miller indices has a negative value, a horizontal line (bar) should be written above the corresponding number, but since this is not possible, within the scope of this specification, the corresponding number is expressed by adding a minus sign "-" before it.

[0030] In this specification, when the terms "upper" and "above" are used to indicate relative positional relationships, "upper" refers to the normal direction of the surface of the substrate where the SiC laminated film is in contact with the substrate, and when the terms "lower", "lower", "bottom surface", and "bottom end" are used, "lower" refers to the normal direction of the surface of the substrate where the SiC laminated film is not provided.

[0031] In the description of the embodiment of the invention, the steps for realizing the structure of the semiconductor element provided by the present invention are also mentioned. However, the patterning step for limiting the impurity doped region, the thermal oxidation step for forming the gate insulating film, the electrode formation step, the activation step after ion implantation, the cleaning step, etc. are similar to the conventional semiconductor element manufacturing steps and can be performed by a person skilled in the art, so detailed description thereof will be omitted in this specification.

[0032] (Structure of the first embodiment) As a first embodiment of a semiconductor device provided by the present invention, the structure of a lateral n-channel MOSFET will be described using the cross-sectional structure shown in FIG. 2. In this embodiment, a gate electrode (M G ) corresponds to the control electrode, and the source electrode (M S ) corresponds to the first electrode, and the drain electrode (M D ) corresponds to the second electrode. G ) is the upper layer of the adjacent SiC laminated film, the 3C-SiC layer (E C ) to form an n-type channel near the surface, the well region (W) is made p-type, and the 4H-SiC layer (E H The drift region in the substrate (U) is n-type. That is, the first conductivity type is n-type and the second conductivity type is p-type. H ) in the first embodiment. H ) conductivity type is preferably p-type or insulating. Alternatively, if it is difficult to obtain a p-type or insulating substrate, H ) a p-type 4H-SiC layer may be formed on the MOSFET. Each region of the MOSFET extends in the [1-100] direction (depth direction in Fig. 2), and its width corresponds to the channel width. In addition, a well region (W), a tunnel doped region (D) are formed along the [11-20] direction (right direction in Fig. 2). T ), and the drift region (in the 4H-SiC layer) is adjacent.

[0033] <Substrate> The substrate (U H ) is preferably single-crystal 4H-SiC because the single-crystal 4H-SiC layer (E H ) on the substrate (U H ) and the orientation of the basal plane (BP) is 4H-SiC substrate (U H ) surface orientation. In order to obtain a high-quality homoepitaxial growth layer, it is necessary to use a 4H-SiC substrate (U HThe surface of the substrate (U) is preferably a Si polar plane tilted at a certain angle (θ) from the basal plane (BP) corresponding to the (0001) plane to a crystal orientation such as the [11-20] direction. In this case, θ can be selected in the range of 0.5 to 60 degrees. H ) When the tolerance of the surface is large, the structural feature of the present invention, the 3C-SiC layer (E C ) and 4H-SiC layer (E H ) of the heterocoherent interface (S X ) position accuracy deteriorates, so it is desirable that θ is 1 degree or more. On the other hand, if θ exceeds 60 degrees, the tunnel doped region (D) that should include the hetero-matched interface (X) T ) needs to be increased in depth, and the tunnel doped region (D T ) requires an increase in the acceleration energy and dose of ion implantation. H ) and the inclined surface of the 3C-SiC layer (S CI ) exposes non-polar and semi-polar surfaces with different physical properties than normal, so the V th This may lead to instability of the SiC film and an increase in leakage current from the SiC film surface. Considering that the surface of commercially available 4H-SiC wafers is tilted 4 degrees from the basal plane (BP) to the [11-20] orientation, it is most preferable to set θ to 4 degrees from the viewpoint of substrate availability.

[0034] <Arrangement of 3C-SiC layer and 4H-SiC layer, matching interface> Substrate (U H ) on which a 4H-SiC layer (E H ) is formed, and a 3C-SiC layer (E C ) is placed. Also, the 3C-SiC layer (E C ) does not include the double positioning boundary (DPB), and is formed by the 4H-SiC layer (E H ) must be in contact with the surface of the SiC laminated film. Therefore, the hetero-coherent interface (X) is inclined in the [-1-120] direction from the surface of the SiC laminated film, and the inclination angle is 4 degrees, which is the same as θ. In addition, the hetero-coherent interface (X) must be in contact with the surface of the SiC laminated film at its intercept (SX The angle between the surface of the SiC laminated film and the hetero-matched interface (X) is equal to the angle between the substrate (U H ) corresponds to the surface inclination angle θ.

[0035] <Concentration and thickness of homoepitaxial layer> Substrate (U H 4H-SiC layer (E H ) is n-type, and the concentration of donor impurities to be added (n H ) is the required V b For example, the V b If the voltage is 600V or more, H 1×10 17 cm ―3 It is desirable to set it to V b If the voltage is 1200V or more, H 6×10 16 cm ―3 It is desirable to do the following:

[0036] <Surface orientation of 4H-SiC and 3C-SiC layers and sections of the coherent interface> 4H-SiC layer (E H ) is a surface (S) tilted 4 degrees from the basal plane (BP) in the [11-20] direction. H ) and the 3C-SiC layer (E C ) is a 4° tilted surface (S CI ) and the non-inclined surface (S CJ ) is exposed. The surface of the 4H-SiC layer (S H ) and the inclined surface of the 3C-SiC layer (S CI ) boundary is the intercept (S X ) is equivalent to

[0037] <Width of 3C-SiC and 4H-SiC layers> The surface width of the 4H-SiC layer along the [11-20] direction (L H ) is the R on and V bThe optimum value must be selected taking into consideration the conflicting relationship between the MOSFET cell density (i.e., current density) and the width (L C ) must be determined taking into consideration the gate length and the arrangement of the source electrode. T ) is the intercept of the heterocoherent interface (S X ) must be formed to include L C and L H is the width of the tunnel doped region (L T ) must also be added in the design. H and L C It is desirable to select the optimum value for each of L within the range of 1 μm or more and 100 μm or less. C If L is less than 1 μm, the channel length is limited, making the short channel effect more likely to occur. H The longer the V b will be higher, but L H If V exceeds 100 μm, the resistance of the drift region increases significantly. b is set to 600V, and n H 1x10 17 cm -3 When doing so, L H It is desirable that the thickness is 7 to 10 μm.

[0038] <Well region arrangement and acceptor concentration> In this embodiment, acceptor impurities are added to the well region (W). As the acceptor impurities to be added to the well region (W), one or more of aluminum (Al) and boron (B) can be selected. S ) and the drain electrode (M D When a voltage is applied between the well region (W) and the drift region (N), it is desirable for the depletion layer to expand mainly toward the drift region. W ) is n H It is desirable that the lower end of the well region (W) is made of a 4H-SiC layer (E H) reduces the electric field strength reaching the surface of the well region, resulting in a V as high as that of a conventional lateral MOSFET using a 4H-SiC substrate. b It is possible to obtain

[0039] <Drift region arrangement and drain electrode> Tunnel doped region (D T ) and the drift region, and the 4H-SiC layer surface (S H ) to the drain electrode (M D ) contacts the drain electrode (M D ) contacts the 4H-SiC layer surface (S H ) to which a high concentration of donor was added + Drain contact region (D D ) can reduce the drain contact resistance.

[0040] <Impurity concentration in the tunnel doped region> Tunnel doped region (D T ) is provided to separate the surface of the drift region from the surface of the well region (W). T ) has a heterocoherent interface intercept (S X ) is exposed, so the tunnel doped region (D T ) contained in the 4H-SiC layer (E H ) is adjacent to the drift region, and the tunnel doped region (D T ) contained in the 3C-SiC layer (E C The tunnel doped region (D) is adjacent to the channel (Ch) formed in the well region (W). T ) is an n-type semiconductor, and the donor concentration (n Td ) is 1×10 19 cm -3 That's all. n Td The higher the value of R, the smaller the width of the depletion layer extending from the hetero-matched interface (X). X The n in the tunnel doped region can be reduced. Td 1×10 19 cm-3 The effect of the present invention can be obtained if the above is satisfied, but X To reduce the donor concentration to 5 × 10 19 cm -3 It is desirable to set the tunnel doping region (D T ) should be 50 nm or more thick, including the upper (3C-SiC layer) and lower (4H-SiC layer) of the hetero-matched interface (X). In this case, the width (L T ) is the thickness of the tunnel doped region (d T ) and the inclination angle θ. For example, if θ is 4 degrees and d T If 0.1 μm, L T The lower limit of d T can be defined as 1.4 μm divided by the tangent of θ.

[0041] <Gate electrode arrangement and gate insulating film> Gate electrode (M G ) is the tunnel doped region (D T ) and n (described below) + Source contact area (D N The surface of the 3C-SiC layer is included in a well region (W) having a p-type conductivity, and is provided adjacent to the surface of the 3C-SiC layer that separates the gate electrode (M G When a positive voltage is applied to the 3C-SiC layer, an n-type inversion layer is formed, which functions as a channel (Ch). CJ ) adjacent to the gate electrode (M G )but If it is established , the distance between the hetero-matched interface (X) and the channel (Ch) is kept constant, so V th The fluctuation of μ ch Therefore, in this embodiment, the gate electrode (M G ) is the gate insulating film (Z G ) through the non-inclined surface (S CJ ) and the thickness of the gate insulating film (d z ) is the dielectric breakdown field strength and the gate electrode (M G) can be determined by considering the maximum gate voltage applied to the th Considering the need to obtain stable long-term z It is desirable that the thickness is about 30 to 60 nm.

[0042] <Channel mobility> According to the first embodiment, the gate insulating film (Z G The channel (Ch) formed directly below the 3C-SiC layer is located within the 3C-SiC layer. ch According to Non-Patent Document 1, the channel mobility at room temperature is 300 cm 2 ·V -1 sec -1 Even when taking into consideration the difference in effective mass of electrons on the 3C-SiC (100) surface on which the channel of Non-Patent Document 1 is formed and the 3C-SiC (111) surface on which the channel (Ch) of the present invention is formed, in this embodiment, 2 ·V -1 sec -1 More than μ ch Therefore, R ch This can be reduced to less than one-fourth of that of conventional 4H-SiC MOSFETs.

[0043] <Source electrode> In this embodiment, the n-type source contact region (D N ) through the source electrode (M S ) is in contact with the well region (W). Furthermore, a p-type source contact region (D P ) and the source electrode (M S By providing it below the n-type source contact region (D N ) and the donor impurity concentration in the p-type source contact region (D P The acceptor impurity concentration in the p-type source contact region (D P ) is the 4H-SiC layer (E H), the potential of the well region (W) can be reliably stabilized.

[0044] <Resistance component> When an n-channel MOSFET is used for power control, it is usually S ) is grounded, and the drain electrode (M D ) is connected to a load. on The main component of is the contact resistance between the source and drain electrodes (R con ), channel resistance (R ch ), hetero-matched interface resistance (R X ), drift resistance (R DRIFT ) are the four resistance components, but the effect of the present invention is ch The high channel mobility of the 3C-SiC region reduces the R X impurity concentration in the tunnel doped region is 5×10 19 cm -3 As described above, in this embodiment, the V b While maintaining R on It is possible to further reduce

[0045] (Modification of the first embodiment) 3 shows a modified example of the first embodiment of the present invention. When it is possible to keep the distance between the hetero-matched interface (X) and the surface of the well region (W) wider than the width of the depletion layer due to the fixed charge at the hetero-matched interface (X), it is not always necessary to form the channel (Ch) on the non-inclined surface (S) of the 3C-SiC layer. CJ ) and does not need to be formed on the inclined surface (S CI ) can also be formed. In order to alleviate the electric field on the drift region surface, a RESURF region (RSF) made of p-type conductivity may be provided on a part of the drift region surface. Furthermore, a tunnel doped region (D T ) to the bottom of the well region (W), and the tunnel doped region (D T) can also be used to reduce the electric field that reaches the adjacent 4H-SiC layer (E H ), in which case p + Source contact area (D P ) on the surface of the 4H-SiC layer (S H ) can be abutted against p + Source contact area (D P This eliminates the need for multi-stage ion implantation steps when forming the ion-implanted layer.

[0046] (Manufacturing process of the first embodiment) The manufacturing process of the n-type channel MOSFET of the first embodiment will be described below with reference to FIGS.

[0047] <Substrate> A commercially available single-crystal 4H-SiC wafer was used as the substrate (U H ) is used. The wafer surface is tilted 4 degrees from the (0001) Si surface toward the [11-20] direction, and a semi-insulating wafer with a resistivity of 3000 ohm-cm or higher is selected. If semi-insulating wafers are difficult to obtain, a p-type wafer can be selected, or an n-type SiC laminated film can be formed on a p-type 4H-SiC homoepitaxial growth layer on top of the substrate.

[0048] <Homoepitaxial growth process> As shown in the cross-sectional structure of Figure 4, the substrate (U H ) on a 4H-SiC layer (E H In this process, Si source gas and C source gas diluted with hydrogen are introduced into the reactor, and the pressure is kept constant between 100 hPa and 300 hPa, and the temperature is kept constant between 1550 °C and 1680 °C for a predetermined time. H ) on a 4H-SiC layer (E H ) can be homoepitaxially grown. In this case, by mixing a certain amount of nitrogen source gas into the gas introduced into the reactor, the 4H-SiC layer (E HIt is also possible to adjust the donor impurity concentration of the 4H-SiC layer (E H The thickness of the layer 10 can be adjusted to a desired value by adjusting the homoepitaxial growth time.

[0049] <Grooving process on the surface of the 4H-SiC layer> Next, as shown in the cross-sectional structure of Figure 5, grooves (V) are formed in part of the surface of the 4H-SiC growth layer. The grooves (V) are formed in accordance with the manufacturing methods provided by Patent Documents 2 and 3. H ) and the 3C-SiC layer (E C The grooves (V) processed in this process may be formed parallel to the [1-100] direction as in Patent Document 2, but as in Patent Document 3, by forming a series of grooves deviated by one degree or more from the [1-100] direction to either the [11-20] direction or the [-1-120] direction, the 3C-SiC layer (E C The width of the grooves (V) formed in this process depends on the temperature of the heteroepitaxial growth process described later, but it is sufficient to satisfy the condition for suppressing the formation of 3C-SiC at the bottom of the grooves (V). Therefore, the required width of the non-inclined surface of the 3C-SiC layer (S CJ ) or less. The depth of the groove (V) is determined based on the required thickness of the 3C-SiC layer (t c ) or more. In this process, the 4H-SiC layer (E H At the same time as forming the grooves (V) on the surface, it is also possible to form alignment marks that serve as references for aligning the various regions that make up the MOSFET.

[0050] <3C-SiC heteroepitaxial growth process> Next, the 4H-SiC layer (E H ) on a 3C-SiC layer (E C ) is heteroepitaxially grown. In carrying out this heteroepitaxial growth, the same CVD method as in homoepitaxial growth can be used. However, the temperature during heteroepitaxial growth should be adjusted to the temperature required for the desired 3C-SiC layer (E C) shape, because the temperature in the epitaxial growth process affects the degree of supersaturation at the growth surface and the critical width (w c As shown in the cross-sectional structure of Figure 6, during the heteroepitaxial growth process, the 4H-SiC layer (E H The width of the surface (WT) parallel to the basal plane (BP) of the 4H-SiC layer extending in the [11-20] direction from the groove (V) on the surface (WT) is w c Once the two-dimensional nucleus (η) of 3C-SiC is generated, a 3C-SiC layer (E C ) surface width is w c As shown in the cross-sectional structure of Fig. 7, when the temperature exceeds , new two-dimensional nuclei (η) of 3C-SiC are formed on the non-inclined surface (S CJ ) and a further 3C-SiC layer (E C ) growth is repeated. Therefore, the width (L CJ ) is w c and the width of the inclined surface of the 3C-SiC layer (L CI ) is t c can be defined geometrically as divided by the tangent of θ.

[0051] Also, w c is determined by the degree of supersaturation, so the temperature during heteroepitaxial growth (T epi ) shows a positive dependence on T epi At 1440℃, L CJ is approximately 7 μm. epi If we set the temperature at 1480℃, L CJ extends to about 16 μm, and T epi is L at 1500℃ CJ Therefore, as in the first embodiment, the gate electrode is formed on the inclined surface of the 3C-SiC (S CI ) and if it is necessary to keep the hetero-matched interface (X) away from the channel (Ch), Tepi By performing heteroepitaxial growth while maintaining a constant low temperature, L CJ While narrowing t c By increasing L CI On the other hand, the non-inclined surface (S CJ ) on the gate electrode (M G ) is set up, T epi By performing heteroepitaxial growth while maintaining the temperature at a low level, a predetermined t c 3C-SiC layer (E C ) is formed. For example, T epi If this is carried out at 1440°C, CJ is about 7 μm. epi Further heteroepitaxial growth was performed at 1480°C. CJ The non-inclined surface (S CJ ) is suppressed, so that the formation of two-dimensional nuclei (η) of 3C-SiC on the surface is suppressed. c becomes constant, and L CI While suppressing the expansion of L CJ That is, in the present invention, T epi By L CI and L CJ It is possible to adjust the ratio of the 3C-SiC layer (E C ) can be adjusted to a desired value.

[0052] <Well region formation> Next, as shown in the cross-sectional structure of FIG. 9, a p-type well region (W) is formed in a predetermined location of the SiC laminated film. The well region (W) can be formed by ion implantation of aluminum (Al) or boron (B), which are acceptor impurities. However, since B has a low activation rate in the activation step described below and there is a possibility of out-diffusion, it is desirable to use Al as the acceptor impurity. However, it is desirable that the bottom end of the well region (W) is located deeper than the hetero-matched interface (X), and the acceptor impurity concentration (n W Since it is desirable to keep the ion implantation temperature constant, a box profile that penetrates the hetero-matched interface (X) is formed by multi-stage implantation with appropriately selected dose and acceleration energy. Note that, to avoid the structure of the matched interface being destroyed by ion implantation and to maintain a high activation rate of the implanted Al, it is desirable to perform the ion implantation in this process at 700°C or higher.

[0053] <Tunnel doped region, n + Contact Area> Next, as shown in the cross-sectional structure of FIG. 10, the drain electrode (M D ) abutting n + Drain contact region (D D ) and the source electrode (M S ) abutting n + Source contact area (D N ), and the tunnel doped region (D T ) are formed by ion implantation. Nitrogen (N) or phosphorus (P) can be selected as the donor impurity to be implanted into each region. N substitutes for the C position of the SiC crystal lattice, and P substitutes for the Si position. Therefore, by implanting both in the same region, the solid solubility of each impurity is exceeded, resulting in a 5×10 19 cm -3It is possible to achieve a donor concentration of 500 keV or more. In order to improve the activation rate of the donor impurities and to avoid destruction of the crystal lattice, it is desirable to perform the ion implantation of N and P at 500°C. Furthermore, since the region where the donor impurities should be implanted is about 0.1 μm deep from the surface of the SiC laminated film, the acceleration energy of N ions is selected to be 60 keV or less, and the acceleration energy of P ions is selected to be 120 keV or less. The total dose of each ion is set to 5 × 10 14 cm -2 By setting it to 5×10 or more, 20 cm -3 A donor-doped region with a concentration exceeding 1000 ppm can be formed.

[0054] <p + Contact Area> The tunnel doped region (D T ) and n + Contact area (D N , D D Before and after the step of forming the source electrode (M S ) is abutted on the well region surface p + Source contact area (D P ) is provided. However, p + Source contact area (D P ) is the 4H-SiC layer (E H ) by multi-stage implantation of Al ions, as in the well region formation process. + Source contact area (D P ) in the well region (W) of the 4H-SiC layer (E H ), Al ions may be implanted only into the surface layer.

[0055] <Activation annealing> Well region (W), each contact region (D P ,D N , D D ), and the tunnel doped region (D TIn order to activate the donor impurities and acceptor impurities implanted in the GaN layer, activation annealing is performed at a temperature of 1650° C. or higher.

[0056] <Gate insulating film formation and gate electrode formation> Following the activation annealing step, as shown in the cross-sectional structure in Figure 12, + Source contact area (D N ) and tunnel doped region (D T ) is separated from the well region (region that acts as a channel) by a gate insulating film (Z G ) is provided. G ) can be an insulating film formed by CVD or the like, but it is also possible to use an SiO2 film formed by thermal oxidation of the surface of the SiC laminated film. This thermal oxidation can be carried out in a dry oxygen oxidation atmosphere (dry oxidation) or an oxygen atmosphere containing water vapor (wet oxidation), and V th The amount of fixed charge that affects the gate insulating film (Z G The optimum thermal oxidation conditions and film thickness can be selected taking into consideration the dielectric breakdown field strength of the gate insulating film (Z G ) on the gate electrode (M G ) can be made of various metal films deposited by sputtering, etc., but by using polycrystalline silicon (doped polysilicon) to which phosphorus (P) or boron (B) is added at high concentrations using low-pressure CVD, V th Stabilization of gate insulating film (Z G ) can improve the long-term reliability of the

[0057] <Source and drain electrode formation process> Finally, as shown in the cross-sectional structure in Figure 13, an electrode film such as Ni is deposited on the specified contact areas as source and drain electrodes by sputtering or other methods. After the electrodes are formed, a heat treatment is carried out in an argon atmosphere at a temperature of 750°C to 1050°C for several minutes to several tens of minutes, which causes a solid-phase reaction to form silicide, and n + Source contact area (D N ) or the drain contact region (DD ) and low contact resistance (R con ) to achieve ohmic characteristics.

[0058] (Structure of the second embodiment) As a semiconductor device according to a second embodiment of the present invention, the structure of a vertical n-channel MOSFET will be described with reference to the cross-sectional view of FIG. G ) corresponds to the control electrode, and the source electrode (M S ) corresponds to the first electrode, and the drain electrode (M D ) corresponds to the second electrode. G ) is adjacent to the 3C-SiC layer (E C ) to form an n-type channel near the surface, so the well region (W) is made p-type and the 4H-SiC layer (E H ) is n-type. That is, the first conductivity type is n-type, and the second conductivity type is p-type. Each region of the MOSFET handled in this embodiment extends in the [1-100] direction (depth direction in FIG. 14), and its width corresponds to the channel width. Also, along the [11-20] direction (right direction in FIG. 14), a well region (W), a tunnel doped region (D T The structure of the main part of the vertical n-channel MOSFET of the second embodiment is similar to that of the first embodiment, but a tunnel doped region (D) is provided between the adjacent well regions (W). T ) and drift region are formed, and then the drain electrode (M D ) is the substrate (U H ) is formed on the underside of the housing, which is a major difference from embodiment 1. The structural features of embodiment 2 that differ from embodiment 1 will be described below.

[0059] <Substrate> As in the first embodiment, the substrate (U HSingle crystal 4H-SiC can be used for the drift region (U), and its surface is a Si polar plane inclined at a certain angle (θ) from the basal plane (BP) corresponding to the (0001) plane to the [11-20] direction. By setting θ to 4 degrees, commercially available 4H-SiC wafers can be used as the substrate, but if it is necessary to narrow the distance between adjacent well regions, θ can be increased within a range not exceeding 60 degrees. However, the drift region of this embodiment is formed on the substrate (U H ) and must be electrically connected to the board (U H ) should have an n-type conductivity and a resistivity of 0.02 ohm·cm or less.

[0060] <Arrangement of 3C-SiC layer and 4H-SiC layer, matching interface> Substrate (U H ) on which the SiC laminated film is formed. The detailed structure of the SiC laminated film is the same as that of the first embodiment. However, in this embodiment, the drift layer is formed below the tunnel doped layer, so the width (L H ) can be reduced.

[0061] <Concentration and thickness of homoepitaxial layer> Substrate (U H 4H-SiC layer (E H ) is n-type, and the concentration of donor impurities to be added is the required V b For example, the V b When the voltage is set to 600V or more, the nitrogen concentration (n H ) is 1×10 17 cm ―3 The following is the 4H-SiC layer (E H ) thickness is preferably 4 μm or more. b If the voltage is 1200V or more, H 6×10 16 cm ―3 The following is the 4H-SiC layer (E H The thickness of the layer 10 μm or more is desirable.

[0062] <Structure of SiC stacked film> The structure of the SiC film constituting the second embodiment is the same as that of the first embodiment, and its 3C-SiC layer (E C ) exposes the inclined surface (S CI ) and the non-inclined surface (S CJ ) on the surface. Also, the boundary between the surface (S H ) of the 4H-SiC layer and the inclined surface (S CI ) of the 3C-SiC layer corresponds to the section (S X ) of the heterointerface. Further, the width (L CI ) of the inclined surface of the 3C-SiC layer needs to be selected as an optimal value in consideration of the relative relationship between the gap of the adjacent well regions (W), the width of the tunnel-doped region, and the MOSFET cell density (i.e., current density). However, since the drift region is formed below the tunnel-doped region (D T ) and the well region (W), it is desirable to make it narrower than that of the first embodiment, 10 μm or less. Also, the width (L CJ ) of the non-inclined surface of the 3C-SiC layer needs to be determined in consideration of the gate length and the arrangement of the source electrode.

[0063] <Arrangement of well region and acceptor concentration> The acceptor impurity added to the well region (W) and its concentration (n W ) are the same as those of the first embodiment, and it is also the same to arrange the lower end of the well region (W) within the 4H-SiC layer (E H ). Also, by arranging the gap (JFET region) between the adjacent well regions (W) below the inclined surface (S CI ) of the 3C-SiC layer, it becomes possible to surely make the lower end of the tunnel-doped region (D T ) abut against the drift region. Further, when a positive voltage is applied to the drain electrode (M S ) with respect to the source electrode (M D ), the depletion layer spreads from the well region (W) into the JFET region, thereby relaxing the electric field reaching the tunnel-doped region (D T ).

[0064] <Drain electrode> Unlike the first embodiment, the second embodiment uses a drain electrode (M D ) to the board (U H ) is brought into contact with the entire bottom surface of the SiC laminated film, allowing the current to pass through the SiC laminated film and substrate during MOSFET operation.

[0065] <Source electrode> In this embodiment, n adjacent channels (Ch) + Source contact area (D N ) through the source electrode (M S ) is in contact with the well region (W). + Source contact area (D P By providing the n-type source contact region (D) in the 4H-SiC layer in the well region (W), the potential of the well region (W) can be kept constant. N ) and the donor impurity concentration in the p-type source contact region (D P The acceptor impurity concentration in the box ( ) is the same as that in the first embodiment.

[0066] <Resistance component> In this embodiment, the source electrode (M S ) is grounded, and the drain electrode (M D ) and connect the load to R on The main component of is the contact resistance between the source and drain electrodes (R con ), the JFET resistance between adjacent well regions (R JFET ), channel resistance (R ch ), hetero-matched interface resistance (R X ), drift resistance (R DRIFT ) are five resistance components, but the effect of the present invention is ch The high channel mobility of the 3C-SiC region reduces the R X impurity concentration in the tunnel doped region is 5x10 19 cm -3 As described above, in this embodiment, the V b While maintaining R on can be further reduced.

[0067] (Manufacturing process of the second embodiment) 15 to 22, the manufacturing process of the n-type channel MOSFET of the first embodiment will be described below, although the description overlapping with the manufacturing process of the first embodiment will be omitted.

[0068] <Substrate> A commercially available single-crystal 4H-SiC wafer was used as the substrate (U H The wafer surface is tilted 4 degrees from the (0001) plane toward the [11-20] direction, and an n-type wafer with a resistivity of 0.02 ohm·cm or less is selected.

[0069] <Homoepitaxial growth process> As shown in the cross-sectional structure of Figure 15, a 4H-SiC substrate (U H ) on an n-type 4H-SiC layer (E H ) is homoepitaxially grown. At this time, the homoepitaxial growth time is adjusted to obtain the 4H-SiC layer (E H ) is the thickness of the drift region. Next, as shown in the cross-sectional structure of FIG. 16, the 4H—SiC growth layer (E H ) surface is partially covered with a 3C-SiC layer (E C A groove (V) is machined along with an alignment mark to identify the location where the .

[0070] <Heteroepitaxial growth process> Next, as shown in the cross-sectional structure of FIG. 17, a 4H—SiC layer (E H ) on a 3C-SiC layer (E C ) and a hetero-interface (S X ) is exposed on the surface of the SiC laminated film. In this process, the temperature during epitaxial growth (T epi ) each time, the 3C-SiC layer (E C ) the width of the inclined surface (L CI ) and the width of the non-inclined surface (L CJ ) is a predetermined value. In particular, L CI In contrast to L CJIf the temperature is maintained for a long time, the T epi is set to 1440℃ or less, w c While keeping small, the thickness of the 3C-SiC layer is set to a predetermined value, and then w c Given L CJ Comparable to T epi By adjusting the above, an optimum SiC laminated film can be obtained.

[0071] <Well region to source contact region formation> Next, as shown in the cross-sectional structure of FIG. 18, a p-type well region (W) is provided at a predetermined location in the SiC laminated film. At this time, a box profile is formed by multi-stage implantation of Al ions so that the bottom end of the well region (W) is located deeper than the hetero-matched interface (X). Furthermore, as shown in the cross-sectional structure of FIG. 19, a source electrode (M S ) abutting n + Source contact area (D N ), and the tunnel doped region (D T ) is formed by ion implantation of N and P. Furthermore, as shown in the cross-sectional structure of FIG. S ) in the well region (W) abutting the 4H-SiC layer surface (S H ) is partially implanted with Al ions, + Source contact area (D P Next, a well region (W), n + Contact area (D P ,D N ), and the tunnel doped region (D T In order to activate the donor impurities and acceptor impurities implanted in the GaN layer, activation annealing is performed at 1650°C or higher.

[0072] <Gate insulating film formation and electrode formation> Following the activation annealing step, as shown in the cross-sectional structure of FIG. + Source contact area (D N ) and tunnel doped region (D T) is separated from the well region (region that acts as a channel) by using CVD or thermal oxidation to form a gate insulating film (Z G ) is provided. Furthermore, a gate insulating film (Z G ) is deposited on the gate electrode (M G ) shall be established.

[0073] <Drain electrode formation process> Finally, as shown in the cross-sectional structure of Figure 22, the 4H-SiC substrate (U H ) by sputtering or the like on the entire bottom surface of the drain electrode (M D After the electrodes are formed, a solid-state reaction is caused by heat treatment, which reduces the contact resistance of each electrode.

[0074] Although the configurations and manufacturing methods of n-type channel lateral MOSFETs and vertical MOSFETs have been described in this specification as Embodiment 1 and Embodiment 2, respectively, a p-type channel MOSFET can also be configured by setting the first conductivity type to p-type and the second conductivity type to n-type. Furthermore, an n-type channel IGBT can also be manufactured by setting the conductivity type of the substrate and a portion of the hexagonal SiC layer abutting the substrate in an n-type channel vertical MOSFET to p-type. In this case, the first electrode functions as the emitter electrode, and the second electrode functions as the collector electrode.

[0075] In the embodiments of this specification, the well region and the control electrode are separated by an insulating film. However, it is also possible to control the current between the first electrode and the second electrode by bringing the well region and the control electrode into contact with each other and changing the width of the channel due to the Schottky barrier that the control electrode exerts in the well region.

[0076] In implementing the present invention, the substrate material is not limited to single-crystal 4H-SiC, but can be selected as needed from 3C-SiC, 6H-SiC, 15R-SiC, etc. Furthermore, a solid material other than SiC, whether single-crystal or polycrystalline, can be used as the substrate as long as its thermal conductivity, thermal expansion coefficient, temperature resistance, conductivity type, and resistivity are compatible with the required semiconductor device structure and manufacturing method. In this case, by attaching a single-crystal hexagonal SiC layer to the substrate, homoepitaxial growth or heteroepitaxial growth can be performed in the same manner as in the embodiments of this specification.

[0077] In the examples of this specification, a homoepitaxially grown 4H—SiC layer was used as the lower layer of the SiC laminated film. However, the SiC is not limited to 4H—SiC, and any hexagonal SiC may be used as long as it has a desired V b Depending on the application, 6H-SiC, 2H-SiC, or 8H-SiC can be selected.

[0078] Furthermore, when it is difficult to control the included angle between the hetero-matched interface and the SiC laminated film when exposing the hetero-matched interface on the surface of the SiC laminated film, it is possible to expose the hetero-matched interface at any location and with any included angle by mesa etching using photolithography and dry etching. In this case, the widths of the inclined and non-inclined surfaces of the 3C-SiC layer can also be determined arbitrarily.

[0079] Furthermore, the inclination direction of the hetero-matched interface relative to the SiC laminated film does not need to be limited to a specific orientation such as the [11-20] orientation, and any direction can be selected depending on the surface inclination direction during the mesa etching and SiC laminated film formation.

[0080] It should be noted that the method of doping impurities into the SiC laminated film does not need to be limited to the ion implantation method described in the embodiments of this specification, and it is also possible to use selective epitaxial growth, buried epitaxial growth, etc. to generate SiC layers doped with required ionized impurities locally, and use these as well regions or tunnel doped regions. As described above, the present invention naturally includes various embodiments not described in this specification. [Industrial Applicability]

[0081] The structure of the semiconductor element of the present invention can be applied to transistors such as MOSFETs, IGBTs, and JFETs that are widely used in power electronics, etc. In particular, it makes use of high breakdown voltages and low specific on-resistances to enable high power density and high-speed switching. [Explanation of symbols]

[0082] U H 4H-SiC substrate E H 4H-SiC layer E C 3C-SiC layer X heterogeneous interface W-well region D T Tunnel doped region Z G Gate insulating film M G gate electrode M S Source electrode M D Drain electrode S H 4H-SiC surface S CI 3C-SiC surface tilted from the basal plane S CJ 3C-SiC surface parallel to the basal plane D P p + Source Contact Area D N n + Source Contact Area DD n + Drain Contact Region RSF RESURF area Ch channel BP basal plane

Claims

1. a silicon carbide laminate film on a substrate, the silicon carbide laminate film having a laminate structure in which a lower single-crystal hexagonal silicon carbide layer and an upper single-crystal cubic silicon carbide layer are in contact with each other and form a heterocoherent interface; the heteromatched interface is parallel to the basal plane of the crystal plane of the hexagonal silicon carbide layer, and exposes its section at an included angle of 0.5 degrees or more and 60 degrees or less with respect to the surface of the silicon carbide laminate film; The silicon carbide laminated film surface including the hetero-matched interface has an ionized impurity concentration of 1×10 １９ cm －３ a tunnel doped region of the first conductivity type doped at a concentration of at least a portion of the hexagonal silicon carbide layer included in the tunnel doped region is in contact with a drift region made of a hexagonal silicon carbide layer of a first conductivity type doped with an impurity at a lower concentration than the tunnel doped region, and a portion of the cubic silicon carbide layer included in the tunnel doped region is in contact with a well region of a second conductivity type; a first electrode abutting on a portion of the surface of the well region via a contact region of a first conductivity type so as to form an ohmic contact; a part of the surface of the cubic silicon carbide layer constituting the well region is a channel separating the contact region of the first conductivity type from the tunnel doped region, and a control electrode is disposed adjacent to an upper portion of the channel; A semiconductor device characterized in that the second electrode is in contact with either the surface of the first conductivity type hexagonal silicon carbide layer or the underside of the substrate so as to form an ohmic contact.

2. 2. The semiconductor device of claim 1, wherein the well region intersects a heteroaligned interface.

3. A semiconductor element characterized in that the control electrode according to claim 1 is adjacent to the channel via an insulating film.

4. 2. The semiconductor device according to claim 1, wherein the surface of the cubic silicon carbide layer is a silicon surface, the first conductivity type is n-type, and the second conductivity type is p-type.

5. 5. The semiconductor device according to claim 1, wherein the surface of the 3C-SiC layer adjacent to the control electrode is parallel to the heteromatched interface.

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