Memory cell and semiconductor memory device having the same

Abstract

The present invention provides a highly integrated memory cell and a semiconductor memory device including the memory cell. According to the present invention, a semiconductor memory device includes: a memory cell array, wherein a plurality of memory cells are vertically stacked onto a substrate, wherein each memory cell includes: a bit line oriented perpendicular to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate, the word line and the back gate facing each other, the active layer interposed between the word line and the back gate, wherein edges of the word line and the back gate have a stepped shape along the stacking direction of the memory cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0023598, filed on February 22, 2021, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a memory cell or a semiconductor device including the memory cell. Background Art

[0004] The integration level of a two-dimensional semiconductor memory device is primarily determined by the area occupied by the unit memory cell. Therefore, the level of technology required to form microscopic patterns significantly impacts the integration level. The integration level of two-dimensional semiconductor memory devices continues to increase. However, this increase is limited because very expensive tools are required to refine the patterns. Therefore, three-dimensional (3D) semiconductor memory devices with three-dimensionally arranged memory cells are being introduced. Summary of the Invention

[0005] Embodiments of the present disclosure provide a highly integrated memory cell and a semiconductor memory device including the same.

[0006] According to one embodiment of the present invention, a semiconductor memory device includes a memory cell array, wherein a plurality of memory cells are vertically stacked on a substrate, wherein each memory cell includes: a bit line oriented perpendicular to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate, wherein the word line and the back gate face each other, the active layer is interposed between the word line and the back gate, and wherein edges of the word line and edges of the back gate have a stepped shape along the stacking direction of the memory cells.

[0007] According to one embodiment, a semiconductor memory device includes a memory cell array, wherein a plurality of memory cells are vertically stacked on a substrate, wherein each memory cell includes: a bit line oriented perpendicular to the substrate; a capacitor laterally spaced apart from the bit line; an active layer including a thin body channel, the thin body being laterally disposed between the bit line and the capacitor; and a word line and a back gate, the word line and the back gate facing each other, the thin body channel being interposed between the word line and the back gate, and wherein edges of the word line and edges of the back gate have a stepped shape along the stacking direction of the memory cells.

[0008] The present disclosure may prevent interference between word lines by forming a back gate between vertically stacked memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic perspective view illustrating a memory cell of a semiconductor memory device according to an embodiment of the present invention.

[0010] Figure 2 It is an icon Figure 1 A cross-sectional view of a storage unit.

[0011] Figure 3 is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention.

[0012] Figure 4 It is an icon Figure 3 Cross-sectional view of a vertical memory cell array.

[0013] Figure 5 is a cross-sectional view illustrating an edge portion of a word line.

[0014] Figure 6 is a schematic cross-sectional view illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present invention.

[0015] Figures 7A to 7M is a diagram illustrating a method of manufacturing a memory cell according to an embodiment of the present invention.

[0016] Figure 8 is a diagram illustrating a memory cell according to an embodiment of the present invention.

[0017] Figure 9A is a diagram illustrating a memory cell according to an embodiment of the present invention.

[0018] Figure 9B yes Figure 9A Detailed view of the transistor.

[0019] Figure 10 is a cross-sectional view of a memory cell array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which are idealized schematic diagrams of the present invention. Therefore, the structures of the drawings may be modified due to manufacturing techniques and / or tolerances. The embodiments of the present invention are not limited to the specific structures shown in the drawings, but include any variations in structure that may be produced based on manufacturing processes. Furthermore, any regions and shapes shown in the drawings are schematic and are intended to illustrate specific examples of the regional structures of the various components and are not intended to limit the scope of the present invention.

[0021] The embodiments described below may increase memory cell density and reduce parasitic capacitance by vertically stacking memory cells.

[0022] Figure 1is a schematic perspective view illustrating a memory cell of a semiconductor memory device according to an embodiment of the present invention. Figure 2 It is an icon Figure 1 A cross-sectional view of a storage unit.

[0023] See also Figure 1 and Figure 2 , a memory cell MC of a 3D semiconductor memory device according to an embodiment of the present invention may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a pillar shape extending in a first direction D1. The active layer ACT may have a bar shape extending in a second direction D2 intersecting the first direction D1. The word line WL may have a line shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to a plate line PL.

[0024] The bit line BL may be vertically oriented along the first direction D1. The bit line BL may be referred to as a vertically oriented bit line or a pillar-shaped bit line. The bit line BL may include a conductive material. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with N-type impurities or titanium nitride (TiN). The bit line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0025] The word line WL may extend in a third direction D3, and the active layer ACT may extend in a second direction D2. The active layer ACT may be arranged laterally from the bit line BL. A gate dielectric layer GD may be formed on the upper and lower surfaces of the active layer ACT. The gate dielectric layer GD may include silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The gate dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON. The word line WL may include a metal, a metal mixture, a metal alloy, or a semiconductor material. The word line WL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the word line WL may include a TiN / W stack, wherein titanium nitride and tungsten are stacked in the order indicated. The word line WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less, and the P-type work function material may have a high work function of 4.5 eV or more.

[0026] The active layer ACT may include a semiconductor material or an oxide semiconductor material. For example, the active layer ACT may include polysilicon, germanium, silicon germanium, or indium gallium zinc oxide (IGZO). The active layer ACT may include a channel CH, a first source / drain region SR between the channel CH and the bit line BL, and a second source / drain region DR between the channel CH and the capacitor CAP.

[0027] The first source / drain region SR and the second source / drain region DR may both be doped with the same conductive impurities. The first source / drain region SR and the second source / drain region DR may be doped with N-type impurities or P-type impurities. The first source / drain region SR and the second source / drain region DR may include at least one impurity selected from arsenic (AS), phosphorus (P), boron (B), indium (In), and combinations thereof. A first side of the first source / drain region SR may be connected to the bit line BL, and a second side of the first source / drain region SR may be connected to the channel CH. A first side of the second source / drain region DR may be connected to the storage node SN, and a second side of the second source / drain region DR may be connected to the channel CH. Each of the second side of the first source / drain region SR and the second side of the second source / drain region DR may overlap with a side of the word line WL. A lateral length of the channel CH along the second direction D2 may be shorter than each of the lateral lengths of the first source / drain region SR and the second source / drain region DR along the second direction D2. In another embodiment, the lateral length of the channel CH along the second direction D2 may be longer than each of the lateral lengths of the first and second source / drain regions SR and DR along the second direction D2.

[0028] The transistor TR as a unit transistor may have a single word line WL. The back gate BG may be arranged to face the word line WL, with the active layer ACT interposed between the back gate BG and the word line WL. The word line may be arranged above the active layer ACT and the back gate BG may be arranged below the active layer ACT. The back gate BG may extend in a third direction D3. The word line WL and the back gate BG may be parallel to each other. The word line WL and the back gate BG may be composed of the same material. For example, the back gate BG may include a metal, a metal mixture, a metal alloy, or a semiconductor material. The back gate BG may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the back gate may include a stack of TiN / W, wherein titanium nitride and tungsten are stacked in the order described.

[0029] The word lines WL and the back gate BG may have different potentials. For example, a word line drive voltage may be applied to the word lines WL, and a reference (e.g., ground) voltage may be applied to the back gate BG. The back gate BG may be used to prevent interference between the word lines WL of the memory cells MC, which are vertically arranged along the first direction D1.

[0030] Therefore, the memory cell MC according to an embodiment of the present invention may have a dual-gate structure in which the word line WL and the back gate BG are adjacent to the single channel CH. In another embodiment, the word line WL may be disposed below the active layer ACT and the back gate BG may be disposed above the active layer ACT.

[0031] A bitline-side ohmic contact (BOC) may be formed between the first source / drain region SR and the bitline BL. The bitline-side ohmic contact (BOC) may have a height sufficient to completely cover one side of the first source / drain region SR. The bitline-side ohmic contact (BOC) may be formed by depositing a metal layer and annealing the metal layer. For example, the bitline-side ohmic contact (BOC) may be formed by a reaction between metal of the metal layer and silicon of the first source / drain region SR. The bitline-side ohmic contact (BOC) may include titanium silicide, cobalt silicide, nickel silicide, or the like.

[0032] The capacitor CAP may be laterally arranged from the transistor TR along the second direction D2. The capacitor CAP may include a storage node SN extending laterally from the active layer ACT along the second direction D2. The capacitor CAP may further include a dielectric layer DE on the storage node SN and a plate node PN on the dielectric layer DE. The storage node SN, the dielectric layer DE, and the plate node PN may be laterally arranged along the second direction D2. The storage node SN may have a laterally oriented cylindrical shape. The dielectric layer DE may conformally cover the inner and outer cylindrical walls of the storage node SN. The plate node PN may have a shape extending within the inner and outer cylindrical walls of the storage node SN on the dielectric layer DE. The plate node PN may be connected to a plate line PL. The storage node SN may be electrically connected to the second source / drain region DR.

[0033] The storage node SN may have a 3D structure. The storage node SN of the 3D structure may have a lateral 3D structure oriented along the second direction D2. As an example of a 3D structure, the storage node SN may have a barrel shape. In another embodiment, the storage node SN may have a column shape or a pylinder shape. The pylinder shape may refer to a structure in which a column shape and a barrel shape are combined. The uppermost surface of the storage node SN may be at the same level as the top surface of the word line WL. The lowermost surface of the storage node SN may be at the same level as the bottom surface of the back gate BG.

[0034] The plate node PN may include an internal node N1 and external nodes N2, N3, and N4. The internal node N1 and the external nodes N2 to N4 may be interconnected. The internal node N1 may be disposed inside the cylindrical body of the storage node SN. The external nodes N2 and N3 may be disposed outside the cylindrical body of the storage node SN, with a dielectric layer DE interposed between the external nodes N2 and N3 and the storage node SN. The external node N4 may interconnect the internal node N1 and the external nodes N2 and N3. The external nodes N2 and N3 may be disposed as a cylindrical outer wall surrounding the storage node SN. The external node N4 may serve as a plate line PL.

[0035] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacking, or tungsten nitride / tungsten (WN / W) stacking. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may include a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stacking. In the case where the plate node PN includes a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium (SiGe) can be a gap-filling material filled inside the cylinder of the storage node SN, titanium nitride (TiN) can be used as the plate node PN of the capacitor CAP, and tungsten nitride (WN) can be a low-resistance material.

[0036] The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of approximately 20 or greater. The high-k material may include: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In one embodiment, the dielectric layer DE may be formed by a composite layer including two or more layers of the above-mentioned high-k materials.

[0037] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a laminated structure including zirconium oxide (ZrO2). The laminated structure including zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) laminate or a ZAZ (ZrO2 / Al2O3 / ZrO2) laminate. The ZA laminate may have a structure in which aluminum oxide (Al2O3) is laminated on zirconium oxide (ZrO2). The ZAZ laminate may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are laminated in the stated order. The ZA and ZAZ laminates may be referred to as zirconium oxide (ZrO2)-based layers. In one embodiment, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a laminated structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in the stated order. The HA and HAH stacks may be referred to as hafnium oxide (HfO2) based layers. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material, the high-bandgap material having a larger bandgap than the high-k material. The dielectric layer DE may include silicon oxide (SiO2) as a high-bandgap material in addition to aluminum oxide (Al2O3). Since the dielectric layer DE includes the high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material. In another embodiment, the dielectric layer DE may include a laminated structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above-described laminated structure, aluminum oxide (Al2O3) may be very thin.

[0038] In one embodiment, the dielectric layer DE may include a stacked structure, a laminated structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0039] In one embodiment, an interface control layer for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0040] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node ON may include a metal-based material.

[0041] The capacitor CAP may be replaced with other storage materials, for example, storage materials such as a phase change material, a magnetic tunnel junction (MTJ) material, or a variable resistor material.

[0042] A storage node-side ohmic contact SOC may be formed between the second source / drain region DR and the storage node SN. The storage node-side ohmic contact SOC may have a height that completely covers one side of the second source / drain region DR. The storage node-side ohmic contact SOC may be formed by depositing a metal layer and annealing it. For example, the storage node-side ohmic contact SOC may be formed by a reaction between the metal of the metal layer and the silicon of the second source / drain region DR. The storage node-side ohmic contact SOC may include a metal silicide. The storage node-side ohmic contact SOC may include titanium silicide, cobalt silicide, nickel silicide, or the like.

[0043] Figure 3 is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention. Figure 4 It is an icon Figure 3 A cross-sectional view of a vertical memory cell array MCA_C. Figure 5 is a cross-sectional view illustrating an edge portion of a word line.

[0044] See also Figures 3 to 5 , the semiconductor memory device 100 may include a memory cell array MCA. Figure 1The memory cells MC can be arranged in a first direction D1 to a third direction D3 and can be configured in a multi-layer memory cell array MCA structure. The memory cell array MCA may include a 3D array of memory cells MC. The 3D memory cell array may include multiple vertical memory cell arrays MCA_C and multiple horizontal memory cell arrays MCA_R. The vertical memory cell array MCA_C may refer to an array of memory cells MC arranged vertically along the first direction D1. The horizontal memory cell array MCA_R may refer to an array of memory cells MC arranged horizontally along the third direction D3. The vertical memory cell array MCA_C may also be referred to as a column array of memory cells MC, and the horizontal memory cell array MCA_R may also be referred to as a row array of memory cells MC. The bit lines BL may be oriented vertically to connect to the vertical memory cell arrays MCA_C. The word lines WL may be oriented horizontally to connect to the horizontal memory cell arrays MCA_R. The bit lines BL connected to the vertical memory cell arrays MCA_C may be referred to as common bit lines. Adjacent vertical memory cell arrays MCA_C arranged along the third direction D3 may be connected to different common bit lines. The word lines WL connected to the lateral memory cell array MCA_R may be referred to as common word lines. Adjacent lateral memory cell arrays MCA_R arranged along the first direction D1 may be connected to different common word lines, respectively.

[0045] The memory cell array MCA may include a plurality of memory cells MC. Each memory cell MC may include a vertically oriented bit line BL, a transversely oriented active layer ACT, a word line WL, a back gate BG, and a transversely oriented capacitor CAP. Figure 3 A 3D memory cell array composed of four memory cells MC is shown.

[0046] A single bit line BL can be connected through adjacent active layers ACT, which are arranged along a first direction D1. Adjacent active layers ACT arranged at the same level along a third direction D3 can share a single word line WL. Each capacitor CAP can be connected to a corresponding active layer ACT. The capacitors CAP can share a single plate line PL. For example, in Figure 3 In FIG, four capacitors are shown and may all share a single plate line PL. In a variation of the described embodiment, only capacitors arranged vertically in the first direction D1 may share a common plate line PL.

[0047] In the memory cell array MCA, a pair of word lines WL and a back gate BG can be vertically stacked along a first direction D1. Between the word lines WL and the back gate BG, multiple active layers ACT can be arranged laterally along a third direction D3 and spaced apart from each other. For example, in the described embodiment, two active layers ACT are shown as being arranged laterally along the third direction D3 between the word lines WL and the back gate BG. However, it should be understood that the specific number may vary without departing from the scope of the present invention. The channel CH of the active layer ACT can be provided between the word lines WL and the back gate BG.

[0048] See again Figure 5 , the word line WL and the back gate BG may extend in the third direction D3. Each of the word line WL and the back gate BG may include edge portions on both sides thereof (i.e., on opposite sides thereof along the third direction D3). The edge portions may form a stepped shape, which may define a contact portion CA. In the memory cell array MCA, the edges of the word line WL and the back gate BG may form a stepped shape along the stacking direction (i.e., the first direction) of the memory cells.

[0049] The contact portions CA of the word lines WL may be connected to a plurality of word line contact plugs WLP, respectively. The contact portions CA of the back gates BG may be connected to a plurality of back gate contact plugs BGP, respectively. The word line contact plugs WLP and the back gate contact plugs BGP may be spaced apart from each other.

[0050] The semiconductor memory device 100 may further include a substrate PERI. The substrate PERI may include peripheral circuits. Hereinafter, the substrate PERI is referred to as the peripheral circuit PERI. The bit lines BL of the memory cell array MCA may be oriented perpendicularly to the surface of the peripheral circuit PERI. The word lines WL and back gates BG may be oriented laterally parallel to the surface of the peripheral circuit PERI.

[0051] The peripheral circuit PERI may be disposed below the memory cell array MCA. This may be referred to as a cell-on-PERI (COP) structure. The peripheral circuit PERI may include one or more control circuits for driving the memory cell array MCA. At least one control circuit of the peripheral circuit PERI may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit PERI may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit PERI may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin-type channel transistor (FinFET), etc.

[0052] For example, the peripheral circuit PERI may include a sub-wordline driver SWD, a sub-hole circuit SH, and a sense amplifier SA. The wordline WL may be connected to the sub-wordline driver SWD via a wordline contact plug WLP and a metal interconnect MI1. The backgate BG may be connected to the sub-hole circuit SH via a backgate contact plug BGP and a metal interconnect MI2. The bitline BL may be connected to the sense amplifier SA via a metal interconnect MI3. Each metal interconnect MI3 may include a multi-layer metal (MLM) structure including a plurality of vias and a plurality of metal interconnects.

[0053] As described above, the word line contact plug WLP and the back gate contact plug BGP may be spaced apart from each other. For example, the edge of the word line WL may be connected to the word line contact plug WLP on one side of the memory cell array MCA, and the edge of the back gate BG may be connected to the back gate contact plug BGP on the other side of the memory cell array MCA, the other side of the memory cell array MCA being opposite to the one side of the memory cell MCA along the third direction D3, as shown in FIG. Figure 5 shown.

[0054] In one embodiment, the memory cell array MCA may be disposed under the peripheral circuit PERI.

[0055] Figure 6 is a schematic cross-sectional view illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present invention. Figure 6 FIG. 1 shows a semiconductor memory device 110 having a peripheral circuit on cell (POC) structure. Figure 6 In, with Figure 5 The same components will not be described again.

[0056] See also Figure 6 , the semiconductor memory device 110 may include a memory cell array MCA and a peripheral circuit PERI'. The peripheral circuit PERI' may be located at a higher level than the memory cell array MCA. This may be referred to as a PERI-on-cell (POC) structure.

[0057] The peripheral circuit PERI′ may include a sub-wordline driver SWD, a sub-hole circuit SH, and a sense amplifier SA. The wordline WL may be connected to the sub-wordline driver SWD via a wordline contact plug WLP and a metal interconnect MI1. The backgate BG may be connected to the sub-hole circuit SH via a backgate contact plug BGP and a metal interconnect MI2. The bitline BL may be connected to the sense amplifier SA via a metal interconnect MI3. Each metal interconnect MI3 may include a multi-layer metal (MLM) structure including a plurality of vias and a plurality of metal interconnects.

[0058] Figures 7A to 7M is a diagram illustrating a method of manufacturing a memory cell according to an embodiment of the present invention.

[0059] like Figure 7A As shown, a stack SB may be formed. The stack SB may include a first interlayer dielectric layer 11 and a second interlayer dielectric layer 15, a first sacrificial layer 12 and a second sacrificial layer 14, and a semiconductor layer 13. The semiconductor layer 13 may be disposed between the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15. The first sacrificial layer 12 may be disposed between the first interlayer dielectric layer 11 and the semiconductor layer 13. The second sacrificial layer 14 may be disposed between the second interlayer dielectric layer 15 and the semiconductor layer 13. The first interlayer dielectric layer 11 and the second interlayer dielectric layer 15 may include silicon oxide, and the first sacrificial layer 12 and the second sacrificial layer 14 may include silicon nitride. The semiconductor layer 13 may include a semiconductor material or an oxide semiconductor material. The semiconductor layer 13 may include polycrystalline silicon or other semiconductor materials, such as indium gallium zinc oxide (IGZO). The semiconductor layer 13 may serve as an active layer. The first sacrificial layer 12 and the second sacrificial layer 14 may be formed of different materials. For example, the first sacrificial layer 12 may include a carbon-based material, and the second sacrificial layer 14 may include silicon nitride. The carbon-based material may include SiCN or SiCO. The carbon-based material may have an etching selectivity relative to silicon nitride and silicon oxide.

[0060] like Figure 7B As shown, the first opening 16 may be formed by etching a portion of the stacked body SB. The first opening 16 may extend vertically.

[0061] like Figure 7C As shown, the first recess 17 may be formed by selectively etching a portion of the second sacrificial layer 14 through the first opening 16 to partially expose the upper surface of the semiconductor layer 13. The first recess 17 may be a lateral recess disposed between the semiconductor layer 13 and the second interlayer dielectric layer 15.

[0062] like Figure 7D As shown, a gate dielectric layer GD may be conformally formed on the side surface of the first recess 17 .

[0063] Subsequently, word lines WL may be formed in the first recess 17 to fill the remaining space within the recess 17 . Titanium nitride and tungsten may be deposited, and an etch-back process may be performed on the deposition of titanium nitride and tungsten to form word lines WL. The word lines WL may partially fill the first recess 17 .

[0064] like Figure 7E As shown, a first capping material 18 may be filled in the first recess 17. The first capping material 18 may include silicon oxide. The first recess 17 may be filled with the gate dielectric layer GD, the word line WL, and the first capping material 18. In one embodiment, the capping material 18 may fill the end of the recess adjacent to the first opening 16 that is not covered by the gate dielectric layer GD and the word line WL.

[0065] Subsequently, a second recess 19 can be formed by selectively etching a portion of the first sacrificial layer 12 through the first opening 16. The bottom surface of the semiconductor layer 13 can be partially exposed through the second recess 19. The second recess 19 can also be a lateral recess parallel to the first recess 17. The lateral lengths of the first recess 17 and the second recess 19 can be the same. The second recess 19 can be a lateral recess disposed between the semiconductor layer 13 and the first interlayer dielectric layer 11.

[0066] like Figure 7F As shown, a liner material 20 may be conformally formed on the side of the second recess 19. The liner material 20 may be an interlayer dielectric material and may include silicon oxide. The liner material 20 and the gate dielectric layer GD may be composed of the same material. The liner material 20 may serve as a gate dielectric layer.

[0067] Subsequently, a back gate BG filling the second recess 19 may be formed on the liner material 20. Titanium nitride and tungsten may be deposited, and an etch-back process may be performed on the deposited titanium nitride and tungsten to form the back gate BG. The back gate BG and the word line WL may be composed of the same material.

[0068] The word line WL and the back gate BG may face each other with the semiconductor layer 13 interposed therebetween. The word line WL and the back gate BG may correspond to Figures 1 to 6 The word line WL and back gate BG mentioned in.

[0069] In one embodiment, the word line WL may be formed after first forming the back gate BG.

[0070] In one embodiment, the word line WL may be disposed under the semiconductor layer 13 , and the back gate BG may be disposed over the semiconductor layer 13 .

[0071] Next, the remaining portion of the second recess 19 may be filled with a second capping material 21. The second capping material 21 may include silicon oxide.

[0072] like Figure 7G As shown, a first source / drain region SR can be formed at the first end of the semiconductor layer 13 through the first opening 16. The first source / drain region SR can be formed through an impurity doping process and a thermal treatment. In one embodiment, after the first opening 16 is filled with impurity-containing polysilicon, a subsequent thermal treatment can be performed to diffuse the impurities from the polysilicon to the first end of the semiconductor layer 13. Thus, the first source / drain region SR can be formed at the first end of the semiconductor layer 13. One side of the first source / drain region SR can extend to overlap with one side of the word line WL and one side of the back gate BG.

[0073] like Figure 7HAs shown, a bit line side ohmic contact BOC may be formed contacting the first source / drain region SR. The bit line side ohmic contact BOC may include a metal silicide. For example, the metal silicide may be formed by sequentially performing a metal layer deposition and annealing process on the first source / drain region SR and the first opening 16, and the unreacted metal layer may be removed. The metal silicide may be formed by a reaction between silicon in the first source / drain region SR and the metal layer.

[0074] Next, a bit line BL contacting the bit line-side ohmic contact BOC may be formed. The bit line BL may fill the first opening 16. The bit line BL may include titanium nitride, tungsten, or a combination thereof.

[0075] like Figure 7I As shown, the second opening 22 may be formed by etching another portion of the stacked body SB. The second opening 22 may extend vertically.

[0076] Next, the first and second sacrificial layers 12 and 14 and the semiconductor layer 13 may be selectively recessed through the second opening 22. The recessed semiconductor layer 13 may become the active layer ACT. A recess space 23 where a storage node of a capacitor is to be formed may also be defined.

[0077] like Figure 7J As shown, a second source / drain region DR can be formed at the second end of the active layer ACT. The second source / drain region DR can be formed through an impurity doping process and a heat treatment. In one embodiment, after the second opening 22 is filled with impurity-containing polysilicon, a subsequent heat treatment can be performed to diffuse the impurities from the polysilicon to the second end of the active layer ACT. Thus, the second source / drain region DR can be formed at the second end of the active layer ACT. A channel CH can be defined between the first source / drain region SR and the second source / drain region DR. The side of the second source / drain region DR adjacent to the channel CH can overlap with the word line WL and the back gate BG.

[0078] Next, a storage node-side ohmic contact SOC may be formed on the second source / drain region DR. The storage node-side ohmic contact SOC may include a metal silicide. For example, the metal silicide may be formed by sequentially performing a metal layer deposition and annealing process on the second source / drain region DR and the recessed space 23, and the unreacted metal layer may be removed. The metal silicide may be formed by a reaction between silicon in the second source / drain region DR and the metal layer.

[0079] like Figure 7KAs shown, a storage node SN contacting the storage node-side ohmic contact SOC may be conformally formed on the side of the recessed space 23. To form the storage node SN, a conductive material deposition and etch-back process may be performed. The storage node SN may include titanium nitride. The storage node SN may have a laterally oriented cylindrical shape.

[0080] like Figure 7L As shown, the outer wall of the storage node SN may be exposed by recessing the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15 to form a space 24 .

[0081] like Figure 7M As shown, a dielectric layer DE and a plate node PN may be sequentially formed on the storage node SN. The dielectric layer DE may be conformally formed on the exposed side surfaces of the storage node SN and on the side surfaces of the first interlayer dielectric layer 11 and the second interlayer dielectric layer 15 facing the space 24. The plate node PN may be formed by filling the remaining portion of the space 24, the remaining portion of the recess 23, and the second opening 22 with a plate node material.

[0082] Figure 8 is a diagram illustrating a memory cell according to an embodiment of the present invention. Figure 8 The memory cell MC10 can be similar to Figure 1 The storage unit MC. Figure 8 In, with Figures 1 to 6 The same components will not be described again.

[0083] See also Figure 8 , a memory cell MC10 of a 3D semiconductor memory device may include: a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include: an active layer ACT, a gate dielectric layer GD, and a word line WL10. The capacitor CAP may include: a storage node SN, a dielectric layer DE, and a plate node PN, wherein the dielectric layer is provided between the storage node SN and the plate node PN. The bit line BL may have a pillar shape extending in a first direction D1. The active layer ACT may have a bar shape extending in a second direction D2 intersecting the first direction D1. The word line WL10 may have a line shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of the capacitor CAP may be connected to the plate line PL.

[0084] The memory cell MC10 may further include a back gate BG10. The word line WL10 and the back gate BG10 may face each other, with the active layer ACT interposed therebetween. The word line WL10 may be disposed above the active layer ACT. The back gate BG10 may be disposed below the active layer ACT. The back gate BG10 may be thinner than the word line WL10. The back gate BG10 and the word line WL10 may be formed of the same material. In one embodiment, the word line WL10 may be disposed below the active layer ACT, and the back gate BG10 may be disposed above the active layer ACT.

[0085] Edge portions on both sides of the word line WL10 and the back gate BG10 may form a step shape, such as Figure 5 shown.

[0086] Figure 9A is a diagram illustrating a memory cell according to an embodiment of the present invention. Figure 9A The memory cell MC20 can be similar to Figure 1 The storage unit MC. Figure 9A In, with Figures 1 to 6 The same components will not be described again.

[0087] See also Figure 9A Memory cell MC20 of a 3D semiconductor memory device may include a bit line BL, a transistor TR, and a capacitor CAP. Transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. Capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The bit line BL may have a pillar shape extending in a first direction D1. The active layer ACT may have a bar shape extending in a second direction D2 intersecting the first direction D1. The word line WL may have a line shape extending in a third direction D3 intersecting the first direction D1 and the second direction D2. The plate node PN of capacitor CAP may be connected to a plate line PL.

[0088] The memory cell MC20 may further include a back gate BG. The word line WL and the back gate BG may face each other, with the active layer ACT interposed therebetween. The word line WL may be disposed above the active layer ACT, and the back gate BG may be disposed below the active layer ACT. The back gate BG and the word line WL may have the same thickness. The back gate BG and the word line WL may be formed of the same material. In one embodiment, the word line WL may be disposed below the active layer ACT, and the back gate BG may be disposed above the active layer ACT.

[0089] Edge portions on both sides of the word line WL and the back gate BG may form a step shape, such as Figure 5 shown.

[0090] The active layer ACT may include a thin body channel TCH that is thinner than the word line WL and the back gate BG. The thin body channel TCH may have a thickness of 1 nm to 7 nm. The thin body channel TCH may include a semiconductor material or an oxide semiconductor material. For example, the thin body channel TCH may include polysilicon, silicon germanium, or indium gallium zinc oxide (IGZO). The active layer ACT may include a first source / drain region SR and a second source / drain region DR on both sides of the thin body channel TCH. The first source / drain region SR may be connected to the bit line BL, and the second source / drain region DR may be connected to the capacitor CAP. A bit line side ohmic contact BOC may be formed between the first source / drain region SR and the bit line BL, and a storage node side ohmic contact SOC may be formed between the second source / drain region DR and the capacitor CAP.

[0091] Figure 9B yes Figure 9A Detailed view of the transistor.

[0092] See also Figure 9B In the transistor TR, the word line WL and the back gate BG may face each other, with the active layer ACT interposed therebetween. The word line WL and the back gate BG may have a first thickness V1. The active layer ACT may have a second thickness V2. The second thickness V2 may be smaller or thinner than the first thickness V1. The thin body channel TCH may have a second thickness V2, and the thin body channel TCH may be thinner than the word line WL and the back gate BG. In one embodiment, the back gate BG may be thinner than the word line WL, and in this case, the thickness of the back gate BG may be equal to or greater than the thickness of the thin body channel TCH.

[0093] The integration density of memory cells stacked along the first direction D1 can be improved by thin body channel TCH. Transistors with thin body channel TCH can be applied to dual-gate DG field effect transistors, FinFETs, all-around gate (GAA) field effect transistors, and multi-bridge thin body channel field effect transistors.

[0094] Figure 10 FIG is a cross-sectional view of a memory cell array according to an embodiment of the present invention. Figure 10 In, with Figure 5 The same components will not be described again.

[0095] See also Figure 10 In the memory cell array 200, the word lines WL and the back gates BG may be vertically stacked along a first direction D1. The word lines WL and the back gates BG may extend along a third direction D3, and edge portions on both sides of the word lines and the back gates BG may form a staircase shape. In the memory cell array 200, the edges of the word lines WL and the edges of the back gates BG may have a staircase shape along the stacking direction of the memory cells (i.e., the first direction D1).

[0096] A plurality of word line contact plugs WLP may be connected to respective edges of the word lines WL. A plurality of back gate contact plugs BGP may be connected to respective edges of the back gates BG. The word line contact plugs WLP and the back gate contact plugs BGP may be spaced apart from each other.

[0097] A pair of word lines WL and back gates BG may include a vertical alignment step VA and a diagonal alignment step SAS. When one side of the word line WL and one side of the back gate BG are self-aligned, the vertical alignment step VA may be formed. When the other side of the back gate BG is longer than the other side of the word line WL and thus aligned diagonally, the diagonal alignment step SAS may be formed. More specifically, as Figure 10 As shown, a first pair of word lines WL and back gates BG may form an obliquely aligned step SAS at their sides near the back gate plug side BGPS of the memory cell array 200, wherein the word lines WL in the first pair are shorter than the back gates BG in the third direction D3. Furthermore, a second pair of word lines WL and back gates BG stacked above the first pair may have back gates BG that are shorter than the length of the word lines WL in the first pair, so that the top surfaces of the ends of the word lines WL in the first pair do not overlap with the word lines in the second pair, allowing for the formation of word line plugs WLP. The word lines in the second pair may be vertically aligned with the back gates BG of the second pair at their ends near the word line plug side WLPS of the memory cell array 200. Furthermore, the length of the word lines WL in the second pair in the third direction D3 may be shorter than the length of the back gates BG in the second pair, thereby forming an obliquely aligned step SAS at their ends near the back gate plug side BGPS of the memory cell array 200. Similarly, a third pair of word lines WL and back gates BG may be stacked over the second pair and form a slant-aligned step SAS at their ends near the back gate plug side BGPS of the memory cell array 200 and a vertically-aligned step VA at their opposite ends near the word line plug side WLPS of the memory cell array 200.

[0098] In the memory cell array 200 , a pair of vertically aligned steps VA may be stacked multiple times along the first direction D1 . In addition, in the memory cell array 200 , a pair of obliquely aligned steps SAS may be stacked multiple times along the first direction D1 .

[0099] While the present disclosure has been shown and described with reference to specific embodiments thereof, the present disclosure is not limited thereto and it will be readily apparent to those skilled in the art that various changes or modifications may be made thereto without departing from the scope of the present disclosure.

Claims

1. A semiconductor memory device comprising: A memory cell array in which multiple memory cells are vertically stacked on a substrate. Wherein, each of the storage units includes: a bit line oriented vertically relative to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and word lines and back gates, the active layer being interposed between the word lines and the back gates, the word lines and the back gates being coupled to the active layer; Wherein, the edge of the word line and the edge of the back gate form a staircase shape along the stacking direction of the memory cell; and Wherein, the active layer comprises: a first source / drain region connected to the bit line; a second source / drain region connected to the capacitor; and a channel between the first source / drain region and the second source / drain region, The channel is thinner than the second source / drain region. 2 . The semiconductor memory device according to claim 1 , further comprising a word line contact plug and a back gate contact plug respectively connected to an edge of the word line and an edge of the back gate having a step shape.

3. The semiconductor memory device according to claim 2, wherein The word line contact plug is disposed on an edge of one side of the memory cell array, and the back gate contact plug is disposed on an edge of another side of the memory cell array opposite to the one side.

4. The semiconductor memory device according to claim 1, wherein The word line and the back gate face each other, the channel is interposed between the word line and the back gate, The word line is disposed above the channel, and The back gate is arranged below the channel.

5. The semiconductor memory device according to claim 1, wherein The word line and the back gate face each other, the channel is interposed between the word line and the back gate, The word line is disposed below the channel, and The back gate is arranged on the channel.

6. The semiconductor memory device according to claim 1, wherein The thickness of the channel is thinner than that of each of the word line and the back gate.

7. The semiconductor memory device according to claim 1, wherein The channel has a thickness of 1 nm to 7 nm.

8. The semiconductor memory device according to claim 1, wherein The word line and the back gate include the same material.

9. The semiconductor memory device according to claim 1, wherein The active layer includes polysilicon, silicon germanium or indium gallium zinc oxide.

10. The semiconductor memory device according to claim 1, wherein The memory cell array includes a DRAM cell array.

11. The semiconductor memory device according to claim 1, in, The capacitor comprises: a storage node connected to the active layer and oriented laterally; a dielectric layer on the storage node; and a plate-type node on the dielectric layer, Wherein, the storage node has a cylindrical shape.

12. The semiconductor memory device according to claim 1, wherein The substrate includes peripheral circuits for controlling the memory cell array.

13. The semiconductor memory device according to claim 12, wherein The peripheral circuit includes a sub-word line driver for controlling a word line and a sub-hole circuit for controlling a back gate.

14. The semiconductor memory device according to claim 13, wherein The sub-word line driver and the memory cell array are vertically overlapped.

15. A semiconductor memory device comprising: A memory cell array in which multiple memory cells are vertically stacked on a substrate. Wherein, each of the storage units includes: a bit line oriented perpendicular to the substrate; a capacitor laterally spaced apart from the bit line; an active layer comprising a thin-body channel disposed laterally between the bit line and the capacitor; and a word line and a back gate, the thin body channel being interposed between the word line and the back gate, the word line and the back gate being coupled to the thin body channel; Wherein, the edge of the word line and the edge of the back gate form a staircase shape along the stacking direction of the memory cell; and The thickness of the thin body channel is thinner than the thickness of each of the word line and the back gate. 16 . The semiconductor memory device according to claim 15 , further comprising a word line contact plug and a back gate contact plug respectively connected to an edge of the word line and an edge of the back gate having a step shape.

17. The semiconductor memory device according to claim 16, wherein The word line contact plug is disposed on an edge of one side of the memory cell array, and the back gate contact plug is disposed on an edge of another side of the memory cell array opposite to the one side.

18. The semiconductor memory device according to claim 15, wherein The word line is disposed above the thin body channel, and the back gate is disposed below the thin body channel.

19. The semiconductor memory device according to claim 15, wherein The word line is disposed below the thin body channel, and the back gate is disposed above the thin body channel.

20. The semiconductor memory device according to claim 15, wherein The thin body channel has a thickness of 1 nm to 7 nm.

21. The semiconductor memory device according to claim 15, wherein The thin channel includes polysilicon, silicon germanium or indium gallium zinc oxide.

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