Light-emitting element, light-emitting module including the same, display device, and method of manufacturing the same

Abstract

A light-emitting element, a light-emitting assembly including the same, a display device, and a manufacturing method thereof. The light-emitting element includes: a semiconductor stack, a metal electrode, a transparent electrode, and a connecting member. The metal electrode is located on the semiconductor stack. The transparent electrode is located on a side of the semiconductor stack opposite to the metal electrode. The connecting member extends at least along sidewalls of the semiconductor stack and the transparent electrode, and a surface of the connecting member away from the metal electrode is flush with a surface of the transparent electrode away from the metal electrode.

Description

Technical Field

[0001] The present invention relates to a light-emitting element, a light-emitting assembly including the same, a display device, and a method for manufacturing a display device. Background Art

[0002] Micro light-emitting diodes (micro-LEDs) have characteristics such as low power consumption, high brightness, high resolution, and high color saturation, and are thus suitable for constructing pixel structures of micro-LED display devices. Due to the extremely small size of micro-LEDs, the current method for manufacturing micro-LED display devices is to use mass transfer technology, that is, to use microelectromechanical array technology to pick and place micro-LED chips, so as to transfer a large number of micro-LED chips to a driving backplane with pixel circuits at one time.

[0003] In addition, according to the packaging method, micro-LED chips can be classified into horizontal, vertical, and flip-chip micro-LEDs. As the size of micro-LED chips becomes smaller and smaller, it is expected that vertical micro-LEDs will be able to provide a larger light-emitting area. However, at present, the upper electrode of vertical micro-LEDs uses a metal electrode, resulting in local current concentration on the metal electrode, and the metal electrode will also block light and affect light extraction. Summary of the Invention

[0004] The present invention provides a light-emitting element with good light extraction efficiency.

[0005] The present invention provides a light-emitting assembly with good light extraction efficiency.

[0006] The present invention provides a display device with good light extraction efficiency.

[0007] The present invention provides a method for manufacturing a display device, which can provide a display device with good light extraction efficiency.

[0008] An embodiment of the present invention provides a light-emitting element, including: a semiconductor stack; a metal electrode located on the semiconductor stack; a transparent electrode located on a side of the semiconductor stack opposite to the metal electrode; and a connecting member at least extending on sidewalls of the semiconductor stack and the transparent electrode, and a surface of the connecting member away from the metal electrode is flush with a surface of the transparent electrode away from the metal electrode.

[0009] In an embodiment of the present invention, the above-mentioned connecting member includes silicon oxide, silicon nitride, or a Bragg reflection layer.

[0010] In an embodiment of the present invention, the above-mentioned Bragg reflection layer includes a plurality of overlapping titanium oxide layers and a plurality of silicon oxide layers.

[0011] In one embodiment of the present invention, the semiconductor stack described above includes: a first-type semiconductor pattern located between the metal electrode and the transparent electrode; a second-type semiconductor pattern overlapping the first-type semiconductor pattern and located between the first-type semiconductor pattern and the transparent electrode; and a light-emitting pattern located between the first-type semiconductor pattern and the second-type semiconductor pattern.

[0012] In one embodiment of the present invention, the second-type semiconductor pattern described above includes a P-type semiconductor material.

[0013] In one embodiment of the present invention, the light-emitting element described above further includes a matching pattern located between the semiconductor stack and the transparent electrode.

[0014] One embodiment of the present invention provides a light-emitting assembly, including: a carrier substrate; a plurality of support members located on the carrier substrate; and the above-described light-emitting element suspended between the support members through a connecting member.

[0015] In one embodiment of the present invention, the orthographic projection of the connecting member on the carrier substrate is outside the orthographic projection of the metal electrode on the carrier substrate.

[0016] In one embodiment of the present invention, the connecting member further extends to the plurality of support members.

[0017] In one embodiment of the present invention, the light-emitting assembly further includes a support layer located between the plurality of support members and the light-emitting element and the carrier substrate.

[0018] In one embodiment of the present invention, the support layer is integrally formed with the support members.

[0019] One embodiment of the present invention provides a display device, including: a circuit substrate; and the above-described light-emitting element located on the circuit substrate and electrically connected to the circuit substrate.

[0020] In one embodiment of the present invention, the metal electrode is located between the semiconductor stack and the circuit substrate.

[0021] In one embodiment of the present invention, the circuit substrate further includes a switching element, and the switching element is electrically connected to the transparent electrode or the metal electrode.

[0022] An embodiment of the present invention provides a method for manufacturing a display device, including: providing a growth substrate; forming a multi-layer semiconductor layer on the growth substrate; forming a transparent electrode layer on the multi-layer semiconductor layer; forming an intermediate substrate on the transparent electrode layer; removing the growth substrate; patterning the multi-layer semiconductor layer and the transparent electrode layer to form a semiconductor stack and a transparent electrode; forming a metal electrode on the semiconductor stack; and forming at least a connecting member on the sidewalls of the semiconductor stack and the transparent electrode and on the intermediate substrate, and the surface of the connecting member facing the intermediate substrate is flush with the surface of the transparent electrode facing the intermediate substrate.

[0023] In an embodiment of the present invention, the above forming of the multi-layer semiconductor layer includes: forming a first-type semiconductor layer on the growth substrate; forming a light-emitting layer on the first-type semiconductor layer; and forming a second-type semiconductor layer on the light-emitting layer.

[0024] In an embodiment of the present invention, the above forming of the transparent electrode layer includes: forming a matching layer on the multi-layer semiconductor layer; and forming a transparent electrode layer on the matching layer.

[0025] In an embodiment of the present invention, the above method for manufacturing a display device further includes forming a plurality of support members on the connecting member, and the support members do not overlap the semiconductor stack.

[0026] In an embodiment of the present invention, the above forming of a plurality of support members on the connecting member includes: forming a sacrificial layer on the metal electrode and the connecting member, and the sacrificial layer has a plurality of through holes, the plurality of through holes do not overlap the semiconductor stack and expose the connecting member; and forming support members in each through hole.

[0027] In an embodiment of the present invention, the above sacrificial layer includes an organic material.

[0028] In an embodiment of the present invention, the above method for manufacturing a display device further includes forming a carrier plate on the plurality of support members and the metal electrode.

[0029] In an embodiment of the present invention, after forming the carrier plate, it further includes removing the intermediate substrate.

[0030] In an embodiment of the present invention, after removing the intermediate substrate, it further includes removing the sacrificial layer.

[0031] In an embodiment of the present invention, after removing the sacrificial layer, it further includes: providing a circuit substrate, the circuit substrate includes pads on its surface; transferring the transparent electrode, the semiconductor stack, the metal electrode, and the connecting member onto the pads of the circuit substrate, such that the metal electrode is located between the semiconductor stack and the pads; and electrically connecting the metal electrode and the pads.

[0032] In an embodiment of the present invention, the method for manufacturing the display device further includes electrically connecting a transparent electrode to a switching element of a circuit board.

[0033] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings of the specification as follows. Description of the Drawings

[0034] Figures 1A through 1J is a partial cross-sectional schematic diagram of the process flow of the method for manufacturing a display device 10 according to an embodiment of the present invention.

[0035] Figure 2 is a cross-sectional schematic diagram of a light-emitting component 20A according to an embodiment of the present invention.

[0036] Figure 3 is a partial cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention.

[0037] Description of Reference Numerals:

[0038] 10, 20: Display device

[0039] 10A, 20A: Light-emitting component

[0040] 110: Circuit board

[0041] 112: Bottom plate

[0042] 114: Driving circuit layer

[0043] 120, 120A: Light-emitting element

[0044] CR1, CR2, CR3: Conductive structure

[0045] CS: Carrier board

[0046] EL: Light-emitting layer

[0047] EP: Light-emitting pattern

[0048] Fi, Fr, Fra, Ft: Surface

[0049] GS: Growth substrate

[0050] I1: Buffer layer

[0051] I2: Gate insulating layer

[0052] I3: Interlayer insulating layer

[0053] I4, I5, I6: Insulating layer

[0054] IS: Intermediary substrate

[0055] ME: Metal electrode

[0056] ML: Matching Layer

[0057] MP: Matching Pattern

[0058] PC: Support Component

[0059] PD: Pad

[0060] PL: Support Layer

[0061] SF: Sacrificial Layer

[0062] SL1: First-Type Semiconductor Layer

[0063] SL2: Second-Type Semiconductor Layer

[0064] SP1: First-Type Semiconductor Pattern

[0065] SP2: Second-Type Semiconductor Pattern

[0066] SS: Semiconductor Stack

[0067] T: Switching Element

[0068] TC: Semiconductor Layer

[0069] TD: Drain

[0070] TE: Transparent Electrode

[0071] TG: Gate

[0072] TL: Transparent Electrode Layer

[0073] TR, Tra: Connecting Component

[0074] TS: Source

[0075] V1, V2, V3, V4, VA: Through Hole

[0076] VL1, VL2: Power Line

[0077] We, Wm, Ws, Wt: Side Wall Detailed Implementation Manner

[0078] In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. is enlarged. Throughout the specification, like reference numerals represent like elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, no intervening elements are present. As used herein, "connected" can refer to physical and / or electrical connection. Furthermore, "electrically connected" or "coupled" can mean that other elements exist between two elements.

[0079] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, the first "element", "component", "region", "layer", or "part" discussed below could be termed a second element, component, region, layer, or part without departing from the teachings herein.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one" or indicating "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or combinations thereof.

[0081] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is flipped, an element described as being on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both the "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in one figure is flipped, an element described as being "below" or "beneath" other elements will be oriented as being "above" the other elements. Thus, the exemplary terms "lower" or "beneath" can include both the upper and lower orientations.

[0082] Considering a specific quantity of the measurements being discussed and the errors associated with the measurements (i.e., the limitations of the measurement system), the “about,” “approximate,” or “substantially” used herein includes the stated value and the average value within an acceptable deviation range of the specific value determined by a person of ordinary skill in the art. For example, “approximate” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the “about,” “approximate,” or “substantially” used herein may select a more acceptable deviation range or standard deviation according to optical properties, etching properties, or other properties, instead of applying one standard deviation to all properties.

[0083] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as shown herein, but include, for example, shape deviations resulting from manufacturing. For example, regions shown or described as flat will generally have rough and / or non-linear features. Additionally, the sharp angles shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the exact shape of the regions and are not intended to limit the scope of the claims.

[0084] Figures 1A through 1J is a partial cross-sectional schematic view of a step flow of a manufacturing method of a display device 10 according to an embodiment of the present invention. Please refer to Figure 1A In the step flow of the manufacturing method of the display device 10 in this embodiment, first, a growth substrate GS is provided. The growth substrate GS may be a sapphire substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or other substrates suitable for an epitaxial process, but is not limited thereto.

[0085] Next, in some embodiments, a release layer (not shown in the figure) may be formed on the surface of the growth substrate GS as needed. The release layer may help to subsequently remove the growth substrate GS and also help to perform an epitaxial process subsequently. The material of the release layer is, for example, aluminum nitride (AlN) or gallium nitride (GaN).

[0086] Next, a blanket multi-layer semiconductor layer is formed on the growth substrate GS and the release layer (if any). For example, a first-type semiconductor layer SL1 can be formed on the growth substrate GS and the release layer (if any); then, a light-emitting layer EL is formed on the first-type semiconductor layer SL1; then, a second-type semiconductor layer SL2 is formed on the light-emitting layer EL. The first-type semiconductor layer SL1 and the second-type semiconductor layer SL2 can include II-VI group materials (such as zinc selenide (ZnSe)) or III-V nitride materials (such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN)). For example, in this embodiment, the first-type semiconductor layer SL1 is, for example, an N-type doped semiconductor layer, and the material of the N-type doped semiconductor layer is, for example, N-type gallium nitride (n-GaN). The second-type semiconductor layer SL2, for example, includes a P-type doped semiconductor material, and the P-type doped semiconductor material is, for example, P-type gallium nitride (p-GaN), but is not limited thereto. In this embodiment, the structure of the light-emitting layer EL is, for example, a multiple quantum well structure (MQW). The multiple quantum well structure includes multiple alternating stacked layers of indium gallium nitride (InGaN) and multiple layers of gallium nitride (GaN). By designing the ratio of indium or gallium in the light-emitting layer EL, the emission wavelength range of the light-emitting layer EL can be adjusted, but the present invention is not limited thereto.

[0087] Next, please refer to Figure 1B , a transparent electrode layer TL is formed on the first-type semiconductor layer SL1, the light-emitting layer EL, and the second-type semiconductor layer SL2, and then an intermediate substrate IS is formed on the transparent electrode layer TL. In this embodiment, the material of the transparent electrode layer TL can include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or other suitable conductive oxides, or a stack of any two or more of the above conductive oxides, but is not limited thereto. In this embodiment, the intermediate substrate IS can be disposed on the transparent electrode layer TL by means of attachment, but is not limited thereto.

[0088] In some embodiments, before forming the transparent electrode layer TL, a transparent matching layer ML can be first formed on the first-type semiconductor layer SL1, the light-emitting layer EL, and the second-type semiconductor layer SL2, and then the transparent electrode layer TL is formed on the matching layer ML. The matching layer ML helps the ohmic contact between the second-type semiconductor layer SL2 and the transparent electrode layer TL. The material of the matching layer ML is, for example, P-type gallium nitride (p-GaN), but is not limited thereto.

[0089] Next, please refer to Figure 1C, the growth substrate GS is removed to expose the first-type semiconductor layer SL1. The growth substrate GS can be removed by, for example, heat treatment or laser lift-off process, but is not limited thereto.

[0090] Next, please refer to Figure 1D , the first-type semiconductor layer SL1, the light-emitting layer EL, the second-type semiconductor layer SL2, the matching layer ML, and the transparent electrode layer TL are patterned to form a first-type semiconductor pattern SP1, a light-emitting pattern EP, a second-type semiconductor pattern SP2, a matching pattern MP, and a transparent electrode TE. Among them, the first-type semiconductor pattern SP1, the light-emitting pattern EP, and the second-type semiconductor pattern SP2 can form a semiconductor stack SS.

[0091] Next, a metal electrode ME is formed on the semiconductor stack SS. In some embodiments, a blanket metal electrode layer (not shown in the figure) can be first formed on the first-type semiconductor layer SL1, and then the metal electrode layer, the first-type semiconductor layer SL1, the light-emitting layer EL, the second-type semiconductor layer SL2, the matching layer ML, and the transparent electrode layer TL are patterned to form a transparent electrode TE, a matching pattern MP, a semiconductor stack SS, and a metal electrode ME stacked on the intermediate substrate IS. The material of the metal electrode ME can include metals with good conductivity, such as aluminum (Al), titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), chromium (Cr), etc., alloys of the above metals, or combinations or stacks of the above metals and / or alloys. For example, the metal electrode ME can include metal stacks such as Ti / Al / Ti / Au, Cr / Pt / Au, or Cr / Al / Ti / Pt / Au.

[0092] Next, please refer to Figure 1E, forming a tie TR on the sidewall Ws of the semiconductor stack SS, the sidewall Wm of the matching pattern MP, the sidewall Wt of the transparent electrode TE, and the surface Fi of the intermediate substrate IS. In this way, the tie TR and the transparent electrode TE can both fit the surface Fi of the intermediate substrate IS, so that the surface Fr of the tie TR facing the intermediate substrate IS can be flush with the surface Ft of the transparent electrode TE facing the intermediate substrate IS. The term "flush" used herein means "approximately flush". For example, in some embodiments, due to the tolerable error of the process, the surface Fr and / or the surface Ft may have a surface undulation less than or equal to 3μm, so some areas of the surface Fr and some areas of the surface Ft may have a surface height difference of about 5μm. In some embodiments, some areas of the surface Fr and some areas of the surface Ft may have a surface height difference of about 3μm, 2μm or 1μm. In some embodiments, the tie TR may also be formed on the sidewall We of the metal electrode ME. The material of the tie TR is, for example, silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0093] At this point, the light-emitting element 120 is formed on the intermediate substrate IS, and the light-emitting element 120 may include: a semiconductor stack SS; a metal electrode ME, located on the semiconductor stack SS; a transparent electrode TE, located on a side of the semiconductor stack SS opposite to the metal electrode ME; a matching pattern MP, located between the semiconductor stack SS and the transparent electrode TE; and a connecting member TR, at least extending to the side walls of the semiconductor stack SS and the transparent electrode TE, and a surface Fr of the connecting member TR away from the metal electrode ME is flush with a surface Ft of the transparent electrode TE away from the metal electrode ME, wherein the semiconductor stack SS may include a first-type semiconductor pattern SP1, a second-type semiconductor pattern SP2 and a light-emitting pattern EP, wherein the first-type semiconductor pattern SP1 may be located between the metal electrode ME and the transparent electrode TE, the second-type semiconductor pattern SP2 may overlap the first-type semiconductor pattern SP1 and be located between the first-type semiconductor pattern SP1 and the transparent electrode TE, and the light-emitting pattern EP may be located between the first-type semiconductor pattern SP1 and the second-type semiconductor pattern SP2. The metal electrode ME and the transparent electrode TE of the light emitting element 120 are respectively located on opposite sides of the light emitting pattern EP, that is, the light emitting element 120 is a vertical light emitting diode. In some embodiments, the light emitting element 120 can be a vertical light emitting diode emitting blue light or green light, but is not limited thereto.

[0094] Next, please refer to Figure 1FIn some embodiments, a sacrificial layer SF may be formed on the metal electrode ME and the tie TR, and the sacrificial layer SF may be formed with a plurality of through holes VA, the orthographic projection of each through hole VA on the intermediate substrate IS does not overlap the orthographic projection of the semiconductor stack SS on the intermediate substrate IS, and the through hole VA may expose the portion where the tie TR is attached to the intermediate substrate IS. The sacrificial layer SF may include an organic material, but is not limited thereto. The through hole VA may have an inverted trapezoidal shape that is wide at the top and narrow at the bottom, but is not limited thereto.

[0095] Next, please refer to Figure 1G , a support member PC can also be formed in each through hole VA. Since the through hole VA can expose the connecting member TR, and the through hole VA does not overlap the semiconductor stack SS, the support member PC can connect the connecting member TR, and the support member PC does not overlap the semiconductor stack SS. In some embodiments, a support layer PL can also be formed on the support member PC and the sacrificial layer SF, and the support layer PL can belong to the same film layer as the support member PC. In other words, the support layer PL can be integrally formed with the support member PC, but is not limited to this. In this way, it can be ensured that the support member PC and the sacrificial layer SF have a flat upper surface. The support member PC and / or the support layer PL may include a material with a certain rigidity, such as a metal, and the support member PC and / or the support layer PL may also have a multilayer structure.

[0096] Next, please refer to Figure 1G , a carrier plate CS can also be formed on the support member PC, the metal electrode ME and the support layer PL. For example, the carrier plate CS can be attached to the support layer PL. Figure 1H After forming the carrier board CS, the intermediate substrate IS can be removed, for example, by laser stripping or heat treatment. Figure 1I , after removing the intermediate substrate IS, the sacrificial layer SF can also be removed. For example, the sacrificial layer SF can be removed by exposure and development. At this point, the light-emitting component 10A according to an embodiment of the present invention is completed, and the light-emitting component 10A may include: a carrier CS; a plurality of support members PC, located on the carrier CS; a light-emitting element 120, suspended between the support members PC through a tie member TR; and a support layer PL, located between the plurality of support members PC and the light-emitting element 120 and the carrier CS, wherein a surface Fr of the tie member TR away from the metal electrode ME is flush with a surface Ft of the transparent electrode TE away from the metal electrode ME.

[0097] In some embodiments, the orthographic projection of the tie TR on the carrier CS may be outside the orthographic projection of the metal electrode ME on the carrier CS. In some embodiments, the tie TR also extends on the support PC, so that the tie TR can connect to the support PC.

[0098] Next, please refer toFigure 1J , a circuit board 110 may further be provided after removing the sacrificial layer SF. The circuit board 110 may include pads PD on its surface. Then, a mass transfer process may be performed, that is, the light-emitting elements 120 in the light-emitting assembly 10A are taken out and transferred onto the circuit board 110. For example, the metal electrodes ME of the light-emitting elements 120 are placed on the pads PD, such that the metal electrodes ME are located between the semiconductor stack SS and the pads PD of the circuit board 110. Then, the metal electrodes ME of the light-emitting elements 120 are electrically connected to the pads PD by, for example, heat treatment. Thus, the display device 10 according to an embodiment of the present invention is completed, and the display device 10 may include: a circuit board 110; and light-emitting elements 120, located on the circuit board 110 and electrically connected to the circuit board 110. Since the upper electrodes of the light-emitting elements 120 of the display device 10 are transparent electrodes TE, the current in the light-emitting elements 120 can be evenly distributed on the transparent electrodes TE, and the display device 10 can have good light extraction efficiency.

[0099] For example, the circuit board 110 may include a bottom plate 112 and a driving circuit layer 114. The bottom plate 112 of the circuit board 110 may be a transparent substrate, an opaque substrate, a flexible substrate or a non-flexible substrate, and its material may be a quartz substrate, a glass substrate, a polymer substrate or other suitable materials. The driving circuit layer 114 may include elements or lines required for the display device 10, such as driving elements, switching elements, storage capacitors, power lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and so on. The driving circuit layer 114 may be formed on the bottom plate 112 by using a thin film deposition process, a photolithography process and an etching process. The driving circuit layer 114 may include at least one insulating layer and at least one conductive layer, and the driving circuit layer 114 may include more insulating layers and conductive layers as needed.

[0100] In some embodiments, the driving circuit layer 114 of the circuit substrate 110 may further include a switch element array, where the switch element array includes a plurality of switch elements T arranged in an array, and the switch elements T may be electrically connected to the light-emitting elements 120. Specifically, for example, the driving circuit layer 114 may include switch elements T, power lines VL1, VL2, conductive structures CR1, CR2, pads PD, buffer layer I1, gate insulating layer I2, interlayer insulating layer I3, and insulating layers I4, I5. The switch element T is composed of a semiconductor layer TC, a gate TG, a source TS, and a drain TD. The region where the semiconductor layer TC overlaps the gate TG can be regarded as the channel region of the switch element T. The buffer layer I1 is located between the bottom plate 112 and the semiconductor layer TC, and is used to prevent impurities in the bottom plate 112 from migrating into the semiconductor layer TC and enhance the adhesion between the semiconductor layer TC and the bottom plate 112. The gate insulating layer I2 is located between the gate TG and the semiconductor layer TC. The interlayer insulating layer I3 is disposed between the source TS and the drain TD and the gate TG and the power line VL2. The gate TG and the source TS can respectively receive signals from, for example, driving elements. The insulating layer I4 is disposed between the source TS, the drain TD, and the power line VL1 and the conductive structures CR1, CR2, and the insulating layer I5 is disposed between the conductive structures CR1, CR2 and the pads PD, and the pads PD may be disposed on the insulating layer I5. The conductive structure CR1 can be electrically connected to the power line VL1 through the via V1 in the insulating layer I4, the conductive structure CR2 can be electrically connected to the drain TD through the via V2 in the insulating layer I4, and the pad PD can be electrically connected to the conductive structure CR1 through the via V3 in the insulating layer I5. In some embodiments, the pad PD may not be electrically connected to the conductive structure CR1, and the pad PD may be electrically connected to the conductive structure CR2 through other vias in the insulating layer I5, so that the switch element T can be electrically connected to the metal electrode ME of the light-emitting element 120.

[0101] The material of the semiconductor layer TC may include silicon-based semiconductor materials (such as polysilicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, but is not limited thereto. The materials of the gate TG, the source TS, the drain TD, the power lines VL1, VL2, the conductive structures CR1, CR2, and the pads PD may include metals with good conductivity, such as metals such as aluminum, molybdenum, titanium, copper, etc., but are not limited thereto. In some embodiments, the conductive structures CR1, CR2, and the pads PD may also respectively have a single-layer structure or a multi-layer structure. The multi-layer structure is, for example, a stack of any two or more layers of the above-mentioned conductive metals or conductive oxides, and can be combined and changed as needed. For example, the conductive structure CR1 may include a sequentially stacked titanium layer, aluminum layer, and titanium layer or a sequentially stacked molybdenum layer, aluminum layer, and molybdenum layer, but is not limited thereto.

[0102] The materials of buffer layer I1, gate insulating layer I2, interlayer insulating layer I3, and insulating layers I4 and I5 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a stack of the above materials, but are not limited thereto. In some embodiments, buffer layer I1, gate insulating layer I2, interlayer insulating layer I3, and insulating layers I4 and I5 may also have a single-layer structure or a multi-layer structure respectively. The multi-layer structure is, for example, a stack of any two or more of the above insulating materials, and can be combined and varied as needed.

[0103] In some embodiments, after electrically connecting metal electrode ME and pad PD, transparent electrode TE may also be electrically connected to switching element T of circuit substrate 110. For example, insulating layer I6 may be formed on insulating layer I5, and at least transparent electrode TE of light-emitting element 120 is exposed. Then, via hole V4 is formed to penetrate insulating layers I5 and I6 and expose conductive structure CR2. After that, conductive structure CR3 is formed on transparent electrode TE and in via hole V4, so that transparent electrode TE can be electrically connected to drain TD of switching element T through conductive structure CR3 and conductive structure CR2. The material of conductive structure CR3 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or other suitable conductive oxides. The material of insulating layer I6 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a stack of the above materials, but are not limited thereto.

[0104] In certain embodiments, when pad PD is electrically connected to conductive structure CR2, a via hole may be formed to penetrate insulating layers I5 and I6 and expose conductive structure CR1, and then another conductive structure is formed on transparent electrode TE and in the via hole exposing conductive structure CR1 to electrically connect transparent electrode TE and power supply line VL1.

[0105] Hereinafter, use Figures 2 through 3 Continue to describe other embodiments of the present invention, and, continue to use Figures 1A through 1J the component numbers and related content of the embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to Figures 1A through 1J the embodiments, and will not be repeated in the following description.

[0106] Figure 2A cross-sectional schematic view of a light-emitting component 20A according to an embodiment of the present invention. The light-emitting component 20A may include: a carrier substrate CS; a plurality of support members PC located on the carrier substrate CS; a light-emitting element 120A suspended between the support members PC by a connecting member TRa; and a support layer PL located between the plurality of support members PC, the light-emitting element 120A, and the carrier substrate CS. Among them, the surface Fra of the connecting member TRa away from the metal electrode ME is flush with the surface Ft of the transparent electrode TE away from the metal electrode ME.

[0107] Compared with the light-emitting component 10A as Figure 1I shown, Figure 2 the difference between the light-emitting component 20A shown and the light-emitting component 10A is that the connecting member TRa of the light-emitting element 120A of the light-emitting component 20A may include a distributed Bragg reflector (DBR). Among them, the distributed Bragg reflector of the connecting member TRa may include, for example, a plurality of overlapping titanium oxide (TiO2) layers and a plurality of silicon oxide (SiO2) layers. By setting the connecting member TRa including the distributed Bragg reflector to control the full penetration or total reflection of a specific wavelength band for light filtering, it can be ensured that the light emitted by the light-emitting element 120A provided by the light-emitting component 20A can be completely color-converted, and the wavelength band of total reflection can be color-converted again to increase the light intensity. In addition, since the upper electrode of the light-emitting element 120A is a transparent electrode TE, when the light-emitting element 120A is energized, the light-emitting element 120A can have good light extraction efficiency, and the current can be evenly distributed on the transparent electrode TE.

[0108] Figure 3 A partial cross-sectional schematic view of a display device 20 according to an embodiment of the present invention. The display device 20 may include: a circuit substrate 110; and a light-emitting element 120A located on the circuit substrate 110 and electrically connected to the circuit substrate 110.

[0109] Compared with the display device 10 as Figure 1J shown, Figure 3The difference of the display device 20 shown is that the connecting member TRa of the light-emitting element 120A of the display device 20 may include a Distributed Bragg Reflector (DBR). Among them, the Bragg reflector layer of the connecting member TRa may include, for example, multiple overlapping titanium oxide (TiO2) layers and multiple silicon oxide (SiO2) layers. By setting the connecting member TRa including the Bragg reflector layer to control the full penetration or total reflection of a specific wavelength band for light filtering, it can ensure complete color light conversion of the display device 20, and the wavelength band of total reflection can be subjected to light color conversion again to increase the light intensity, thereby improving the full-color display effect of the display device 20. In addition, since the upper electrode of the light-emitting element 120A in the display device 20 is a transparent electrode TE, the current in the light-emitting element 120A can be evenly distributed on the transparent electrode TE, and the display device 20 can provide good light extraction efficiency.

[0110] In summary, for the light-emitting element, the light-emitting component, and the display device of the present invention, by making the upper electrode of the vertical light-emitting element a transparent electrode, the current in the light-emitting element can be evenly distributed on the transparent upper electrode, and the light-emitting element, the light-emitting component, and the display device can have good light extraction efficiency.

[0111] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to what is defined by the claims.

Claims

1. A light-emitting element, comprising: A semiconductor stack; A metal electrode located on the semiconductor stack; A transparent electrode located on a side of the semiconductor stack opposite to the metal electrode; And A connecting member extending at least along sidewalls of the semiconductor stack and the transparent electrode, and a surface of the connecting member away from the metal electrode being flush with a surface of the transparent electrode away from the metal electrode, Wherein a positive projection of the connecting member in a direction perpendicular to the transparent electrode is outside a positive projection of the metal electrode in the direction perpendicular to the transparent electrode.

2. The light-emitting element according to claim 1, wherein the connecting member comprises silicon oxide, silicon nitride, or a Bragg reflection layer.

3. The light-emitting element according to claim 2, wherein the Bragg reflection layer comprises a plurality of overlapping titanium oxide layers and a plurality of silicon oxide layers.

4. The light-emitting element according to claim 1, wherein the semiconductor stack comprises: A first-type semiconductor pattern located between the metal electrode and the transparent electrode; A second-type semiconductor pattern overlapping the first-type semiconductor pattern and located between the first-type semiconductor pattern and the transparent electrode; And A light-emitting pattern located between the first-type semiconductor pattern and the second-type semiconductor pattern.

5. The light-emitting element according to claim 4, wherein the second-type semiconductor pattern comprises a P-type semiconductor material.

6. The light-emitting element according to claim 1, further comprising a matching pattern located between the semiconductor stack and the transparent electrode.

7. A light-emitting assembly, comprising: A carrier substrate; A plurality of support members located on the carrier substrate; And The light-emitting element according to any one of claims 1 to 6, suspended between the support members through the connecting member.

8. The light-emitting assembly according to claim 7, wherein a positive projection of the connecting member on the carrier substrate is outside a positive projection of the metal electrode on the carrier substrate.

9. The light-emitting assembly according to claim 7, wherein the connecting member further extends onto the plurality of support members.

10. The light-emitting assembly according to claim 7, further comprising a support layer located between the plurality of support members, the light-emitting element, and the carrier substrate.

11. The light-emitting assembly according to claim 10, wherein the support layer is integrally formed with the support members.

12. A display device, comprising: A circuit substrate; And The light-emitting element according to any one of claims 1 to 6, located on the circuit substrate and electrically connected to the circuit substrate.

13. The display device according to claim 12, wherein the metal electrode is located between the semiconductor stack and the circuit substrate.

14. The display device according to claim 12, wherein the circuit substrate further comprises a switching element, and the switching element is electrically connected to the transparent electrode or the metal electrode.

15. A manufacturing method of a display device, comprising: Providing a growth substrate; Forming a multi-layer semiconductor layer on the growth substrate; Forming a transparent electrode layer on the multi-layer semiconductor layer; Forming an intermediate substrate on the transparent electrode layer; Removing the growth substrate; Pattern the multi-layer semiconductor layer and the transparent electrode layer to form a semiconductor stack and a transparent electrode; Form a metal electrode on the semiconductor stack; And Form at least a connecting member on the sidewalls of the semiconductor stack and the transparent electrode and on the intermediate substrate, and a surface of the connecting member facing the intermediate substrate is flush with a surface of the transparent electrode facing the intermediate substrate, Wherein a positive projection of the connecting member in a direction perpendicular to the transparent electrode layer is outside a positive projection of the metal electrode in a direction perpendicular to the transparent electrode layer.

16. The method for manufacturing a display device according to claim 15, wherein forming the multi-layer semiconductor layer includes: Form a first-type semiconductor layer on the growth substrate; Form a light-emitting layer on the first-type semiconductor layer; And Form a second-type semiconductor layer on the light-emitting layer.

17. The method for manufacturing a display device according to claim 15, wherein forming the transparent electrode layer includes: Form a matching layer on the multi-layer semiconductor layer; And Form a transparent electrode layer on the matching layer.

18. The method for manufacturing a display device according to claim 15, further comprising forming a plurality of support members on the connecting member, and the support members do not overlap the semiconductor stack.

19. The method for manufacturing a display device according to claim 18, wherein forming the plurality of support members on the connecting member includes: Form a sacrificial layer on the metal electrode and the connecting member, and the sacrificial layer has a plurality of through holes, the plurality of through holes do not overlap the semiconductor stack and expose the connecting member; And Form the support members in each of the through holes.

20. The method for manufacturing a display device according to claim 19, wherein the sacrificial layer includes an organic material.

21. The method for manufacturing a display device according to claim 18, further comprising forming a carrier plate on the plurality of support members and the metal electrode.

22. The method for manufacturing a display device according to claim 21, wherein after forming the carrier plate, the intermediate substrate is removed.

23. The method for manufacturing a display device according to claim 22, wherein after removing the intermediate substrate, the sacrificial layer formed on the metal electrode and the connecting member is removed.

24. The method for manufacturing a display device according to claim 23, wherein after removing the sacrificial layer, further comprising: Provide a circuit substrate, the circuit substrate includes pads on its surface; Transfer the transparent electrode, the semiconductor stack, the metal electrode and the connecting member onto the pads of the circuit substrate, such that the metal electrode is located between the semiconductor stack and the pads; And Electrically connect the metal electrode and the pads.

25. The method for manufacturing a display device according to claim 24, further comprising electrically connecting the transparent electrode and a switching element of the circuit substrate.

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