Display panel and method for manufacturing the same

Abstract

The present invention discloses a display panel and a manufacturing method thereof. The display panel includes a first conduction layer, an insulating layer, a spacer layer, and a second conduction layer; the first conduction layer includes an auxiliary electrode and a first test electrode; the insulating layer is disposed on one side of the first conduction layer and includes a first insulator portion and a second insulator portion, the first insulator portion includes a plurality of openings, one opening corresponding to one auxiliary electrode, and the second insulator portion is disposed on one side of the first test electrode; the spacer layer is disposed at least on one side of the first insulator portion away from the first conduction layer; the second conduction layer is disposed on one side of the spacer layer away from the insulating layer and includes a second test electrode, and the second test electrode is disposed on one side of the second insulator portion away from the first test electrode; the first insulator portion is provided with a first undercut opening at the opening, and the second insulator portion is provided with a second undercut opening. The present invention can effectively measure the depth of the second undercut opening to obtain the depth of the first undercut opening and reduce the production cost.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a manufacturing method thereof. Background Art

[0002] Currently, most mainstream Organic Light-Emitting Diode (OLED) displays are of a top-emitting structure. The top-emitting structure requires that the planar cathode in the OLED needs to have sufficient light-transmitting characteristics. This requirement leads to the use of special materials or relatively thin film thicknesses for the planar cathode, resulting in an increase in the planar cathode resistance and a serious voltage drop (IR Drop) phenomenon in the display. To solve the voltage drop caused by this situation, the top-emitting structure OLED mostly adopts an in-plane auxiliary cathode, which is connected in parallel with the planar cathode to reduce the voltage drop caused by the planar cathode.

[0003] Generally, side etching needs to be performed in the film layer above the auxiliary electrode to form an undercut opening structure, so that the planar cathode can extend into the undercut opening to overlap with the auxiliary electrode. However, the current method for measuring the side etching depth is: scrapping and fragmenting the product, and then using a measuring instrument to measure the side etching depth; this method has a long test cycle, cannot detect abnormal side etching depth in a timely manner, and causes production waste. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a manufacturing method thereof, which can effectively measure the side etching depth above the auxiliary electrode and reduce the production cost.

[0005] Embodiments of the present invention provide a display panel, which includes a display area and a non-display area adjacent to the display area;

[0006] The display panel further includes:

[0007] A first conductive layer, including a plurality of auxiliary electrodes disposed in the display area, and at least one first test electrode and at least one first test terminal disposed in the non-display area, and one of the first test electrodes is electrically connected to one of the first test terminals;

[0008] An insulating layer, disposed on one side of the first conductive layer, and including a first insulating part disposed in the display area and a second insulating part disposed in the non-display area. The first insulating part includes a plurality of openings, and one of the openings corresponds to one of the auxiliary electrodes. The second insulating part is disposed on one side of one of the first test electrodes;

[0009] A spacer layer, disposed at least on a side of the first insulating part away from the first conductive layer;

[0010] A second conductive layer is disposed on a side of the spacer layer away from the insulating layer, and includes at least one second test electrode and at least one second test terminal disposed in the non-display area. One of the second test electrodes is electrically connected to one of the second test terminals, and one of the second test electrodes is disposed on a side of one of the second insulating parts away from the corresponding first test electrode.

[0011] Wherein, at the opening, a first undercut opening located between the spacer layer and the auxiliary electrode is provided in the first insulating part, and a second undercut opening located between the second test electrode and the first test electrode is provided in the second insulating part.

[0012] In an embodiment of the present invention, the spacer layer includes a first sub-part disposed on a side of the first insulating part away from the first conductive layer, and a second sub-part connected to the first sub-part and extending above the auxiliary electrode relative to the first sub-part. Wherein, the distance that the second sub-part extends above the auxiliary electrode relative to the first sub-part is equal to the depth of the first undercut opening and equal to the depth of the second undercut opening.

[0013] In an embodiment of the present invention, the spacer layer further includes a third sub-part disposed in the non-display area and connected to the second insulating part. The second test terminal is disposed on a side of the third sub-part away from the first conductive layer, and a surface of the third sub-part away from the first conductive layer is flush with a surface of the second insulating part away from the first test electrode.

[0014] In an embodiment of the present invention, the first conductive layer further includes a first connection part connected between the first test electrode and the first test terminal, and the second conductive layer further includes a second connection part disposed on a side of the third sub-part away from the first conductive layer and connected between the second test electrode and the second test terminal.

[0015] In an embodiment of the present invention, the first conductive layer further includes a plurality of source electrodes and a plurality of drain electrodes disposed in the display area, and the second conductive layer further includes a plurality of anodes disposed on a side of the first sub-part away from the first insulating part, and one of the anodes is electrically connected to one of the drain electrodes.

[0016] According to the above object of the present invention, an embodiment of the present invention further provides a method for manufacturing a display panel. The display panel includes a display area and a non-display area adjacent to the display area, and the method for manufacturing the display panel includes the following steps:

[0017] Form a first conductive layer, where the first conductive layer includes a plurality of auxiliary electrodes formed in the display area, and at least one first test electrode and at least one first test terminal formed in the non-display area, and one of the first test electrodes is electrically connected to one of the first test terminals;

[0018] Form an insulating layer on one side of the first conductive layer. The insulating layer includes a first insulator portion formed in the display area and a second insulator portion formed in the non-display area. The first insulator portion includes a plurality of openings, and one of the openings corresponds to one of the auxiliary electrodes. One of the second insulator portions is formed on one side of one of the first test electrodes;

[0019] Form a spacer layer at least on the side of the first insulator portion away from the first conductive layer;

[0020] Form a second conductive layer on the side of the spacer layer away from the insulating layer. The second conductive layer includes at least one second test electrode and at least one second test terminal formed in the non-display area, and one of the second test electrodes is electrically connected to one of the second test terminals. One of the second test electrodes is formed on the side of one of the second insulator portions away from the corresponding one of the first test electrodes;

[0021] Etch the insulating layer so that at the opening, a first undercut opening located between the spacer layer and the auxiliary electrode is formed in the first insulator portion, and a second undercut opening located between the second test electrode and the first test electrode is formed in the second insulator portion;

[0022] Obtain the etched capacitance between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening.

[0023] In an embodiment of the present invention, before the step of obtaining the etched capacitance between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening, the following steps are further included:

[0024] Obtain the width of the second insulator portion in the first direction and the thickness of the second insulator portion. The first direction is perpendicular to the depth direction of the second undercut opening;

[0025] Obtain the pre-etch length of the second insulator portion in the second direction before the insulating layer is etched. The second direction is the depth direction of the second undercut opening;

[0026] Obtaining the capacitance after etching between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening further includes the following steps:

[0027] Determine the depth of the second undercut opening according to the width of the second insulator portion in the first direction, the thickness of the second insulator portion, the length before etching, and the capacitance after etching.

[0028] In an embodiment of the present invention, the step of obtaining the length before etching of the second insulator portion in the second direction before the etching process of the insulating layer includes the following steps:

[0029] Before the etching process of the insulating layer, use an optical line width measuring instrument to measure the length before etching.

[0030] In an embodiment of the present invention, the step of obtaining the length before etching of the second insulator portion in the second direction before the etching process of the insulating layer includes the following steps:

[0031] Before the etching process of the insulating layer, connect the two probes of the capacitance testing instrument to the first test terminal and the second test terminal respectively to measure the capacitance before etching between the first test electrode and the second test electrode;

[0032] Obtain the length before etching according to the formula shown below;

[0033]

[0034] Wherein, W1 is the length before etching, C1 is the capacitance before etching, d is the thickness of the second insulator portion, k is the electrostatic constant, and L is the width of the second insulator portion in the first direction.

[0035] In an embodiment of the present invention, the step of obtaining the capacitance after etching between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening further includes the following steps:

[0036] After the etching process of the insulating layer, connect the two probes of the capacitance testing instrument to the first test terminal and the second test terminal respectively to measure the capacitance after etching between the first test electrode and the second test electrode;

[0037] Obtain the length after etching of the second insulator portion in the first direction according to the formula shown below;

[0038]

[0039] Wherein, W2 is the length after etching, C2 is the capacitance after etching, d is the thickness of the second insulator portion, k is the electrostatic constant, and L is the width of the second insulator portion in the first direction;

[0040] Determine the depth of the second undercut opening according to the length before etching and the length after etching.

[0041] Advantages of the present invention: An auxiliary electrode is formed in the display area of the present invention. An opening is formed in the first insulator portion corresponding to the auxiliary electrode to expose the auxiliary electrode. And at the opening, a first undercut opening located between the spacer layer and the auxiliary electrode is provided in the first insulator portion; at the same time, a first test electrode and a first test terminal on the same layer as the auxiliary electrode, a second insulator portion on the same layer as the first insulator portion, and a second test electrode and a second test terminal are formed in the non-display area of the present invention. Among them, the first test electrode, the second insulator portion, and the second test electrode are stacked to form a capacitive structure. The first test electrode is electrically connected to the first test terminal, the second test electrode is electrically connected to the second test terminal, and a second undercut opening located between the second test electrode and the first test electrode is provided in the second insulator portion. Furthermore, the capacitance between the first test electrode and the second test electrode can be measured through the first test terminal and the second test terminal, and the size of the second insulator portion can be obtained according to the capacitance calculation formula. According to the difference between the size of the second insulator portion before etching and the size after etching, the depth of the second undercut opening can be obtained. And since the second insulator portion is prepared on the same layer as the first insulator portion, the depth of the second undercut opening can be regarded as the depth of the first undercut opening, and the depth of the first undercut opening can be obtained without scrapping and dicing the display panel, reducing the production cost. Description of the Drawings

[0042] The following will clearly show the technical solutions and other beneficial effects of the present invention by describing the specific embodiments of the present invention in detail with reference to the drawings.

[0043] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0044] Figure 2 It is a schematic structural diagram of the first undercut opening and the second undercut opening provided by an embodiment of the present invention;

[0045] Figure 3 It is a schematic connection structural diagram of the first test electrode, the second test electrode, the first test terminal, and the second test terminal provided by an embodiment of the present invention;

[0046] Figure 4 It is a flowchart of a manufacturing method of a display panel provided by an embodiment of the present invention;

[0047] Figure 5 Schematic diagram of the depth measurement system module for the first undercut opening and the second undercut opening of the display panel provided by the embodiment of the present invention. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0049] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0050] The embodiment of the present invention provides a display panel. Please refer to Figure 1 , the display panel includes a display area AA and a non-display area BA adjacent to the display area AA.

[0051] Further, the display panel further includes a first conductive layer 10, an insulating layer 20, a spacer layer 30, and a second conductive layer 40; the first conductive layer 10 includes a plurality of auxiliary electrodes 11 disposed in the display area AA, and at least one first test electrode 12 and at least one first test terminal 13 disposed in the non-display area BA, and a first test electrode 12 is electrically connected to a test terminal 13; the insulating layer 20 is disposed on one side of the first conductive layer 10 and includes a first insulator portion 21 disposed in the display area AA and a second insulator portion 22 disposed in the non-display area BA. The first insulator portion 21 includes a plurality of openings 201, and an opening 201 corresponds to an auxiliary electrode 11. A second insulator portion 22 is disposed on one side of a first test electrode 12; the spacer layer 30 is disposed at least on the side of the first insulator portion 21 away from the first conductive layer 10; the second conductive layer 40 is disposed on the side of the spacer layer 30 away from the insulating layer 20 and includes at least one second test electrode 41 and at least one second test terminal 42 disposed in the non-display area AA, and a second test electrode 41 is electrically connected to a second test terminal 42. A second test electrode 41 is disposed on the side of a second insulator portion 22 away from the corresponding first test electrode 12.

[0052] Wherein, at the opening 201, a first undercut opening 210 located between the spacer layer 30 and the auxiliary electrode 11 is provided in the first insulator portion 21, and a second undercut opening 220 located between the second test electrode 41 and the first test electrode 12 is provided in the second insulator portion 22.

[0053] During the implementation and application process, in the embodiment of the present invention, an auxiliary electrode 11 is formed in the display area AA. An opening 201 is formed in the first insulator part 21 corresponding to the auxiliary electrode 11, which can expose the auxiliary electrode 11. And at the opening 201, a first undercut opening 210 located between the spacer layer 30 and the auxiliary electrode 11 is provided in the first insulator part 21. At the same time, in the non-display area BA of the present invention, a first test electrode 12 and a first test terminal 13 of the same layer as the auxiliary electrode 11, a second insulator part 22 of the same layer as the first insulator part 21, and a second test electrode 41 and a second test terminal 42 are formed. Among them, the first test electrode 12, the second insulator part 22, and the second test electrode layer 41 are stacked to form a capacitive structure. The first test electrode 12 is electrically connected to the first test terminal 13, and the second test electrode 41 is electrically connected to the second test terminal 42. And a second undercut opening 220 located between the second test electrode 41 and the first test electrode 12 is provided in the second insulator part 22. Furthermore, the capacitance between the first test electrode 12 and the second test electrode 41 can be measured through the first test terminal 13 and the second test terminal 42, and the size of the second insulator part 22 can be obtained according to the capacitance calculation formula. According to the difference between the size of the second insulator part 22 before etching and the size after etching, the depth of the second undercut opening 220 can be obtained. And since the second insulator part 22 is prepared on the same layer as the first insulator part 21, the depth of the second undercut opening 220 can be regarded as the depth of the first undercut opening 210. And the depth of the first undercut opening 210 can be obtained without scrapping and dicing the display panel, reducing the production cost.

[0054] Specifically, please refer to Figure 1 , in the embodiment of the present invention, the display panel includes a display area AA and a non-display area BA adjacent to the display area AA.

[0055] Among them, the display panel includes a substrate 51, a buffer layer 52 provided on the substrate 51, a light-shielding layer 61 provided on the buffer layer 52, a passivation layer 53 provided on the buffer layer 52 and covering the light-shielding layer 61, an active layer 62 provided on the passivation layer 53, a gate insulating layer 63 provided on the active layer 62, a gate 64 provided on the gate insulating layer 63, an interlayer dielectric layer 54 provided on the passivation layer 53 and covering the active layer 62, the gate insulating layer 63 and the gate 64, a first conductive layer 10 provided on the interlayer dielectric layer 54, an insulating layer 20 provided on the first conductive layer 10, a spacer layer 30 provided on the insulating layer 20, a second conductive layer 40 provided on the spacer layer 30, and a pixel definition layer 55 provided on the second conductive layer 40.

[0056] It can be understood that the buffer layer 52, the passivation layer 53, and the interlayer dielectric layer 54 are stacked on the substrate 51 and cover the light-shielding layer 61, the active layer 62, and the gate electrode 64. The above-mentioned film layers can be realized with reference to conventional processes and will not be elaborated here.

[0057] Further, the first conduction layer 10 is disposed on the interlayer dielectric layer 54. The first conduction layer 10 includes a plurality of auxiliary electrodes 11, a plurality of source electrodes 15, and a plurality of drain electrodes 16 disposed in the display area AA. The first conduction layer 10 further includes at least one first test electrode 12 and at least one first test terminal 13 disposed in the non-display area BA. Among them, each source electrode 15 and each drain electrode 16 are overlapped with both sides of an active layer 62 through vias passing through the interlayer dielectric layer 54 and the passivation layer 53. A first test electrode 12 is electrically connected to a first test terminal 13.

[0058] The insulating layer 20 is disposed on the first conduction layer 10. The insulating layer 20 includes a first insulator portion 21 disposed in the display area AA and a second insulator portion 22 disposed in the non-display area BA. Among them, the first insulator portion 21 covers a plurality of source electrodes 15, and the first insulator portion 21 includes a plurality of openings 201 and a plurality of first vias. An opening 201 is provided for one auxiliary electrode 11 to expose a part of the upper surface of the corresponding auxiliary electrode 11. A first via correspondingly exposes a part of the upper surface of a drain electrode 16. The second insulator portion 22 is disposed on the second test electrode 41.

[0059] The spacer layer 30 is disposed on the insulating layer 20. The spacer layer 30 includes a plurality of second vias and a plurality of first alignment openings disposed in the display area AA. Among them, a second via is correspondingly disposed and communicated with a first via, and a first alignment opening is correspondingly disposed and communicated with an opening 201.

[0060] The second conduction layer 40 is disposed on the spacer layer 30. The second conduction layer 40 includes a plurality of anodes 43 disposed in the display area AA and at least one second test electrode 41 and at least one second test terminal 42 disposed in the non-display area BA. Among them, each anode 43 is correspondingly disposed for a second via and is overlapped with a drain electrode 16 through a corresponding second via and a first via. A second test electrode 41 is electrically connected to a second test terminal 42. The second test electrode 41 is disposed on a side of the second insulator portion 22 away from the first test electrode 12. That is, the first test electrode 12, the second insulator portion 22, and the second test electrode 41 are stacked on the interlayer dielectric layer 54, and the first test electrode 12 and the second test electrode 41 can form a capacitive structure.

[0061] The pixel definition layer 55 includes a plurality of pixel openings and a plurality of second alignment openings. Each pixel opening corresponds to an anode 43 and exposes a part of the upper surface of the corresponding anode 43. Each second alignment opening is correspondingly arranged and communicated with a first alignment opening. Thus, an opening 201, a first alignment opening, and a second alignment opening are communicated to expose a part of the upper surface of the corresponding auxiliary electrode 11.

[0062] In an embodiment of the present invention, at the opening 201, a first undercut opening 210 located between the spacer layer 30 and the auxiliary electrode 11 is provided in the first insulator part 21, and a second undercut opening 220 located between the second test electrode 41 and the first test electrode 12 is provided in the second insulator part 22. Specifically, at the opening 201, the side wall of the first insulator part 21 is retracted relative to the side wall of the spacer layer 30 to form the first undercut opening 210, while the side wall of the second insulator part 22 is retracted relative to the side wall of the second test electrode 41 to form the second undercut opening 220.

[0063] Among them, the spacer layer 30 includes a first sub-part 31 and a second sub-part 32 provided in the display area AA. The first sub-part 31 is provided on the first insulator part 21, the second sub-part 32 is connected to the first sub-part 31 and extends above the auxiliary electrode 11, and the length of the second sub-part 32 extending above the auxiliary electrode 11 is equal to the depth of the first undercut opening 210. In an embodiment of the present invention, the second undercut opening 220 is formed in the second insulator part 22, and the second insulator part 22 is prepared on the same layer as the first insulator part 21 and belongs to the insulating layer 20. Thus, the first undercut opening 210 and the second undercut opening 220 are obtained in the same side etching process, and the depth of the second undercut opening 220 can be equal to the depth of the first undercut opening 210. However, due to process errors and other factors, the depth of the second undercut opening 220 and the depth of the first undercut opening 210 may not be the same. However, because they are prepared on the same layer and formed in the same side etching process, that is, the depth difference between the second undercut opening 220 and the first undercut opening 210 is small and can be regarded as equal. Thus, the depth of the first undercut opening 210 can be obtained by measuring the depth of the second undercut opening 220.

[0064] Further, please refer to Figure 1 and Figure 2, the spacer layer 30 further includes a third sub - part 33 disposed in the non - display area BA, and the second test terminal 42 is disposed on the side of the third sub - part 33 away from the first conduction layer 10. In addition, the first conduction layer 10 further includes a first connection part 14 disposed on the interlayer dielectric layer 54 and within the non - display area BA, and a second connection part 44 disposed on the side of the third sub - part 33 away from the first conduction layer 10. Among them, the first connection part 14 is connected between the first test electrode 12 and the first test terminal 13, and the second connection part 44 is connected between the second test electrode 41 and the second test terminal 42. In the embodiment of the present invention, the third sub - part 33 is connected to the second insulator part 22, and the surface of the third sub - part 33 on the side away from the first conduction layer 10 is flush with the surface of the second insulator part 22 on the side away from the first test electrode 12. Furthermore, the second connection part 44 is disposed on the third sub - part 33 and extends towards the second test electrode 41 to be connected to the second test electrode 41. The upper surface of the third sub - part 33 is flush with the upper surface of the second insulator part 22, thereby improving the connection stability and the yield rate of the second connection part 44 and the second test electrode 41.

[0065] It should be noted that the display panel provided by the embodiment of the present invention further includes an organic light - emitting layer and a cathode layer disposed on the pixel definition layer 55. Among the circumferences of the opening 201, at least one side does not have the first undercut opening 210. The organic light - emitting layer and the cathode layer are separated above the first undercut opening 210 and extend from the opening 201 where there is no first undercut opening 210 into the opening 201. By controlling the evaporation angle of the cathode layer, the cathode layer covers the organic light - emitting layer within the opening 201 and extends into the undercut opening 210 to overlap with the auxiliary electrode 11, so as to reduce the surface resistance of the cathode layer and improve the voltage drop phenomenon of the display panel. In the related art, the undercut opening is generally obtained by side etching, and it is necessary to test the side etching depth of the undercut opening. The commonly used test method is to scrap and break the display panel, and then use a measuring instrument to measure the side etching depth. This method has a long test cycle, and it is impossible to timely detect the abnormal situation of the side etching depth, resulting in production waste.

[0066] However, in the embodiment of the present invention, the capacitance between the first test electrode 12 and the second test electrode 41 can be measured through the first test terminal 13 and the second test terminal 42, and the size of the second insulator part 22 can be obtained according to the capacitance calculation formula. According to the difference between the size of the second insulator part 22 before etching and after etching, the depth of the second undercut opening 220 can be obtained. Since the second insulator part 22 and the first insulator part 21 are prepared in the same layer, the depth of the second undercut opening 220 can be regarded as the depth of the first undercut opening 210, and the depth of the first undercut opening 210 can be obtained without scrapping and breaking the display panel, reducing the production cost.

[0067] In addition, an embodiment of the present invention further provides a method for manufacturing the above display panel. Please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 . The display panel includes a display area AA and a non-display area BA. The method for manufacturing the display panel includes the following steps:

[0068] S10. Form a first conductive layer 10. The first conductive layer 10 includes a plurality of auxiliary electrodes 11 formed in the display area AA, at least one first test electrode 12 and at least one first test terminal 13 formed in the non-display area BA, and one first test electrode 12 is electrically connected to one first test terminal 13.

[0069] Provide a substrate 51, form a buffer layer 52 on the substrate 51, form a light-shielding layer 61 on the buffer layer 52, form a passivation layer 53 covering the light-shielding layer 61 on the buffer layer 52, form an active layer 62 on the passivation layer 53, form a gate insulating layer 63 on the active layer 62, form a gate 64 on the gate insulating layer 63, and form an interlayer dielectric layer 54 covering the active layer 62, the gate insulating layer 63 and the gate 64 on the passivation layer 53.

[0070] Then, form a first conductive layer 10 on the interlayer dielectric layer 54. The first conductive layer 10 includes a plurality of auxiliary electrodes 11, a plurality of source electrodes 15 and a plurality of drain electrodes 16 formed in the display area AA. The first conductive layer 10 further includes at least one first test electrode 12 and at least one first test terminal 13 formed in the non-display area BA. Each source electrode 15 and each drain electrode 16 are lapped on both sides of an active layer 62 through vias passing through the interlayer dielectric layer 54 and the passivation layer 53, and one first test electrode 12 is electrically connected to one first test terminal 13.

[0071] S20. Form an insulating layer 20 on one side of the first conductive layer 10. The insulating layer 20 includes a first insulator part 21 formed in the display area AA and a second insulator part 22 formed in the non-display area BA. The first insulator part 21 includes a plurality of openings 201, and one opening 201 is provided corresponding to one auxiliary electrode 11. The second insulator part 22 is formed on one side of one first test electrode 12.

[0072] An insulating layer 20 is formed on the first conductive layer 10, and the insulating layer 20 includes a first insulator portion 21 formed in the display area AA and a second insulator portion 22 formed in the non-display area BA. Among them, the first insulator portion 21 covers a plurality of source electrodes 15, and the first insulator portion 21 includes a plurality of openings 201 and a plurality of first vias. One opening 201 is provided for one auxiliary electrode 11 to expose a part of the upper surface of the corresponding auxiliary electrode 11, and one first via correspondingly exposes a part of the upper surface of a drain electrode 16. The second insulator portion 22 is formed on the second test electrode 41.

[0073] S30. Form a spacer layer 30 at least on the side of the first insulator portion 21 away from the first conductive layer 10.

[0074] The spacer layer 30 is formed on the insulating layer 20, and the spacer layer 30 includes a plurality of second vias and a plurality of first alignment openings formed in the display area AA. Among them, one second via is correspondingly provided and communicated with one first via, and one first alignment opening is correspondingly provided and communicated with one opening 201.

[0075] S40. Form a second conductive layer 40 on the side of the spacer layer 30 away from the insulating layer 20. The second conductive layer 40 includes at least one second test electrode 41 and at least one second test terminal 42 formed in the non-display area BA, and one second test electrode 41 is electrically connected to one second test terminal 42. One second test electrode 41 is formed on the side of one second insulator portion 22 away from the corresponding first test electrode 12.

[0076] The second conductive layer 40 is formed on the spacer layer 30. The second conductive layer 40 includes a plurality of anodes 43 formed in the display area AA and at least one second test electrode 41 and at least one second test terminal 42 formed in the non-display area BA. Among them, each anode 43 is correspondingly provided for one second via and is overlapped with one drain electrode 16 through the corresponding one second via and one first via. One second test electrode 41 is electrically connected to one second test terminal 42, and the second test electrode 41 is disposed on the side of the second insulator portion 22 away from the first test electrode 12. That is, the first test electrode 12, the second insulator portion 22, and the second test electrode 41 are stacked on the interlayer dielectric layer 54, and the first test electrode 12 and the second test electrode 41 can form a capacitive structure.

[0077] S50. Etch the insulating layer 20 so that at the opening 201, a first undercut opening 210 located between the spacer layer 30 and the auxiliary electrode 11 is formed in the first insulator portion 21, and a second undercut opening 220 located between the second test electrode 41 and the first test electrode 12 is formed in the second insulator portion 22.

[0078] Perform side etching on the insulating layer 20, specifically including performing side etching at the opening 201 and at the second insulator portion 22, so as to form a first undercut opening 210 between the spacer layer 30 and the auxiliary electrode 11 in the first insulator portion 21 at the opening 201, and form a second undercut opening 220 between the second test electrode 41 and the first test electrode 12 in the second insulator portion 22. Specifically, the side wall of the first insulator portion 21 located inside the opening 201 is retracted relative to the side wall of the spacer layer 30 to form the first undercut opening 210, and the side wall of the second insulator portion 22 is retracted relative to the side wall of the second test electrode 41 to form the second undercut opening 220.

[0079] In the embodiment of the present invention, the first insulator portion 21 and the second insulator portion 22 both belong to the insulating layer 20. Therefore, since the first undercut opening 210 and the second undercut opening 220 are formed in the same film layer in the same etching process, furthermore, the depth of the second undercut opening 220 can be equal to the depth of the first undercut opening 210, or due to process errors and other factors, the depth of the second undercut opening 220 is different from the depth of the first undercut opening 210, but the difference is not significant, and the depth of the second undercut opening 220 can be regarded as the depth of the first undercut opening 210.

[0080] S60. Obtain the capacitance after etching between the first test electrode 12 and the second test electrode 41 through the first test terminal 13 and the second test terminal 42, so as to obtain the depth of the second undercut opening 220.

[0081] Specifically, the specific steps for obtaining the depth of the second undercut opening 220 may include:

[0082] Obtain the width L of the second insulator portion 22 along the first direction X and the thickness of the second insulator portion 22, where the first direction X is perpendicular to the depth direction of the second undercut opening 220. It should be noted that in step S20, when the second insulator portion 22 is formed, the width L of the second insulator portion 22 along the first direction X and the thickness d of the second insulator portion 22 can be obtained through a measuring instrument; in addition, the second insulator portion 22 has set parameters before being formed, and the width L and the thickness d can also be directly obtained through the set parameters.

[0083] Obtain the pre-etching length W1 of the second insulator portion 22 along the second direction Y before the insulating layer 20 is etched, where the second direction Y is the depth direction of the second undercut opening 220.

[0084] In an embodiment of the present invention, in step S20, an optical line width measuring instrument can be used to measure the pre-etching length W1. It should be noted that the length of the second test electrode 41 along the second direction Y can also be obtained through a measuring instrument and regarded as the pre-etching length W1.

[0085] In another embodiment of the present invention, before step S50, two probes of a capacitance testing instrument can be respectively connected to the first test terminal 13 and the second test terminal 42 to measure the pre-etching capacitance C1 between the first test electrode 12 and the second test electrode 41;

[0086] The pre-etching length is obtained according to the formula shown below;

[0087]

[0088] Where k is the electrostatic constant. And the thickness d and the width L are known parameters. The pre-etching capacitance C1 can be obtained through the capacitance testing instrument. Then, by substituting the pre-etching capacitance C1, the thickness d, the width L, and the electrostatic constant k into the above formula, the pre-etching length W1 can be obtained.

[0089] The post-etching capacitance C2 between the first test electrode 12 and the second test electrode 41 after the etching treatment of the insulating layer 20 is obtained through the first test terminal 13 and the second test terminal 42.

[0090] The depth of the second undercut opening 220 is determined according to the width L of the second insulator portion in the first direction, the thickness d of the second insulator portion, the pre-etching length W1, and the post-etching capacitance C2.

[0091] Where two probes of the capacitance testing instrument are respectively connected to the first test terminal 13 and the second test terminal 42 to measure the post-etching capacitance C2 between the first test electrode 12 and the second test electrode 41.

[0092] The post-etching length W2 of the second insulator portion in the first direction X is obtained according to the formula shown below;

[0093]

[0094] Where the post-etching capacitance C2, the thickness d, the width L, and the electrostatic constant k are substituted into the above formula, and the post-etching length W2 can be obtained.

[0095] The difference obtained by subtracting the post-etching length W2 from the pre-etching length W1 is the depth of the second undercut opening 220. And in the implementation of the present invention, the depth of the second undercut opening 220 is the depth of the first undercut opening 210.

[0096] It should be noted that in the embodiments of the present invention, a first test electrode 12, a second insulator portion 22, a second test electrode 41, a first connection portion 14, and a second connection portion 44 can form a test unit, and this test unit can be located within the non-display area BA and distributed on the periphery of the display area AA. Optionally, the number of such test units can be multiple. The average value of the depths of the second undercut openings 220 obtained from the tests on multiple test units can be calculated, and then the depth of the first undercut opening 210 can be regarded as the average value of the depths of the multiple second undercut openings 220.

[0097] In other embodiments of the present invention, the non-display area BA of the display panel further includes the cutting area during the manufacturing process of the display panel. That is, the above-mentioned test unit can be fabricated within the cutting area of the display panel. Then, after obtaining the depth of the second undercut opening 220 (i.e., the first undercut opening 210), the above-mentioned test unit can be cut and removed during the cutting process to reduce the occupied area of the non-display area BA of the subsequent display panel, that is, the screen-to-body ratio of the display panel can be increased.

[0098] Furthermore, please refer to Figure 5 , which is a measurement system provided by the embodiments of the present invention for measuring the depth of the second undercut opening 220 (i.e., the first undercut opening 210) in the display panel described in the above embodiments.

[0099] Specifically, please combine Figure 2 , Figure 3 and Figure 5 . This measurement system can include a measurement unit 71, a storage unit 72, and a calculation unit 73. Among them, the measurement unit 71 can include the capacitance test instrument and the optical linewidth measurement instrument in the above embodiments. The optical linewidth measurement instrument can measure and obtain the pre-etching length W1 and store the obtained pre-etching length W1 in the storage unit 72. The storage unit 72 can previously obtain and store the thickness d, width L, and electrostatic constant k through process preset parameters. The capacitance test instrument can measure and obtain the post-etching capacitance C2, and then the above-mentioned measured or stored data can be transmitted to the calculation unit 73. The calculation unit 73 calculates the post-etching length W2 based on the post-etching capacitance C2, thickness d, width L, and electrostatic constant k, and the calculation unit 73 can calculate the difference between the pre-etching length W1 and the post-etching length W2 to obtain the depth of the second undercut opening 220 (i.e., the first undercut opening 210).

[0100] Alternatively, the capacitance testing instrument can measure and obtain the capacitance C1 before etching and the capacitance C2 after etching. The storage unit 72 can obtain and store the thickness d, width L, and electrostatic constant k in advance through process preset parameters, and then transmit the measured or stored data to the calculation unit 73. The calculation unit 73 calculates the length W1 before etching and the length W2 after etching based on the capacitance C1 before etching, the capacitance C2 after etching, the thickness d, the width L, and the electrostatic constant k. Moreover, the calculation unit 73 can calculate the difference based on the length W1 before etching and the length W2 after etching to obtain the depth of the second undercut opening 220 (i.e., the first undercut opening 210).

[0101] It should be noted that the above thickness d and width L can be obtained according to the process preset parameters or measured by a measuring instrument during the manufacturing process and stored in the storage unit 72, which is not limited herein.

[0102] In summary, in the embodiment of the present invention, an auxiliary electrode 11 is formed in the display area AA. An opening 201 is formed in the first insulator portion 21 corresponding to the auxiliary electrode 11, which can expose the auxiliary electrode 11. And at the opening 201, a first undercut opening 210 located between the spacer layer 30 and the auxiliary electrode 11 is provided in the first insulator portion 21. At the same time, in the non-display area BA of the present invention, a first test electrode 12 and a first test terminal 13 of the same layer as the auxiliary electrode 11, a second insulator portion 22 of the same layer as the first insulator portion 21, and a second test electrode 41 and a second test terminal 42 are formed. Among them, the first test electrode 12, the second insulator portion 22, and the second test electrode layer 41 are stacked to form a capacitance structure. The first test electrode 12 is electrically connected to the first test terminal 13, the second test electrode 41 is electrically connected to the second test terminal 42, and a second undercut opening 220 located between the second test electrode 41 and the first test electrode 12 is provided in the second insulator portion 22. Furthermore, the capacitance between the first test electrode 12 and the second test electrode 41 can be measured through the first test terminal 13 and the second test terminal 42, and the size of the second insulator portion 22 can be obtained according to the capacitance calculation formula. According to the difference between the size of the second insulator portion 22 before etching and the size after etching, the depth of the second undercut opening 220 can be obtained. And since the second insulator portion 22 is prepared on the same layer as the first insulator portion 21, the depth of the second undercut opening 220 can be regarded as the depth of the first undercut opening 210. Moreover, the depth of the first undercut opening 210 can be obtained without scrapping and splitting the display panel, reducing the production cost.

[0103] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0104] The above has introduced in detail a display panel and a manufacturing method thereof provided by an embodiment of the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area adjacent to the display area; The display panel further includes: A first conductive layer, including a plurality of auxiliary electrodes disposed in the display area, and at least one first test electrode and at least one first test terminal disposed in the non-display area, and one of the first test electrodes is electrically connected to one of the first test terminals; An insulating layer, disposed on one side of the first conductive layer, and including a first insulator portion disposed in the display area and a second insulator portion disposed in the non-display area, the first insulator portion includes a plurality of openings, and one of the openings corresponds to one of the auxiliary electrodes, and one of the second insulator portions is disposed on one side of one of the first test electrodes; A spacer layer, disposed at least on a side of the first insulator portion away from the first conductive layer; A second conductive layer, disposed on a side of the spacer layer away from the insulating layer, and including at least one second test electrode and at least one second test terminal disposed in the non-display area, and one of the second test electrodes is electrically connected to one of the second test terminals, and one of the second test electrodes is disposed on a side of one of the second insulator portions away from the corresponding one of the first test electrodes; Wherein, at the opening, a first undercut opening located between the spacer layer and the auxiliary electrode is provided in the first insulator portion, and a second undercut opening located between the second test electrode and the first test electrode is provided in the second insulator portion.

2. The display panel according to claim 1, wherein The spacer layer includes a first sub-portion disposed on a side of the first insulator portion away from the first conductive layer, and a second sub-portion connected to the first sub-portion and extending above the auxiliary electrode relative to the first sub-portion, wherein the distance that the second sub-portion extends above the auxiliary electrode relative to the first sub-portion is equal to the depth of the first undercut opening and equal to the depth of the second undercut opening.

3. The display panel according to claim 2, wherein The spacer layer further includes a third sub-portion disposed in the non-display area and connected to the second insulator portion, the second test terminal is disposed on a side of the third sub-portion away from the first conductive layer, and a surface of the third sub-portion away from the first conductive layer is flush with a surface of the second insulator portion away from the first test electrode.

4. The display panel according to claim 3, characterized in that, The first conductive layer further includes a first connection portion, the first connection portion is connected between the first test electrode and the first test terminal, the second conductive layer further includes a second connection portion disposed on a side of the third sub-portion away from the first conductive layer, and the second connection portion is connected between the second test electrode and the second test terminal.

5. The display panel according to claim 2, characterized in that, The first conductive layer further includes a plurality of source electrodes and a plurality of drain electrodes disposed in the display area, the second conductive layer further includes a plurality of anodes disposed on a side of the first sub-portion away from the first insulator portion, and one of the anodes is electrically connected to one of the drain electrodes.

6. A method for manufacturing a display panel, characterized in that, The display panel includes a display area and a non-display area adjacent to the display area, and a manufacturing method of the display panel includes the following steps: Form a first conductive layer, where the first conductive layer includes a plurality of auxiliary electrodes formed in the display area, at least one first test electrode and at least one first test terminal formed in the non-display area, and one of the first test electrodes is electrically connected to one of the first test terminals; Form an insulating layer on one side of the first conductive layer, where the insulating layer includes a first insulator portion formed in the display area and a second insulator portion formed in the non-display area. The first insulator portion includes a plurality of openings, and one of the openings corresponds to one of the auxiliary electrodes. A second insulator portion is formed on one side of one of the first test electrodes; Form a spacer layer at least on the side of the first insulator portion away from the first conductive layer; Form a second conductive layer on the side of the spacer layer away from the insulating layer. The second conductive layer includes at least one second test electrode and at least one second test terminal formed in the non-display area, and one of the second test electrodes is electrically connected to one of the second test terminals. One of the second test electrodes is formed on the side of one of the second insulator portions away from the corresponding one of the first test electrodes; Etch the insulating layer so that at the openings, a first undercut opening located between the spacer layer and the auxiliary electrode is formed in the first insulator portion, and a second undercut opening located between the second test electrode and the first test electrode is formed in the second insulator portion; Obtain the capacitance after etching between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening.

7. The manufacturing method of the display panel according to claim 6, characterized in that, Before the step of obtaining the capacitance after etching between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening, the following steps are further included: Obtain the width of the second insulator portion in a first direction and the thickness of the second insulator portion, where the first direction is perpendicular to the depth direction of the second undercut opening; Obtain the pre-etching length of the second insulator portion in a second direction before the insulating layer is etched, where the second direction is the depth direction of the second undercut opening; The step of obtaining the capacitance after etching between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening further includes the following steps: Determine the depth of the second undercut opening according to the width of the second insulator portion in the first direction, the thickness of the second insulator portion, the pre-etching length, and the capacitance after etching.

8. The manufacturing method of the display panel according to claim 7, characterized in that, The step of obtaining the pre-etching length of the second insulator portion in the second direction before the insulating layer is etched includes the following steps: Before the insulating layer is etched, measure the pre-etching length using an optical line width measuring instrument.

9. The manufacturing method of the display panel according to claim 7, wherein The step of obtaining the pre-etching length of the second insulator portion in the second direction before the insulating layer is etched includes the following steps: Before etching the insulating layer, connect two probes of a capacitance testing instrument to the first test terminal and the second test terminal respectively to measure the capacitance before etching between the first test electrode and the second test electrode; Obtain the length before etching according to the formula shown below; wherein, W1 is the length before etching, C1 is the capacitance before etching, d is the thickness of the second insulator portion, k is the electrostatic constant, and L is the width of the second insulator portion in the first direction.

10. The manufacturing method of the display panel according to claim 7, wherein The steps of obtaining the capacitance after etching between the first test electrode and the second test electrode through the first test terminal and the second test terminal to determine the depth of the second undercut opening further include the following steps: After etching the insulating layer, connect two probes of a capacitance testing instrument to the first test terminal and the second test terminal respectively to measure the capacitance after etching between the first test electrode and the second test electrode; Obtain the length after etching of the second insulator portion in the first direction according to the formula shown below; wherein, W2 is the length after etching, C2 is the capacitance after etching, d is the thickness of the second insulator portion, k is the electrostatic constant, and L is the width of the second insulator portion in the first direction; Determine the depth of the second undercut opening according to the length before etching and the length after etching.

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