Motor control method, motor controller, motor, and storage medium

Abstract

The application discloses a motor control method, a motor controller, a motor and a storage medium. The method comprises the following steps: in each carrier cycle of motor vector control, a comparison value is determined and stored in a buffer memory, and the comparison value comprises a PWM modulation comparison value; and the PWM modulation comparison value in the buffer memory is updated to a modulation comparison register through a DMA controller, so that a PWM control signal is generated according to the updated modulation comparison register. Therefore, the updating of the comparison register is realized in a hardware mode through the DMA controller, the problem of low software efficiency caused by the updating of the comparison register through a software interrupt is avoided, and the efficiency of the whole software and the stability of the software architecture are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of motor control, and in particular to a motor control method, a motor controller, a motor and a storage medium. BACKGROUND

[0002] In recent years, brushless DC motors are increasingly widely used in industry and consumer electronics technology. Compared with brush DC motors, brushless DC motors have simpler structure, higher power density, more stable and reliable operation, and better speed regulation performance. When vector control is performed on a brushless DC motor, a single-resistor sampling technique is generally used to obtain current data of the motor. For some cost-sensitive motor applications, such as vacuum cleaners and high-speed hair dryers, using a single resistor can save a sampling resistor and an operational amplifier circuit, thereby saving material costs and having strong practicality and economy.

[0003] When a single-resistor sampling technique is used to obtain current data of the motor, it is necessary to ensure that the PWM (Pulse Width Modulation) control signal is a non-symmetrical PWM control signal. However, since each channel of the advanced timer of a general-purpose MCU (micro control unit) can only implement symmetrical PWM function, and since the main frequency of the general-purpose MCU is only 48MHz, in order to fully utilize the chip resources, the main interrupt of the motor only generates an update interrupt of the advanced timer at the overflow of each carrier cycle, and therefore the advanced timer cannot complete the update of the comparison register twice in its own update interrupt, resulting in the inability to generate the non-symmetrical PWM control signal required by single-resistor sampling.

[0004] In related technologies, a general timer is used as an auxiliary timer, and the same counting period, counting mode and counting rhythm as the advanced timer are used for counting, so as to generate a synchronous interrupt at the overflow and overflow of each carrier cycle, respectively, and update the comparison register of the advanced timer through the two synchronous interrupts, so as to realize the generation of the non-symmetrical PWM control signal. However, this method can only realize the phase shift of the PWM control signal in software, and there will be two synchronous interrupts with higher priority than the main interrupt in the software architecture to interrupt the main interrupt twice in a carrier cycle to perform the phase shift operation, resulting in low efficiency of the entire software. SUMMARY

[0005] The present application aims to at least partially solve one of the technical problems in the related art. To this end, the first object of the present application is to propose a motor control method, which realizes the update of the comparison register in a hardware manner through a DMA controller, avoids the problem of low software efficiency caused by updating the comparison register through a software interrupt, and effectively improves the efficiency of the entire software and the stability of the software architecture.

[0006] A second object of the present application is to provide a computer-readable storage medium.

[0007] A third object of the present application is to provide a motor controller.

[0008] A fourth object of the present application is to provide a motor.

[0009] To achieve the above objects, the first aspect of the present application provides a motor control method, comprising: determining comparison values and storing the comparison values to a buffer memory in each carrier period of motor vector control, the comparison values including PWM modulation comparison values; updating the PWM modulation comparison values in the buffer memory to modulation comparison registers by a DMA controller, so as to generate PWM control signals according to the updated modulation comparison registers.

[0010] The motor control method according to the embodiment of the present application determines PWM modulation comparison values and stores the PWM modulation comparison values to a buffer memory in each carrier period of motor vector control, and updates the PWM modulation comparison values in the buffer memory to modulation comparison registers by a DMA controller, so as to generate PWM control signals according to the updated modulation comparison registers. Thus, the updating of the comparison registers is realized by the DMA controller in a hardware manner, avoiding the problem of low software efficiency caused by updating the comparison registers through software interrupts, and effectively improving the efficiency of the entire software and the stability of the software architecture.

[0011] According to an embodiment of the present application, the comparison values further include current sampling comparison values, and the method further comprises: updating the current sampling comparison values in the buffer memory to sampling comparison registers by the DMA controller, so as to perform current sampling according to the updated sampling comparison registers.

[0012] According to an embodiment of the present application, the method further comprises: generating an update interrupt at an underflow of each carrier period, and determining comparison values of a next carrier period and storing the comparison values to the buffer memory by a processor in the update interrupt.

[0013] According to an embodiment of the present application, the comparison values include a first group of comparison values and a second group of comparison values, the first group of comparison values corresponding to a left half period of the carrier period, and the second group of comparison values corresponding to a right half period of the carrier period, and the method further comprises: generating a first DMA request at an underflow of the next carrier period, and updating the first group of comparison values in the buffer memory to corresponding comparison registers by the DMA controller based on the first DMA request; generating a second DMA request at an overflow of the next carrier period, and updating the second group of comparison values in the buffer memory to corresponding comparison registers by the DMA controller based on the second DMA request.

[0014] According to an embodiment of the present application, the first DMA request and the second DMA request are both DMA Burst requests.

[0015] According to an embodiment of the present application, the time for the second group of comparison values to be updated to the corresponding comparison registers is ahead of the time for the comparison values to be stored to the buffer memory in the next carrier period.

[0016] According to an embodiment of the present application, the PWM control signal is generated according to the updated modulation comparison registers, including: comparing the count value corresponding to the carrier period with the value of the modulation comparison register; determining that the count value is equal to the value of the modulation comparison register, flipping the current signal level, otherwise keeping the current signal level unchanged, to generate the PWM control signal.

[0017] According to an embodiment of the present application, the modulation comparison registers include three, and each modulation comparison register corresponds to a PWM control signal.

[0018] According to an embodiment of the present application, the current sampling is performed according to the updated sampling comparison registers, including: comparing the count value corresponding to the carrier period with the value of the sampling comparison register; determining that the count value is equal to the value of the sampling comparison register, to perform the current sampling.

[0019] According to an embodiment of the present application, the sampling comparison registers include a first sampling comparison register and a second sampling comparison register, and the count value is determined to be equal to the value of the first sampling comparison register or the second sampling comparison register to perform the current sampling.

[0020] To achieve the above object, the second aspect of the present application provides a computer readable storage medium, which stores a motor control program, and the motor control program is executed by a processor to implement the motor control method.

[0021] The computer readable storage medium according to the embodiment of the present application adopts the motor control method, and the update of the comparison registers is realized by the DMA controller in a hardware manner, thereby avoiding the problem of low software efficiency caused by updating the comparison registers through software interruption, and effectively improving the efficiency of the whole software and the stability of the software architecture.

[0022] To achieve the above object, the third aspect of the present application provides a motor controller, including: a processor, configured to determine comparison values and store the comparison values to a buffer memory in each carrier period of motor vector control, the comparison values including PWM modulation comparison values; and a DMA controller, configured to update the PWM modulation comparison values in the buffer memory to modulation comparison registers, so as to generate a PWM control signal according to the updated modulation comparison registers.

[0023] The motor controller according to the embodiment of the present application determines the PWM modulation comparison value in each carrier cycle of motor vector control through the processor and stores the PWM modulation comparison value to the buffer memory, and updates the PWM modulation comparison value in the buffer memory to the modulation comparison register through the DMA controller, so as to generate the PWM control signal according to the updated modulation comparison register. Thus, the update of the comparison register is realized by the DMA controller in a hardware manner, the problem of low software efficiency caused by the update of the comparison register through the software interrupt is avoided, and the efficiency of the whole software and the stability of the software architecture are effectively improved.

[0024] To achieve the above object, the fourth aspect of the present application provides a motor, comprising a motor body; a frequency converter, the frequency converter comprising an inverter circuit and the motor controller as described above, the motor controller being used to generate a PWM control signal to control the inverter circuit, so as to drive the motor body to operate through the inverter circuit.

[0025] The motor according to the embodiment of the present application adopts the motor controller as described above, the update of the comparison register is realized by the DMA controller in a hardware manner, the problem of low software efficiency caused by the update of the comparison register through the software interrupt is avoided, and the efficiency of the whole software and the stability of the software architecture are effectively improved.

[0026] Additional aspects and advantages of the present application will be given in part in the following description, become apparent from the following description, or be understood through practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 Generation of the asymmetric PWM control signal in the related art;

[0028] Figure 2 Flowchart of the motor control method according to one embodiment of the present application;

[0029] Figure 3 Generation of the asymmetric PWM control signal according to one embodiment of the present application;

[0030] Figure 4 Flowchart of the current sampling in the motor control method according to one embodiment of the present application;

[0031] Figure 5 Schematic diagram of the current sampling according to one embodiment of the present application;

[0032] Figure 6 Schematic diagram of the current sampling according to another embodiment of the present application;

[0033] Figure 7 Structural schematic diagram of the motor controller according to one embodiment of the present application;

[0034] Figure 8 Structure diagram of a motor controller according to another embodiment of the application;

[0035] Figure 9 Structure diagram of a motor according to an embodiment of the application. DETAILED DESCRIPTION

[0036] Embodiments of the present application are described in detail below with reference to the attached drawings, wherein the same or like reference numerals are used to represent the same or like elements or elements having the same or similar function throughout the several several views. The embodiments described below are exemplary and are intended to be illustrative of the present application, and are not to be construed as limiting the present application.

[0037] Before introducing the motor control method of the embodiments of the present application, the generation of the asymmetric PWM control signal in the related art is briefly described.

[0038] When the single-resistance sampling technology is used to obtain the current data of the motor, it is necessary to ensure that the PWM control signal is an asymmetric PWM control signal. However, since each channel of the advanced timer of the general-purpose MCU can only realize the symmetric PWM function, and since the main frequency of the general-purpose MCU is only 48MHz, in order to fully utilize the chip resources, the main interrupt of the motor only generates the update interrupt of the advanced timer at the underflow of each carrier cycle, and therefore the advanced timer cannot complete the update of the two comparison registers in its own update interrupt, resulting in the inability to generate the asymmetric PWM control signal required by the single-resistance sampling. Therefore, in the related art, the general timer is used as an auxiliary timer to assist the advanced timer to realize the two updates of the comparison registers, so as to realize the generation of the asymmetric PWM control signal.

[0039] Figure 1 Structure diagram of the generation of the asymmetric PWM control signal in the related art. As shown in FIG. 1, the general timer is used as an auxiliary timer, and the auxiliary timer counts in the same counting period, counting mode and counting rhythm as the advanced timer. Figure 1

[0040] ​The advanced timer generates an update interrupt at the underflow of each carrier period of the motor vector control (e.g., at A), in which the six PWM modulation comparison values of the next carrier period are obtained. It should be noted that, since the asymmetric PWM control signal is generated, in each carrier period, the left half period and the right half period, each PWM control signal corresponds to a PWM modulation comparison value, when the motor is a three-phase motor, the three PWM control signals correspond to six PWM modulation comparison values, and the asymmetric PWM control signal is exemplarily illustrated in the figure, and the corresponding two PWM modulation comparison values are D and E.

[0041] Then, in the next carrier period of the motor vector control, the auxiliary timer generates a synchronization interrupt 1 at the underflow of the carrier period (e.g., at B), in which the three PWM modulation comparison values of the left half period of the carrier period are updated to the three comparison registers (e.g., CCR1, CCR2 and CCR3) of the advanced timer; and generates a synchronization interrupt 2 at the overflow of the carrier period (e.g., at C), in which the three PWM modulation comparison values of the right half period of the carrier period are updated to the three comparison registers (e.g., CCR1, CCR2 and CCR3) of the advanced timer. In this way, in one carrier period, the comparison registers are updated twice, so that the generation of the non-PWM control signal can be realized.

[0042] However, this method can only realize the phase shift of the PWM control signal in software, and there are two synchronization interrupts with higher priority than the main interrupt in the software architecture, which will interrupt the main interrupt twice in one carrier period to perform the phase shift operation, resulting in low software efficiency. Therefore, an embodiment of the present application provides a motor control method, which realizes the update of the comparison registers by using the hardware mode of the DMA controller, avoids the problem of low software efficiency caused by updating the comparison registers by using the software interrupt, and effectively improves the efficiency of the entire software and the stability of the software architecture.

[0043] The motor control method provided by the embodiment of the present application will be described below with reference to the accompanying drawings.

[0044] Figure 2 The flowchart of the motor control method according to an embodiment of the present application is shown in FIG. 1. Figure 2 As shown in the figure, the motor control method can include the following steps.

[0045] In step S101, in each carrier period of the motor vector control, the comparison value is determined and stored in the buffer memory, and the comparison value includes the PWM modulation comparison value.

[0046] It should be noted that the buffer memory can be a RAM (Random Access Memory), and specifically can be a DMA (Direct Memory Access) buffer. The comparison value can be a PWM modulation comparison value, which is used to generate a PWM control signal.

[0047] When the motor is controlled by vector control, the PWM modulation comparison value required for the next carrier cycle can be calculated by a motor vector control algorithm in each carrier cycle, and stored in the buffer memory. For example, when the motor is a three-phase motor and the PWM control signal is an asymmetric PWM control signal, two PWM modulation comparison values are generated for each PWM control signal, and a total of six PWM modulation comparison values are generated.

[0048] Further, in some embodiments, an update interrupt is generated at the underflow of each carrier cycle, and in the update interrupt, the comparison value of the next carrier cycle is determined by the processor and stored in the buffer memory.

[0049] Specifically, as shown in Figure 3 The advanced timer can generate an update interrupt at the underflow of each carrier cycle (e.g., at A), so that in the update interrupt, the processor (e.g., CPU) calculates the PWM modulation comparison value (e.g., PWM modulation comparison values D and E, only one comparison value corresponding to one PWM control signal is shown here) of the next carrier cycle, and stores the calculated PWM modulation comparison value in the buffer memory.

[0050] It should be noted that the advanced timer includes a counter register, which is counted to generate a triangular wave carrier, and the period of the triangular wave carrier is the carrier cycle. The counter register can use a center-aligned counting mode, i.e., starting from 0 and counting up, when the count value is equal to the maximum count value corresponding to the carrier cycle minus 1, an upward overflow occurs, and the counter register is reloaded with the maximum count value, and then starts to count down until it reaches 1, an underflow occurs, and then the counter register is reloaded with 0 and starts the next round of counting. When the underflow occurs, the advanced timer generates an update interrupt, i.e., an update interrupt is generated at the underflow of the carrier cycle, and then in the update interrupt, the processor calculates the comparison value of the next carrier cycle and stores it in the buffer memory such as the DMA buffer.

[0051] In step S102, the PWM modulation comparison value in the buffer memory is updated to the modulation comparison register by the DMA controller, so that the PWM control signal is generated according to the updated modulation comparison register.

[0052] It should be noted that the advanced timer includes a compare register. When used to generate PWM control signals, it can be defined as a modulation compare register. Furthermore, when the motor is a three-phase motor, three PWM control signals need to be generated: the U-phase, V-phase, and W-phase PWM control signals. This requires three modulation compare registers, each corresponding to one PWM control signal. For ease of explanation, the three modulation compare registers are designated CCR1, CCR2, and CCR3.

[0053] After the PWM modulation comparison value is calculated and stored in the buffer memory via the update interrupt, the PWM modulation comparison value in the buffer memory can be updated to the modulation compare registers CCR1, CCR2, and CCR3 via the DMA controller, thereby generating the PWM control signal based on the updated modulation compare registers. It should be noted that the DMA controller, or direct memory access controller, allows direct data transfer between the buffer memory and the compare registers without the need for a processor (such as a CPU) to participate. This prevents interruptions to the main interrupt for motor vector control, effectively improving software efficiency.

[0054] Furthermore, in some embodiments, the comparison values ​​include a first group of comparison values ​​and a second group of comparison values, the first group of comparison values ​​corresponds to the left half of the carrier cycle, and the second group of comparison values ​​corresponds to the right half of the carrier cycle. The method also includes: generating a first DMA request at the underflow of the next carrier cycle, and based on the first DMA request, updating the first group of comparison values ​​in the buffer memory to the corresponding comparison register through the DMA controller; generating a second DMA request at the overflow of the next carrier cycle, and based on the second DMA request, updating the second group of comparison values ​​in the buffer memory to the corresponding comparison register through the DMA controller.

[0055] Specifically, when the motor is a three-phase motor and the PWM control signal is an asymmetric PWM control signal, the six PWM modulation comparison values ​​generated include three PWM modulation comparison values ​​corresponding to the left half of the carrier cycle and three PWM modulation comparison values ​​corresponding to the right half of the carrier cycle, respectively denoted as the first set of PWM modulation comparison values ​​and the second set of PWM modulation comparison values. When a counter register overflows, in addition to generating an update interrupt, a first DMA request is generated and sent to a DMA controller, which updates the first set of PWM modulation comparison values ​​in the buffer memory to the three modulation comparison registers CCR1, CCR2, and CCR3. When a counter register overflows, a second DMA request is generated (in this case, no update interrupt is generated) and sent to the DMA controller, which updates the second set of PWM modulation comparison values ​​in the buffer memory to the three modulation comparison registers CCR1, CCR2, and CCR3. In this way, the three modulation comparison registers can be updated twice within a single carrier cycle, thereby enabling the generation of an asymmetric PWM control signal.

[0056] Optionally, the first DMA request and the second DMA request may be DMA Burst requests, that is, DMA burst requests, which can update multiple comparison registers at one time, effectively improving the update speed of the comparison registers compared to updating only one comparison register at a time.

[0057] It should be noted that the time when the second set of comparison values ​​is updated to the corresponding comparison register is ahead of the time when the comparison values ​​are stored in the buffer memory in the next carrier cycle.

[0058] Specifically, if Figure 3 As shown, assuming that an update interrupt is generated at the underflow of the second carrier cycle (i.e., at A'), and the six PWM modulation comparison values ​​of the third carrier cycle are calculated in this update interrupt, since Field Oriented Control (FOC) execution requires nearly one carrier cycle, by the time the six PWM modulation comparison values ​​of the third carrier cycle are obtained and stored in the buffer memory, it is already close to the end of the second carrier cycle. During the second carrier cycle, the second DMA request occurs at the overflow of the second carrier cycle. Therefore, the time it takes to read the second set of PWM modulation comparison values ​​from the buffer register and update them to the modulation comparison register based on the second DMA request will be ahead of the time it takes to store the six PWM modulation comparison values ​​of the third carrier cycle in the buffer memory. Therefore, the update of the buffer memory will not affect the update of the comparison register.

[0059] It should be noted that, in order to avoid the update of the buffer memory affecting the update of the comparison register, the update of the buffer memory can also be limited to ensure that the time of updating the second set of comparison values to the corresponding comparison register is ahead of the time of storing the comparison values in the buffer memory in the next carrier cycle.

[0060] Further, in each carrier cycle, after each update of the modulation comparison register, the PWM control signal of the current carrier cycle is generated based on the value of the updated modulation comparison register.

[0061] In some embodiments, generating the PWM control signal according to the updated modulation comparison register includes: comparing the count value corresponding to the carrier cycle with the value of the modulation comparison register; determining that the count value is equal to the value of the modulation comparison register, and flipping the current signal level, otherwise keeping the current signal level unchanged, to generate the PWM control signal.

[0062] Specifically, taking a motor as a three-phase motor, a PWM control signal as an asymmetric PWM control signal, and an MCU as an STM32 as an example, the MCU includes a CPU and an advanced timer, the advanced timer includes a counter register CNT and three modulation comparison registers CCR1, CCR2 and CCR3, the counter register CNT is used to generate a triangular wave carrier, and the three modulation comparison registers CCR1, CCR2 and CCR3 are used to store PWM modulation comparison values.

[0063] When the motor is subjected to vector control, it is assumed that the current position is at the beginning of the second carrier cycle (i.e., A'), the count value of the counter register CNT decreases to 1, the counter register CNT is subjected to downward overflow, at this time, an update interrupt and a first DMA request are generated, in the update interrupt, the CPU performs FOC and calculates six PWM modulation comparison values of the third carrier cycle, after receiving the first DMA request, the DMA controller updates the three PWM modulation comparison values corresponding to the left half cycle of the second carrier cycle in the DMA buffer to the three modulation comparison registers CCR1, CCR2 and CCR3. The counter register CNT is reloaded as 0 and starts to count up from 0, during the counting up, when the count value is equal to the three PWM modulation comparison values stored in the three modulation comparison registers CCR1, CCR2 and CCR3, a comparison jump occurs once, as shown in FIG. 4, for one of the asymmetric PWM control signals, when the count value of the counter register CNT is equal to the PWM modulation comparison value D stored in the modulation comparison register CCR1 corresponding to the road, it jumps from low level to high level. Figure 3

[0064] ​When the count value of the counter register CNT increases to the maximum count value corresponding to the carrier period minus 1, the counter register CNT occurs upward overflow, at this time, the second DMA request is generated, and after receiving the second DMA request, the DMA controller updates the three PWM modulation comparison values corresponding to the right half cycle of the second carrier period in the DMA cache to the three modulation comparison registers CCR1, CCR2 and CCR3. The counter register CNT is reloaded as the maximum count value, and starts to count down from the maximum count value. During the counting down, when the count value is equal to the three PWM modulation comparison values stored in the three modulation comparison registers CCR1, CCR2 and CCR3, a comparison jump occurs, as shown in Figure 3 For one of the asymmetric PWM control signals, when the count value of the counter register CNT is equal to the PWM modulation comparison value E stored in the modulation comparison register CCR1 corresponding to the signal, it jumps from high level to low level.

[0065] Since the FOC needs to be executed for nearly one carrier period, at the end of the second carrier period, the six PWM modulation comparison values corresponding to the third carrier period will be calculated and stored in the DMA cache. When the count value of the counter register CNT decreases to 1, the counter register CNT occurs downward overflow, enters the third carrier period, and sequentially executes in turn until the motor control ends.

[0066] In the above embodiment, the double update event method is used to separate the update event of executing the FOC main interrupt and the update event of generating the MDA request, so as to realize the phase shift of the PWM control signal by using the hardware method, realize the generation of the asymmetric PWM control signal, save two synchronous interrupts, avoid the problem of low software efficiency caused by updating the comparison register through the software interrupt, and effectively improve the efficiency of the whole software and the stability of the software architecture.

[0067] Figure 4 For the flowchart of the motor control method according to another embodiment of the application, as shown in Figure 4 The motor control method can include:

[0068] In step S201, in each carrier period of motor vector control, the comparison value is determined and stored in the buffer memory, and the comparison value includes the current sampling comparison value.

[0069] It should be noted that when vector control is performed on the motor, the motor's current data needs to be obtained. Therefore, in each carrier cycle of the motor vector control, the current sampling comparison value is determined while determining the PWM modulation comparison value, which is used to collect the motor's phase current. Furthermore, when using a single-resistor sampling technique to obtain the motor's current data, two sampling requests need to be generated to the ADC (Analogue to Digital Conversion) in each carrier cycle. Current sampling is performed through the ADC, and accordingly, two current sampling comparison values ​​are required to generate two sampling requests. Therefore, when vector control is performed on the motor, the two current sampling comparison values ​​required for the next carrier cycle can be calculated by the motor vector control algorithm in each carrier cycle and stored in the buffer memory.

[0070] Furthermore, in some embodiments, an update interrupt is generated at the underflow of each carrier cycle, and within the update interrupt, a comparison value of the next carrier cycle is determined by the processor and stored in the buffer memory.

[0071] Specifically, if Figure 3 As shown, the advanced timer can generate an update interrupt at the underflow of each carrier cycle (such as at A), so that within the update interrupt, the current sampling comparison value required for the next carrier cycle can be calculated by the processor (such as the CPU) and the calculated current sampling comparison value can be stored in the buffer memory.

[0072] Furthermore, the advanced timer includes a counter register, which counts to generate a triangular wave carrier, as described above, wherein when the counter register overflows, the advanced timer generates an update interrupt, and then within the update interrupt, the processor calculates the current sampling comparison value of the next carrier cycle and stores it in a buffer memory such as a DMA cache.

[0073] In step S202 , the current sampling comparison value in the buffer memory is updated to the sampling comparison register via the DMA controller, so that current sampling is performed according to the updated sampling comparison register.

[0074] Specifically, after the current sampling comparison value is obtained by the update interrupt calculation and stored in the buffer memory, the current sampling comparison value in the buffer memory can be updated to the sampling comparison register through the DMA controller, so that current sampling can be performed according to the updated sampling comparison register.

[0075] Furthermore, in each carrier cycle, each time the sampling comparison register is updated, current sampling of the current carrier cycle is performed based on the value of the updated sampling comparison register.

[0076] In some embodiments, performing current sampling according to the updated sampling comparison register includes: comparing the count value corresponding to the carrier cycle with the value of the sampling comparison register; and performing current sampling when determining that the count value is equal to the value of the sampling comparison register.

[0077] It should be noted that the advanced timers of most MCUs currently include only four compare registers, three of which are needed to store PWM modulation comparison values ​​so as to generate PWM control signals based on the PWM modulation comparison values. Only one compare register is left to store the current sampling comparison value. However, since two sampling requests are required in each carrier cycle, two current sampling comparison values ​​are required.

[0078] In response to the above situation, in some embodiments, the current sampling comparison value can be first stored in the sampling comparison register, and the ADC can be triggered to perform current sampling through the current sampling comparison value. After the current sampling is completed, the value of the sampling comparison register can be modified in the interrupt to perform the next current sampling.

[0079] Specifically, refer to Figure 5 As shown, two current samplings can be performed in the right half of the carrier cycle. The first current sampling is triggered based on the current sampling comparison value in the sampling comparison register, and the second current sampling is set by interruption when the first current sampling is completed.

[0080] Specifically, when the count value of the counter register equals the current sampling comparison value, an ADC trigger signal is output to the ADC, and the ADC is initialized to set the sampling channel to current sampling. At the same time, the interrupt enable after sampling is completed is configured with a priority higher than the priority of the main interrupt, and then the ADC begins to perform the first current sampling. After the first current sampling is completed, the sampling channel is modified through the interrupt after sampling is completed, such as adding bus voltage sampling, and the value of the sampling comparison register is modified to the value corresponding to the second current sampling, and the relevant parameters of ADC_DMA are modified. Then, when the count value of the counter register equals the value corresponding to the second current sampling, the second current sampling is performed. After the second current sampling is completed, the sampling channel is reset to current sampling, and the value of the sampling comparison register is modified to the current sampling comparison value, and ADC_DMA is modified to the initial state to prevent data misalignment.

[0081] In this embodiment, two current samplings can be achieved through one sampling comparison register and one current sampling comparison value, but an ADC completion interrupt is required to trigger the second current sampling.

[0082] In other embodiments, a comparison register may be added, that is, two comparison registers may respectively store a current sampling comparison value to trigger the ADC to perform current sampling.

[0083] To simplify the description, the two comparison registers used for sampling are defined as the first sampling comparison register and the second sampling comparison register, which are respectively denoted as CCR4 and CCR5. Figure 6 As shown, the first sampling comparison register stores a first current sampling comparison value, which is used to trigger the first current sampling. The second sampling comparison register stores a second current sampling comparison value, which is used to trigger the second current sampling. When the count value of the counter register equals the first current sampling comparison value, an ADC trigger signal is output to the ADC, and the ADC performs the first current sampling. Then, when the count value of the counter register equals the second current sampling comparison value, an ADC trigger signal is output to the ADC, and the ADC performs the second current sampling. This achieves two current samplings within one carrier cycle.

[0084] Furthermore, in this embodiment, current sampling may be performed when it is determined that the count value of the counter register is equal to the value of the first sampling comparison register or the second sampling comparison register.

[0085] That is, OR logic can be used so that both the first sampling comparison register and the second sampling comparison register can trigger the ADC to perform current sampling. Specifically, when the count value of the counter register equals the first current sampling comparison value, the OR logic determines that the ADC needs to be triggered to perform a current sampling. The counter register then continues to count down. When the count value equals the second current sampling comparison value, the OR logic determines that the ADC needs to be triggered to perform a current sampling. In this way, the OR logic can generate a trigger signal to trigger the ADC to perform current sampling.

[0086] In the above embodiment, by using two comparison registers to perform a logical OR operation to form a current sampling trigger signal to trigger the ADC to perform current sampling, one ADC completion interrupt can be saved, thereby realizing two current samplings in one carrier cycle through hardware, further improving the execution efficiency of the software and streamlining the entire software architecture.

[0087] The following combination Figure 3 The motor control method according to the embodiment of the present invention is further described.

[0088] Specifically, the single-resistor sampling technology is adopted to control the three-phase motor, and the MCU includes a CPU and an advanced timer, and the advanced timer includes a counter register CNT, three modulation comparison registers CCR1, CCR2 and CCR3, and two sampling comparison registers CCR4 and CCR5, wherein the counter register CNT is used to generate a triangular wave carrier, the three modulation comparison registers CCR1, CCR2 and CCR3 are used to store PWM modulation comparison values, and the two sampling comparison registers CCR4 and CCR5 are used to store current sampling comparison values.

[0089] When the motor is controlled by the vector control, it is assumed that the current is at the start position of the second carrier period (i.e. A'), the count value of the counter register CNT decreases to 1, the counter register CNT overflows downward, at this time, an update interrupt and a first DMA request are generated, in the update interrupt, the CPU executes the FOC, and calculates six PWM modulation comparison values and two current sampling comparison values of the third carrier period by the single-resistor vector control algorithm. It should be noted that when the current is sampled by the single resistor, the current can be sampled twice in the left half period or the right half period of each carrier period, so the current sampling comparison values of the left half period and the right half period of each carrier period are the same, and accordingly, after the two current sampling comparison values are calculated in the update interrupt, the two values are copied to obtain four current sampling comparison values.

[0090] After the DMA controller receives the first DMA request, the three PWM modulation comparison values corresponding to the left half period of the second carrier period in the DMA cache are updated to the three modulation comparison registers CCR1, CCR2 and CCR3, and the two current sampling comparison values are updated to the two sampling comparison registers CCR4 and CCR5. The counter register CNT is reloaded as 0 and starts to count from 0, and during the counting process, when the count value is equal to the three PWM modulation comparison values stored in the three modulation comparison registers CCR1, CCR2 and CCR3, a comparison jump occurs, as shown in FIG. 4, for one of the asymmetric PWM control signals, when the count value of the counter register CNT is equal to the PWM modulation comparison value D stored in the modulation comparison register CCR1 corresponding to the signal, the signal jumps from low level to high level; when the count value is equal to one of the current sampling comparison values in the two sampling comparison registers CCR4 and CCR5, a sampling trigger signal is generated to trigger the ADC to sample the current, and since the current sampling comparison values of the two sampling comparison registers CCR4 and CCR5 are different, the current can be sampled twice in the left half period of the carrier period. Figure 3

[0091] ​When the count value of the counter register CNT increases to the maximum count value corresponding to the carrier period minus 1, the counter register CNT occurs upward overflow, at this time, the second DMA request is generated, after receiving the second DMA request, the DMA controller updates the three PWM modulation comparison values corresponding to the right half cycle of the second carrier period in the DMA cache to the three modulation comparison registers CCR1, CCR2 and CCR3, and updates the two current sampling comparison values to the two sampling comparison registers CCR4 and CCR5. The counter register CNT is reloaded as the maximum count value, and starts to count down from the maximum count value, during the counting down, when the count value is equal to the three PWM modulation comparison values stored in the three modulation comparison registers CCR1, CCR2 and CCR3, a comparison jump occurs once, as shown in the following table: Figure 3 As shown in the table, for one of the asymmetric PWM control signals, when the count value of the counter register CNT is equal to the PWM modulation comparison value E stored in the modulation comparison register CCR1 corresponding to the signal, it jumps from high level to low level; when the count value is equal to one of the current sampling comparison values in the two sampling comparison registers CCR4 and CCR5, a sampling trigger signal is generated to trigger the ADC to sample the current, since the current sampling comparison values of the two sampling comparison registers CCR4 and CCR5 are different, two current samplings can be performed in the right half cycle of the carrier period (it should be noted that one of the left half cycle and the right half cycle can be selected to perform two current samplings).

[0092] Since the FOC needs to be performed for nearly one carrier period, at the end of the second carrier period, the six PWM modulation comparison values and the two current sampling comparison values corresponding to the third carrier period are calculated and stored in the DMA cache. When the count value of the counter register CNT decreases to 1, the counter register CNT occurs downward overflow, enters the third carrier period, and sequentially performs the cycle.

[0093] In summary, according to the motor control method of the embodiment of the application, the updating of the comparison register is realized by the DMA controller in a hardware manner, avoiding the problem of low software efficiency caused by updating the comparison register through software interruption, effectively improving the efficiency of the entire software and the stability of the software architecture; the two current samplings are realized by the or operation of the two sampling comparison registers in a hardware manner, compared with setting the comparison value corresponding to the second current sampling after the ADC sampling is completed, the use of interruption is reduced, further improving the efficiency of the entire software and the stability of the software architecture.

[0094] The embodiment of the application also provides a computer readable storage medium, which stores a motor control program, and the motor control program is executed by a processor to realize the motor control method.

[0095] According to the computer-readable storage medium of an embodiment of the present invention, the aforementioned motor control method is adopted, and the update of the comparison register is realized in hardware through the DMA controller, thereby avoiding the problem of low software efficiency in updating the comparison register through software interrupts, and effectively improving the efficiency of the entire software and the stability of the software architecture.

[0096] An embodiment of the present invention further provides a motor controller.

[0097] Figure 7 is a schematic diagram of the structure of a motor controller according to an embodiment of the present invention, referring to Figure 7 As shown, the motor controller 100 may include: a processor 110, a DMA controller 120, a buffer memory 130, and a comparison register 140. The processor 110 is configured to determine a comparison value and store it in the buffer memory 130 within each carrier cycle of the motor vector control. The comparison value includes a PWM modulation comparison value. The DMA controller 120 is configured to update the PWM modulation comparison value in the buffer memory 130 to the modulation comparison register 140, so as to generate a PWM control signal according to the updated modulation comparison register 140.

[0098] In some embodiments, the comparison value also includes a current sampling comparison value, referring to Figure 8 As shown, the DMA controller 120 is further configured to update the current sampling comparison value in the buffer memory 130 to the sampling comparison register 150 , so as to perform current sampling according to the updated sampling comparison register 150 .

[0099] In some embodiments, the motor controller 100 further includes a counter register 160 for generating an update interrupt at an underflow of each carrier cycle. In the update interrupt, the processor 110 determines a comparison value for the next carrier cycle and stores the result in the buffer memory 130 .

[0100] In some embodiments, the comparison values ​​include a first group of comparison values ​​and a second group of comparison values, the first group of comparison values ​​corresponds to the left half of the carrier cycle, and the second group of comparison values ​​corresponds to the right half of the carrier cycle. The counter register 160 is also used to generate a first DMA request at the underflow of the next carrier cycle and to generate a second DMA request at the overflow of the next carrier cycle, wherein the DMA controller 120 is also used to update the first group of comparison values ​​in the buffer memory 130 to the corresponding comparison register based on the first DMA request, and to update the second group of comparison values ​​in the buffer memory 130 to the corresponding comparison register based on the second DMA request.

[0101] In some embodiments, the first DMA request and the second DMA request are both DMA Burst requests.

[0102] In some embodiments, the time of updating the second group of comparison values to the corresponding comparison registers is ahead of the time of storing the comparison values to the buffer memory 130 in the next carrier period.

[0103] In some embodiments, the counter register 160 is further configured to compare the count value corresponding to the carrier period with the value of the modulation comparison register 140; determine that the count value is equal to the value of the modulation comparison register 140, flip the current signal level, otherwise keep the current signal level unchanged, to generate the PWM control signal.

[0104] In some embodiments, the modulation comparison register 140 includes three, and each modulation comparison register 140 corresponds to one PWM control signal.

[0105] In some embodiments, the counter register 160 is further configured to compare the count value corresponding to the carrier period with the value of the sampling comparison register 150; determine that the count value is equal to the value of the sampling comparison register 150, generate a current trigger signal to perform current sampling.

[0106] In some embodiments, the sampling comparison register 150 includes a first sampling comparison register and a second sampling comparison register, and the determination that the count value is equal to the value of the first sampling comparison register or the second sampling comparison register generates a current trigger signal to perform current sampling.

[0107] It should be noted that details of the motor controller not disclosed in the present application can refer to details disclosed in the present application regarding the motor control method, which will not be described here in detail.

[0108] According to the motor controller of the embodiment of the present application, the processor determines the PWM modulation comparison value in each carrier period of motor vector control and stores it to the buffer memory, and the DMA controller updates the PWM modulation comparison value in the buffer memory to the modulation comparison register, so as to generate the PWM control signal according to the updated modulation comparison register. Thus, the DMA controller updates the comparison register in a hardware manner, avoids the low software efficiency problem of updating the comparison register through software interruption, and effectively improves the efficiency of the entire software and the stability of the software architecture.

[0109] The embodiment of the present application further proposes a motor.

[0110] Figure 9 The structure diagram of the motor according to an embodiment of the present application is shown. Referring to Figure 9As shown, the motor 200 comprises a motor body M and a frequency converter 210, the frequency converter 210 comprising an inverter circuit 211 and the aforementioned motor controller 100, the motor controller 100 being configured to generate a PWM control signal to control the inverter circuit 211 to drive the motor body M to operate through the inverter circuit 211.

[0111] According to the motor of the embodiment of the present application, the aforementioned motor controller is adopted, and the updating of the comparison register is realized in a hardware manner through the DMA controller, thereby avoiding the problem of low software efficiency in updating the comparison register through a software interrupt, and effectively improving the efficiency of the whole software and the stability of the software architecture.

[0112] It should be understood that portions of the application can be implemented with hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented with software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or a combination thereof, can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0113] It should be understood that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, which can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system that includes a processor, or other system that can fetch instructions from an instruction execution system, apparatus, or device and execute the instructions, or in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device, or in conjunction with these instruction execution systems, apparatus, or devices. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or more wires (electrical devices), a portable computer diskette (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). In addition, a computer-readable medium can even be paper or another suitable medium on which the program is printed, as the program can be electronically captured, for example, by optically scanning the paper or other medium, then electronically converting the captured program into a machine-readable form, and then storing the machine-readable form into a computer memory.

[0113] It should be understood that portions of the application can be implemented with hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented with software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or a combination thereof, can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0114] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the description of the application, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0115] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0116] In the application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and other terms should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0117] Although the embodiments of the application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the application.

Claims

1. A method of controlling an electric machine, characterized by, The method comprises: In each carrier cycle of motor vector control, a comparison value is determined and stored in a buffer memory, the comparison value comprising a PWM modulation comparison value; The PWM modulation comparison value in the buffer memory is updated to a modulation comparison register by a DMA controller, so as to generate a PWM control signal according to the updated modulation comparison register; the method further comprises: An update interrupt is generated at the overflow of the each carrier cycle, in the update interrupt, a comparison value of a next carrier cycle is determined by a processor and stored in a buffer memory, the comparison value comprising a first group of comparison values and a second group of comparison values, the first group of comparison values corresponding to a left half cycle of the carrier cycle, and the second group of comparison values corresponding to a right half cycle of the carrier cycle, the method further comprising: A first DMA request is generated at the overflow of the next carrier cycle, based on the first DMA request, the first group of comparison values in the buffer memory are updated to a corresponding comparison register by a DMA controller; A second DMA request is generated at the overflow of the next carrier cycle, based on the second DMA request, the second group of comparison values in the buffer memory are updated to a corresponding comparison register by a DMA controller.

2. The method of claim 1, wherein, The comparison value further comprises a current sampling comparison value, and the method further comprises: The current sampling comparison value in the buffer memory is updated to a sampling comparison register by a DMA controller, so as to perform current sampling according to the updated sampling comparison register.

3. The method of claim 1, wherein, The first DMA request and the second DMA request are both DMA Burst requests.

4. The method of claim 1, wherein, The time of updating the second group of comparison values to the corresponding comparison register is ahead of the time of storing the comparison value to the buffer memory in the next carrier cycle.

5. The method of claim 1, wherein, Generating the PWM control signal according to the updated modulation comparison register comprises: Comparing a count value corresponding to the carrier cycle with a value of the modulation comparison register; Determining that the count value is equal to the value of the modulation comparison register, flipping a current signal level, or otherwise keeping the current signal level unchanged, to generate the PWM control signal.

6. The method of claim 5, wherein, The modulation comparison register comprises three, and each modulation comparison register corresponds to a PWM control signal.

7. The method of claim 2, wherein, Performing current sampling according to the updated sampling comparison register comprises: Comparing a count value corresponding to the carrier cycle with a value of the sampling comparison register; Determining that the count value is equal to the value of the sampling comparison register, to perform current sampling.

8. The method of claim 7, wherein, The sampling comparison register comprises a first sampling comparison register and a second sampling comparison register, and determining that the count value is equal to the value of the first sampling comparison register or the second sampling comparison register, to perform current sampling.

9. A computer-readable storage medium, characterized in that, A motor control program is stored thereon, and the motor control program is executed by a processor to implement the motor control method according to any one of claims 1-8.

10. An electric machine controller characterized by The method comprises: A processor is configured to determine a comparison value in each carrier cycle of motor vector control and store the comparison value in a buffer memory, the comparison value comprising a PWM modulation comparison value; a DMA controller for updating the PWM modulation comparison values in the buffer memory to modulation comparison registers so as to generate PWM control signals according to the updated modulation comparison registers; a counter register for generating an update interrupt at an underflow of each carrier cycle, within the update interrupt, the processor determines comparison values for a next carrier cycle and stores to the buffer memory; the comparison values comprise a first set of comparison values and a second set of comparison values, the first set of comparison values correspond to a left half cycle of a carrier cycle, the second set of comparison values correspond to a right half cycle of the carrier cycle, the counter register is configured to generate a first DMA request at an underflow of the next carrier cycle and a second DMA request at an overflow of the next carrier cycle, the DMA controller is configured to update the first set of comparison values in the buffer memory to the corresponding modulation comparison registers based on the first DMA request, and update the second set of comparison values in the buffer memory to the corresponding modulation comparison registers based on the second DMA request.

11. An electric machine characterized by comprise: a motor body; a frequency converter, the frequency converter comprises an inverter circuit and a motor controller according to claim 10, the motor controller is configured to generate PWM control signals to control the inverter circuit to drive the motor body to operate through the inverter circuit.

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